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| U s e r ' s Ma n u a l , V 1 . 0 , J u n e 2 0 0 7 XC2000 Derivatives V o l u m e 2 ( o f 2 ): P e r i p h e r a l U n i t s M i c r o c o n t r o l l e rs P re li m in ar 1 6 / 3 2 - B i t S i n g l e -C h i p M i c r o c o n t r o l l e r w i t h 32-Bit Performance y Edition 2007-06 Published by Infineon Technologies AG 81726 Munich, Germany (c) 2007 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. U s e r ' s Ma n u a l , V 1 . 0 , J u n e 2 0 0 7 XC2000 Derivatives V o l u m e 2 ( o f 2 ): P e r i p h e r a l U n i t s M i c r o c o n t r o l l e rs P re li m in ar 1 6 / 3 2 - B i t S i n g l e -C h i p M i c r o c o n t r o l l e r w i t h 32-Bit Performance y XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary XC2xxx Revision History: V1.0, 2007-06 Previous Version(s): V0.1, 2007-03, Draft Version Page Subjects (major changes since last revision) We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com User's Manual V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Summary Of Chapters Summary Of Chapters This User's Manual consists of two Volumes, "System Units" and "Peripheral Units". For a quick overview this table of chapters summarizes both volumes, so you immediately can find the reference to the desired section in the corresponding document ([1] or [2]). Summary Of Chapters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0-1 [1] Table Of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0-3 [1] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 [1] Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 [1] Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 [1] Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 [1] Interrupt and Trap Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 [1] System Control Unit (SCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 [1] Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 [1] Dedicated Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 [1] The External Bus Controller EBC . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 [1] Startup Configuration and Bootstrap Loading . . . . . . . . . . . . . . . 10-1 [1] Debug System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 [1] Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 [1] Device Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 [1] The General Purpose Timer Units . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 [2] Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 [2] Analog to Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 [2] Capture/Compare Unit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 [2] Capture/Compare Unit 6 (CCU6) . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 [2] Universal Serial Interface Channel . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 [2] Controller Area Network (MultiCAN) Controller . . . . . . . . . . . . . . 20-1 [2] Keyword Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 [2] Register Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5 [2] User's Manual L-1 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Summary Of Chapters User's Manual L-2 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Table Of Contents Table Of Contents This User's Manual consists of two Volumes, "System Units" and "Peripheral Units". For your convenience this table of contents (and also the keyword and register index) lists both volumes, so you can immediately find the reference to the desired section in the corresponding document ([1] or [2]). Summary Of Chapters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0-1 [1] Table Of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0-3 [1] 1 1.1 1.2 1.3 1.4 2 2.1 2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 2.1.6 2.2 2.3 2.4 2.5 2.6 3 3.1 3.2 3.3 3.4 3.4.1 3.4.2 3.5 3.6 3.7 3.8 3.9 3.9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 [1] Members of the 16-bit Microcontroller Family . . . . . . . . . . . . . . . . . . . 1-3 [1] Summary of Basic Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 [1] Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 [1] Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 [1] Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 [1] Basic CPU Concepts and Optimizations . . . . . . . . . . . . . . . . . . . . . . . 2-2 [1] High Instruction Bandwidth/Fast Execution . . . . . . . . . . . . . . . . . . . 2-4 [1] Powerful Execution Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 [1] High Performance Branch-, Call-, and Loop-Processing . . . . . . . . . 2-6 [1] Consistent and Optimized Instruction Formats . . . . . . . . . . . . . . . . 2-7 [1] Programmable Multiple Priority Interrupt System . . . . . . . . . . . . . . 2-8 [1] Interfaces to System Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 [1] On-Chip System Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 [1] On-Chip Peripheral Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 [1] Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32 [1] Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33 [1] On-Chip Debug Support (OCDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34 [1] Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 [1] Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 [1] Special Function Register Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 [1] Data Memory Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 [1] Program Memory Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 [1] Program/Data SRAM (PSRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 [1] Non-Volatile Program Memory (Flash) . . . . . . . . . . . . . . . . . . . . . 3-13 [1] System Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 [1] IO Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 [1] External Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 [1] Crossing Memory Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 [1] Embedded Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 [1] Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 [1] L-3 V1.0, 2007-06 User's Manual XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary 3.9.2 3.9.3 3.9.4 3.9.5 3.9.6 3.9.7 3.9.8 3.9.9 3.10 3.10.1 3.10.2 3.10.3 3.10.4 3.11 3.11.1 3.11.2 3.11.3 3.12 3.12.1 4 4.1 4.2 4.2.1 4.2.2 4.2.3 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.4 4.5 4.5.1 4.5.2 4.6 4.7 4.7.1 4.7.2 4.7.3 4.7.4 4.7.5 4.8 Table Of Contents 3-20 [1] 3-22 [1] 3-25 [1] 3-35 [1] 3-38 [1] 3-45 [1] 3-47 [1] 3-49 [1] 3-50 [1] 3-50 [1] 3-52 [1] 3-67 [1] 3-69 [1] 3-70 [1] 3-71 [1] 3-72 [1] 3-76 [1] 3-77 [1] 3-78 [1] Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Details of Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . Data Integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protection Handling Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protection Handling Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEPROM Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Program Memory Control . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Startup, Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Error Reporting Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Retention Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stand-By RAM Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stand-By RAM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Marker Memory (MKMEM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Parity Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parity Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 [1] Components of the CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 [1] Instruction Fetch and Program Flow Control . . . . . . . . . . . . . . . . . . . . 4-5 [1] Branch Detection and Branch Prediction Rules . . . . . . . . . . . . . . . . 4-7 [1] Correctly Predicted Instruction Flow . . . . . . . . . . . . . . . . . . . . . . . . 4-7 [1] Incorrectly Predicted Instruction Flow . . . . . . . . . . . . . . . . . . . . . . . 4-9 [1] Instruction Processing Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 [1] Pipeline Conflicts Using General Purpose Registers . . . . . . . . . . . 4-13 [1] Pipeline Conflicts Using Indirect Addressing Modes . . . . . . . . . . . 4-15 [1] Pipeline Conflicts Due to Memory Bandwidth . . . . . . . . . . . . . . . . 4-17 [1] Pipeline Conflicts Caused by CPU-SFR Updates . . . . . . . . . . . . . 4-20 [1] CPU Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26 [1] Use of General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29 [1] GPR Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31 [1] Context Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-33 [1] Code Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-37 [1] Data Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39 [1] Short Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39 [1] Long Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-41 [1] Indirect Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-44 [1] DSP Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-46 [1] The System Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-52 [1] Standard Data Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-56 [1] L-4 V1.0, 2007-06 User's Manual XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary 4.8.1 4.8.2 4.8.3 4.9 4.9.1 4.9.2 4.9.3 4.9.4 4.9.5 4.9.6 4.9.7 4.9.8 4.9.9 4.9.10 4.9.11 4.10 5 5.1 5.2 5.3 5.4 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.5 5.6 5.7 5.8 5.9 5.10 5.11 6 6.1 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.2 Table Of Contents 4-60 [1] 4-60 [1] 4-62 [1] 4-64 [1] 4-65 [1] 4-65 [1] 4-66 [1] 4-66 [1] 4-66 [1] 4-66 [1] 4-67 [1] 4-67 [1] 4-68 [1] 4-70 [1] 4-72 [1] 4-74 [1] 16-bit Adder/Subtracter, Barrel Shifter, and 16-bit Logic Unit . . . . Bit Manipulation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiply and Divide Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Data Processing (MAC Unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . MAC Unit Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Representation of Numbers and Rounding . . . . . . . . . . . . . . . . . . The 16-bit by 16-bit Signed/Unsigned Multiplier and Scaler . . . . . Concatenation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . One-bit Scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The 40-bit Adder/Subtracter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Data Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Accumulator Shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The 40-bit Signed Accumulator Register . . . . . . . . . . . . . . . . . . . . The MAC Unit Status Word MSW . . . . . . . . . . . . . . . . . . . . . . . . . The Repeat Counter MRW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Constant Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt and Trap Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 [1] Interrupt System Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 [1] Interrupt Arbitration and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 [1] Interrupt Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 [1] Operation of the Peripheral Event Controller Channels . . . . . . . . . . 5-19 [1] The PECC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19 [1] The PEC Source and Destination Pointers . . . . . . . . . . . . . . . . . . 5-23 [1] PEC Transfer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 [1] Channel Link Mode for Data Chaining . . . . . . . . . . . . . . . . . . . . . . 5-27 [1] PEC Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28 [1] Prioritization of Interrupt and PEC Service Requests . . . . . . . . . . . . 5-30 [1] Context Switching and Saving Status . . . . . . . . . . . . . . . . . . . . . . . . 5-32 [1] Interrupt Node Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35 [1] External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36 [1] OCDS Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-38 [1] Service Request Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-39 [1] Trap Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-41 [1] System Control Unit (SCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 [1] Clock Generation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 [1] Wake-Up Clock Circuit (OSC_WU) . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 [1] High Precision Oscillator Circuit (OSC_HP) . . . . . . . . . . . . . . . . . . 6-3 [1] Phase-Locked Loop (PLL) Module . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 [1] Clock Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13 [1] External Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15 [1] CGU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 [1] Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33 [1] L-5 V1.0, 2007-06 User's Manual XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 6.2.8 6.2.9 6.2.10 6.3 6.3.1 6.3.2 6.3.3 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 6.4.6 6.4.7 6.4.8 6.5 6.5.1 6.5.2 6.5.3 6.5.4 6.5.5 6.5.6 6.5.7 6.6 6.6.1 6.6.2 6.7 6.7.1 6.8 6.8.1 6.8.2 6.8.3 6.8.4 6.9 6.9.1 Table Of Contents Reset Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33 [1] General Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33 [1] Coupling of Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-35 [1] Debug Reset Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36 [1] Example1: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36 [1] Example2: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36 [1] Example3: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36 [1] Reset Request Trigger Sources . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36 [1] Module Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-40 [1] Reset Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-41 [1] External Service Request (ESR) Pins . . . . . . . . . . . . . . . . . . . . . . . . 6-52 [1] General Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-52 [1] ESR Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-58 [1] ESR Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-63 [1] External Request Unit (ERU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-64 [1] Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-64 [1] ERU Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-66 [1] External Request Select Unit (ERSx; x = 0..3) . . . . . . . . . . . . . . . 6-72 [1] Event Trigger Logic (ETLx; x = 0..3) . . . . . . . . . . . . . . . . . . . . . . . 6-74 [1] Connecting Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-76 [1] Output Gating Unit (OGUy; y = 0..3) . . . . . . . . . . . . . . . . . . . . . . . 6-77 [1] ERU Output Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-81 [1] ERU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-83 [1] Power Supply and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-90 [1] Supply Watchdog (SWD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-91 [1] Monitoring the Voltage Level of a Core Domain . . . . . . . . . . . . . . 6-97 [1] Controlling the Voltage Level of a Core Domain . . . . . . . . . . . . . 6-115 [1] Handling the Power System . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-126 [1] Power State Controller (PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-128 [1] Operating a Power Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-130 [1] Power Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-134 [1] Global State Controller (GSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-156 [1] GSC Control Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-156 [1] GSC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-160 [1] Temperature Compensation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . 6-165 [1] Temperature Compensation Registers . . . . . . . . . . . . . . . . . . . . 6-166 [1] Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-168 [1] Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-168 [1] Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-168 [1] Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-169 [1] WDT Kernel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-173 [1] Wake-up Timer (WUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-176 [1] Wake-Up Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-177 [1] L-6 V1.0, 2007-06 User's Manual XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary 6.9.2 6.10 6.10.1 6.10.2 6.10.3 6.11 6.11.1 6.11.2 6.11.3 6.11.4 6.11.5 6.11.6 6.11.7 6.12 6.13 7 7.1 7.1.1 7.1.2 7.1.3 7.2 7.2.1 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.3.7 7.3.8 7.3.9 7.3.10 7.3.11 7.3.12 7.3.13 7.3.14 8 9 9.1 9.2 Table Of Contents 6-178 [1] 6-181 [1] 6-181 [1] 6-183 [1] 6-185 [1] 6-186 [1] 6-187 [1] 6-189 [1] 6-200 [1] 6-202 [1] 6-210 [1] 6-211 [1] 6-216 [1] 6-218 [1] 6-220 [1] WUT Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Protection Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . Miscellaneous System Control Registers . . . . . . . . . . . . . . . . . . SCU Interrupt and Trap Handling . . . . . . . . . . . . . . . . . . . . . . . . . . SCU Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCU Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . SCU Trap Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCU Trap Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . DPM_M Interrupt and Trap Support . . . . . . . . . . . . . . . . . . . . . . DPM_M Interrupt and Trap Registers . . . . . . . . . . . . . . . . . . . . . Alternate Interrupt Assignment Register . . . . . . . . . . . . . . . . . . . Identification Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCU Register Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 [1] General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 [1] Basic Port Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 [1] Input Stage Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 [1] Output Driver Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 [1] Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 [1] Description Scheme for the Port IO Functions . . . . . . . . . . . . . . . . 7-6 [1] Port Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 [1] Port Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 [1] Port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18 [1] Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-22 [1] Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-26 [1] Port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-33 [1] Port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-37 [1] Port 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-41 [1] Port 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-43 [1] Port 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-46 [1] Port 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-49 [1] Port 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-52 [1] Port 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-55 [1] Port 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-62 [1] Port 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-65 [1] Dedicated Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 [1] The External Bus Controller EBC . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 [1] External Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 [1] Timing Principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 [1] L-7 V1.0, 2007-06 User's Manual XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary 9.2.1 9.2.2 9.2.3 9.3 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 9.3.6 9.3.7 9.3.8 9.3.9 9.3.10 9.4 9.5 10 10.1 10.2 10.3 10.4 10.4.1 10.4.2 10.4.3 10.4.4 10.4.5 11 11.1 11.1.1 11.2 11.2.1 11.2.2 11.3 11.3.1 12 13 14 14.1 14.1.1 14.1.2 Table Of Contents Basic Bus Cycle Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 [1] Bus Cycle Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 [1] Bus Cycle Examples: Fastest Access Cycles . . . . . . . . . . . . . . . . . 9-9 [1] Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11 [1] Configuration Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11 [1] The EBC Mode Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13 [1] The EBC Mode Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15 [1] The Timing Configuration Registers TCONCSx . . . . . . . . . . . . . . 9-16 [1] The Function Configuration Registers FCONCSx . . . . . . . . . . . . . 9-19 [1] The Address Window Selection Registers ADDRSELx . . . . . . . . . 9-22 [1] Ready Controlled Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-25 [1] Access Control to LXBus Modules . . . . . . . . . . . . . . . . . . . . . . . . 9-27 [1] External Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-28 [1] Shutdown Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-32 [1] LXBus Access Control and Signal Generation . . . . . . . . . . . . . . . . . 9-33 [1] EBC Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-33 [1] Startup Configuration and Bootstrap Loading . . . . . . . . . . . . . . . 10-1 [1] Start-Up Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 [1] Internal Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 [1] External Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 [1] Bootstrap Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 [1] General Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 [1] Standard UART Bootstrap Loader . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 [1] Synchronous Serial Channel Bootstrap Loader . . . . . . . . . . . . . . 10-11 [1] CAN Bootstrap Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14 [1] Summary of Bootstrap Loader Modes . . . . . . . . . . . . . . . . . . . . . 10-17 [1] Debug System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Debug Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Routing of Debug Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OCDS Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Debug Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Debug Actions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cerberus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 [1] 11-2 [1] 11-3 [1] 11-5 [1] 11-7 [1] 11-8 [1] 11-9 [1] 11-9 [1] Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 [1] Device Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 [1] The General Purpose Timer Units . . . . . . . . . . . . . . . . . . . . . . . . . Timer Block GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPT1 Core Timer T3 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPT1 Core Timer T3 Operating Modes . . . . . . . . . . . . . . . . . . . . . L-8 14-1 [2] 14-2 [2] 14-4 [2] 14-8 [2] User's Manual V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary 14.1.3 14.1.4 14.1.5 14.1.6 14.1.7 14.2 14.2.1 14.2.2 14.2.3 14.2.4 14.2.5 14.2.6 14.2.7 14.2.8 14.2.9 14.3 15 15.1 15.2 15.3 15.4 15.5 15.6 15.7 15.8 16 16.1 16.1.1 16.1.2 16.1.3 16.1.4 16.1.5 16.1.6 16.1.7 16.1.8 16.1.9 16.2 16.2.1 16.2.2 16.2.3 16.2.4 16.2.5 Table Of Contents 14-15 [2] 14-18 [2] 14-27 [2] 14-30 [2] 14-31 [2] 14-32 [2] 14-34 [2] 14-38 [2] 14-41 [2] 14-44 [2] 14-48 [2] 14-53 [2] 14-56 [2] 14-57 [2] 14-58 [2] 14-60 [2] GPT1 Auxiliary Timers T2/T4 Control . . . . . . . . . . . . . . . . . . . . . GPT1 Auxiliary Timers T2/T4 Operating Modes . . . . . . . . . . . . . GPT1 Clock Signal Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPT1 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Control for GPT1 Timers . . . . . . . . . . . . . . . . . . . . . . . . Timer Block GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPT2 Core Timer T6 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . GPT2 Core Timer T6 Operating Modes . . . . . . . . . . . . . . . . . . . . GPT2 Auxiliary Timer T5 Control . . . . . . . . . . . . . . . . . . . . . . . . GPT2 Auxiliary Timer T5 Operating Modes . . . . . . . . . . . . . . . . . GPT2 Register CAPREL Operating Modes . . . . . . . . . . . . . . . . . GPT2 Clock Signal Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPT2 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Control for GPT2 Timers and CAPREL . . . . . . . . . . . . . KSCCFG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interfaces of the GPT Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 [2] Defining the RTC Time Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2 [2] RTC Run Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5 [2] RTC Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7 [2] 48-bit Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-11 [2] System Clock Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-11 [2] Cyclic Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12 [2] RTC Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13 [2] KSCCFG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15 [2] Analog to Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 [2] Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 [2] ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2 [2] Feature Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3 [2] Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4 [2] ADC Kernel Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5 [2] Conversion Request Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7 [2] Conversion Result Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-9 [2] Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10 [2] Electrical Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11 [2] Transfer Characteristics and Error Definitions . . . . . . . . . . . . . . . 16-14 [2] Operating the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-15 [2] Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-16 [2] Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-20 [2] Module Activation and Power Saving Modes . . . . . . . . . . . . . . . 16-22 [2] Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-23 [2] General ADC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-24 [2] L-9 V1.0, 2007-06 User's Manual XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary 16.2.6 16.2.7 16.2.8 16.2.9 16.2.10 16.2.11 16.2.12 16.2.13 16.2.14 16.2.15 16.2.16 16.2.17 16.2.18 16.3 16.3.1 16.3.2 16.3.3 16.3.4 17 17.1 17.2 17.3 17.3.1 17.4 17.5 17.5.1 17.5.2 17.5.3 17.5.4 17.5.5 17.6 17.7 17.8 17.9 17.10 17.10.1 17.11 18 18.1 18.1.1 18.1.2 18.1.3 Table Of Contents Request Source Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-33 [2] Arbiter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-37 [2] Scan Request Source Handling . . . . . . . . . . . . . . . . . . . . . . . . . . 16-39 [2] Scan Request Source Registers . . . . . . . . . . . . . . . . . . . . . . . . . 16-43 [2] Sequential Request Source Handling . . . . . . . . . . . . . . . . . . . . . 16-47 [2] Sequential Source Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-52 [2] Channel-Related Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-63 [2] Channel-Related Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-68 [2] Conversion Result Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-78 [2] Conversion Result-Related Registers . . . . . . . . . . . . . . . . . . . . . 16-86 [2] External Multiplexer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-96 [2] Synchronized Conversions for Parallel Sampling . . . . . . . . . . . . 16-98 [2] Additional Feature Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-102 [2] Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-105 [2] Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-105 [2] Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-105 [2] Analog Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-106 [2] Digital Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-109 [2] Capture/Compare Unit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 [2] The CAPCOM2 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 [2] CAPCOM2 Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10 [2] Capture/Compare Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11 [2] Capture/Compare Registers for the CAPCOM2 (CC31 ... CC16) 17-11 [2] Capture Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-14 [2] Compare Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-15 [2] Compare Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-16 [2] Compare Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-16 [2] Compare Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-19 [2] Compare Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-19 [2] Double-Register Compare Mode . . . . . . . . . . . . . . . . . . . . . . . . 17-24 [2] Compare Output Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . 17-27 [2] Single Event Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-29 [2] Staggered and Non-Staggered Operation . . . . . . . . . . . . . . . . . . . . 17-31 [2] CAPCOM2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-36 [2] External Input Signal Requirements . . . . . . . . . . . . . . . . . . . . . . . . 17-38 [2] KSCCFG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-39 [2] Interfaces of the CAPCOM Units . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-41 [2] Capture/Compare Unit 6 (CCU6) . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Feature Set Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . L-10 18-1 [2] 18-1 [2] 18-2 [2] 18-3 [2] 18-4 [2] User's Manual V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary 18.2 18.2.1 18.2.2 18.2.3 18.2.4 18.2.5 18.2.6 18.2.7 18.2.8 18.2.9 18.3 18.3.1 18.3.2 18.3.3 18.3.4 18.3.5 18.3.6 18.4 18.5 18.6 18.6.1 18.6.2 18.6.3 18.6.4 18.7 18.7.1 18.7.2 18.7.3 18.7.4 18.8 18.8.1 18.8.2 18.9 18.9.1 18.9.2 18.9.3 18.10 18.10.1 18.10.2 18.10.3 18.10.4 19 Table Of Contents Operating Timer T12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-8 [2] T12 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9 [2] T12 Counting Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-11 [2] T12 Compare Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-15 [2] Compare Mode Output Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-22 [2] T12 Capture Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-27 [2] T12 Shadow Register Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . 18-31 [2] Timer T12 Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . 18-32 [2] T12 related Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-33 [2] Capture/Compare Control Registers . . . . . . . . . . . . . . . . . . . . . . 18-38 [2] Operating Timer T13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-50 [2] T13 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-50 [2] T13 Counting Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-53 [2] T13 Compare Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-58 [2] Compare Mode Output Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-60 [2] T13 Shadow Register Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . 18-61 [2] T13 related Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-63 [2] Trap Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-66 [2] Multi-Channel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-68 [2] Hall Sensor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-70 [2] Hall Pattern Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-71 [2] Hall Pattern Compare Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-73 [2] Hall Mode Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-74 [2] Hall Mode for Brushless DC-Motor Control . . . . . . . . . . . . . . . . . 18-76 [2] Modulation Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-78 [2] Modulation Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-78 [2] Trap Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-80 [2] Passive State Level Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-83 [2] Multi-Channel Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 18-84 [2] Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-89 [2] Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-89 [2] Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-91 [2] General Module Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-103 [2] Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-103 [2] Input Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-106 [2] General Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-107 [2] Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-115 [2] Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-115 [2] Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-116 [2] Synchronous Start Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-117 [2] Digital Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-118 [2] Universal Serial Interface Channel . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 [2] L-11 V1.0, 2007-06 User's Manual XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary 19.1 19.1.1 19.1.2 19.1.3 19.1.4 19.1.5 19.1.6 19.1.7 19.2 19.2.1 19.2.2 19.2.3 19.2.4 19.2.5 19.2.6 19.2.7 19.2.8 19.2.9 19.2.10 19.2.11 19.2.12 19.2.13 19.2.14 19.3 19.3.1 19.3.2 19.3.3 19.3.4 19.3.5 19.4 19.4.1 19.4.2 19.4.3 19.4.4 19.4.5 19.4.6 19.5 19.5.1 19.5.2 19.5.3 19.5.4 19.5.5 19.6 Table Of Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 [2] Feature Set Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 [2] Channel Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5 [2] Input Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6 [2] Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-7 [2] Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-8 [2] Channel Events and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-9 [2] Data Shifting and Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-9 [2] Operating the USIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-13 [2] Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-13 [2] Operating the USIC Communication Channel . . . . . . . . . . . . . . . 19-17 [2] Channel Control and Configuration Registers . . . . . . . . . . . . . . . 19-28 [2] Protocol Related Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-37 [2] Operating the Input Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-40 [2] Input Stage Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-42 [2] Operating the Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . 19-44 [2] Baud Rate Generator Registers . . . . . . . . . . . . . . . . . . . . . . . . . 19-49 [2] Operating the Transmit Data Path . . . . . . . . . . . . . . . . . . . . . . . . 19-54 [2] Operating the Receive Data Path . . . . . . . . . . . . . . . . . . . . . . . . 19-58 [2] Transfer Control and Status Registers . . . . . . . . . . . . . . . . . . . . 19-60 [2] Data Buffer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-72 [2] Operating the FIFO Data Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . 19-82 [2] FIFO Buffer and Bypass Registers . . . . . . . . . . . . . . . . . . . . . . . 19-91 [2] Asynchronous Serial Channel (ASC = UART) . . . . . . . . . . . . . . . . 19-112 [2] Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-112 [2] Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-113 [2] Operating the ASC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-116 [2] ASC Protocol Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-124 [2] Hardware LIN Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-129 [2] Synchronous Serial Channel (SSC) . . . . . . . . . . . . . . . . . . . . . . . 19-130 [2] Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-130 [2] Operating the SSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-138 [2] Operating the SSC in Master Mode . . . . . . . . . . . . . . . . . . . . . . 19-141 [2] Operating the SSC in Slave Mode . . . . . . . . . . . . . . . . . . . . . . . 19-148 [2] SSC Protocol Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-150 [2] SSC Timing Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-154 [2] Inter-IC Bus Protocol (IIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-158 [2] Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-158 [2] Operating the IIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-162 [2] Symbol Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-168 [2] Data Flow Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-171 [2] IIC Protocol Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-176 [2] IIS Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-181 [2] L-12 V1.0, 2007-06 User's Manual XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary 19.6.1 19.6.2 19.6.3 19.6.4 19.6.5 19.7 19.7.1 19.7.2 19.7.3 19.7.4 19.7.5 20 20.1 20.1.1 20.1.2 20.2 20.2.1 20.2.2 20.2.3 20.2.4 20.2.5 20.2.6 20.2.7 20.2.8 20.2.9 20.2.10 20.2.11 20.2.12 20.3 20.3.1 20.3.2 20.3.3 20.3.4 20.4 20.4.1 20.4.2 20.4.3 20.4.4 20.4.5 20.4.6 20.4.7 Table Of Contents 19-181 [2] 19-185 [2] 19-190 [2] 19-194 [2] 19-195 [2] 19-199 [2] 19-199 [2] 19-200 [2] 19-200 [2] 19-201 [2] 19-203 [2] Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating the IIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating the IIS in Master Mode . . . . . . . . . . . . . . . . . . . . . . . Operating the IIS in Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . IIS Protocol Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USIC Implementation in XC2000 . . . . . . . . . . . . . . . . . . . . . . . . . . Implementation Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Channel Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input/Output Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Controller Area Network (MultiCAN) Controller . . . . . . . . . . . . . . 20-1 [2] MultiCAN Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 [2] Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 [2] CAN Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2 [2] CAN Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4 [2] Conventions and Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4 [2] Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4 [2] CAN Node Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-10 [2] Message Object List Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-14 [2] CAN Node Analysis Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-19 [2] Message Acceptance Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-22 [2] Message Postprocessing Interface . . . . . . . . . . . . . . . . . . . . . . . 20-25 [2] Message Object Data Handling . . . . . . . . . . . . . . . . . . . . . . . . . . 20-29 [2] Message Object Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-36 [2] MultiCAN Kernel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-45 [2] CAN Node Specific Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-62 [2] Message Object Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-79 [2] General Control and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-102 [2] Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-102 [2] Port Input Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-103 [2] Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-104 [2] Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-105 [2] MultiCAN Module Implementation . . . . . . . . . . . . . . . . . . . . . . . . . 20-106 [2] Interfaces of the CAN Module . . . . . . . . . . . . . . . . . . . . . . . . . . 20-106 [2] Module Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-107 [2] Mode Control Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-116 [2] Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-117 [2] Mode Control Register Description . . . . . . . . . . . . . . . . . . . . . . 20-119 [2] Connection of External Signals . . . . . . . . . . . . . . . . . . . . . . . . . 20-122 [2] MultiCAN Module Register Address Map . . . . . . . . . . . . . . . . . 20-125 [2] Keyword Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 [2] User's Manual L-13 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Table Of Contents Register Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5 [2] User's Manual L-14 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary The General Purpose Timer Units 14 The General Purpose Timer Units The General Purpose Timer Unit blocks GPT1 and GPT2 have very flexible multifunctional timer structures which may be used for timing, event counting, pulse width measurement, pulse generation, frequency multiplication, and other purposes. They incorporate five 16-bit timers that are grouped into the two timer blocks GPT1 and GPT2. Each timer in each block may operate independently in a number of different modes such as gated timer or counter mode, or may be concatenated with another timer of the same block. Each block has alternate input/output functions and specific interrupts associated with it. Block GPT1 contains three timers/counters: The core timer T3 and the two auxiliary timers T2 and T4. The maximum resolution is fGPT/4. The auxiliary timers of GPT1 may optionally be configured as reload or capture registers for the core timer. These registers are listed in Section 14.1.6. * * * * fGPT/4 maximum resolution 3 independent timers/counters Timers/counters can be concatenated 4 operating modes: - Timer Mode - Gated Timer Mode - Counter Mode - Incremental Interface Mode * Reload and Capture functionality * Separate interrupt lines Block GPT2 contains two timers/counters: The core timer T6 and the auxiliary timer T5. The maximum resolution is fGPT/2. An additional Capture/Reload register (CAPREL) supports capture and reload operation with extended functionality. These registers are listed in Section 14.2.7. The core timer T6 may be concatenated with timers of the CAPCOM units (T0, T1, T7, and T8). The following list summarizes the features which are supported: fGPT/2 maximum resolution 2 independent timers/counters Timers/counters can be concatenated 3 operating modes: - Timer Mode - Gated Timer Mode - Counter Mode * Extended capture/reload functions via 16-bit capture/reload register CAPREL * Separate interrupt lines * * * * User's Manual GPT_X7, V2.0 14-1 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary The General Purpose Timer Units 14.1 Timer Block GPT1 From a programmer's point of view, the GPT1 block is composed of a set of SFRs as summarized below. Those portions of port and direction registers which are used for alternate functions by the GPT1 block are shaded. Data Registers T2 T3 T4 Control Registers T2CON T3CON T4CON T2CON KSCFG T2CON Interrupt Control T2IC T3IC T4IC Tx TxCON TxIC KSCFG GPT1 Timer x Register GPT1 Capture/Reload Register GPT1 Timer x Interrupt Ctrl. Reg. Kernel State Configuration Register m c_gpt 1_regist ers.vsd Figure 14-1 SFRs Associated with Timer Block GPT1 All three timers of block GPT1 (T2, T3, T4) can run in one of 4 basic modes: Timer Mode, Gated Timer Mode, Counter Mode, or Incremental Interface Mode. All timers can count up or down. Each timer of GPT1 is controlled by a separate control register TxCON. Each timer has an input pin TxIN (alternate pin function) associated with it, which serves as the gate control in gated timer mode, or as the count input in counter mode. The count direction (up/down) may be programmed via software or may be dynamically altered by a signal at the External Up/Down control input TxEUD (alternate pin function). An overflow/underflow of core timer T3 is indicated by the Output Toggle Latch T3OTL, whose state may be output on the associated pin T3OUT (alternate pin function). The auxiliary timers T2 and T4 may additionally be concatenated with the core timer T3 (through T3OTL) or may be used as capture or reload registers for the core timer T3. The current contents of each timer can be read or modified by the CPU by accessing the corresponding timer count registers T2, T3, or T4, located in the non-bitaddressable SFR space (see Section 14.1.6). When any of the timer registers is written to by the CPU in the state immediately preceding a timer increment, decrement, reload, or capture operation, the CPU write operation has priority in order to guarantee correct results. User's Manual GPT_X7, V2.0 14-2 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary The General Purpose Timer Units The interrupts of GPT1 are controlled through the Interrupt Control Registers TxIC. These registers are not part of the GPT1 block. The input and output lines of GPT1 are connected to pins of ports P3 and P5. The control registers for the port functions are located in the respective port modules. Note: The timing requirements for external input signals can be found in Section 14.1.5, Section 14.3 summarizes the module interface signals, including pins. T3CON.BPS1 f GPT 2n: 1 Basic clock Interrupt Request (T2IRQ) Aux. Timer T2 T2IN T2EUD T2 Mode Control U/D Reload Capture Interrupt Request (T3IRQ) T3 Mode Control U/D T3EUD Capture Reload T4IN T4EUD T4 Mode Control U/D Toggle Latch Core Timer T3 T3OTL T3OUT T3IN Aux. Timer T4 Interrupt Request (T4IRQ) mc_gpt0101_bldiax1.vsd Figure 14-2 GPT1 Block Diagram (n = 2 ... 5) User's Manual GPT_X7, V2.0 14-3 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary The General Purpose Timer Units 14.1.1 GPT1 Core Timer T3 Control The current contents of the core timer T3 are reflected by its count register T3. This register can also be written to by the CPU, for example, to set the initial start value. The core timer T3 is configured and controlled via its bitaddressable control register T3CON. GPT12E_T3CON Timer 3 Control Register 15 14 13 T3 ED GE rwh 12 11 10 SFR (FF42H/A1H) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 T3 T3 R CH DIR DIR rh rwh BPS1 T3 T3 T3 T3 OTL OE UDE UD rwh rw rw rw T3R T3M T3I rw rw rw rw Field T3RDIR Bits 15 Type rh Description Timer T3 Rotation Direction Flag 0 Timer T3 counts up 1 Timer T3 counts down Timer T3 Count Direction Change Flag This bit is set each time the count direction of timer T3 changes. T3CHDIR must be cleared by SW. 0 No change of count direction was detected 1 A change of count direction was detected Timer T3 Edge Detection Flag The bit is set each time a count edge is detected. T3EDGE must be cleared by SW. 0 No count edge was detected 1 A count edge was detected GPT1 Block Prescaler Control Selects the basic clock for block GPT1 (see also Section 14.1.5) 00 fGPT/8 01 fGPT/4 10 fGPT/32 11 fGPT/16 T3CHDIR 14 rwh T3EDGE 13 rwh BPS1 [12:11] rw User's Manual GPT_X7, V2.0 14-4 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field T3OTL Bits 10 Type rwh Description Timer T3 Overflow Toggle Latch Toggles on each overflow/underflow of T3. Can be set or reset by software (see separate description) Overflow/Underflow Output Enable 0 Alternate Output Function Disabled 1 State of T3 toggle latch is output on pin T3OUT Timer T3 External Up/Down Enable1) 0 Input T3EUD is disconnected 1 Direction influenced by input T3EUD Timer T3 Up/Down Control1) 0 Timer T3 counts up 1 Timer T3 counts down Timer T3 Run Bit 0 Timer T3 stops 1 Timer T3 runs Timer T3 Mode Control (Basic Operating Mode) 000 Timer Mode 001 Counter Mode 010 Gated Timer Mode with gate active low 011 Gated Timer Mode with gate active high 100 Reserved. Do not use this combination. 101 Reserved. Do not use this combination. 110 Incremental Interface Mode (Rotation Detection Mode) 111 Incremental Interface Mode (Edge Detection Mode) Timer T3 Input Parameter Selection Depends on the operating mode, see respective sections for encoding: Table 14-7 for Timer Mode and Gated Timer Mode Table 14-2 for Counter Mode Table 14-3 for Incremental Interface Mode The General Purpose Timer Units T3OE 9 rw T3UDE 8 rw T3UD 7 rw T3R 6 rw T3M [5:3] rw T3I [2:0] rw 1) See Table 14-1 for encoding of bits T3UD and T3UDE. User's Manual GPT_X7, V2.0 14-5 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Timer T3 Run Control The core timer T3 can be started or stopped by software through bit T3R (Timer T3 Run Bit). This bit is relevant in all operating modes of T3. Setting bit T3R will start the timer, clearing bit T3R stops the timer. In gated timer mode, the timer will only run if T3R = 1 and the gate is active (high or low, as programmed). Note: When bit T2RC or T4RC in timer control register T2CON or T4CON is set, bit T3R will also control (start and stop) the auxiliary timer(s) T2 and/or T4. Count Direction Control The count direction of the GPT1 timers (core timer and auxiliary timers) can be controlled either by software or by the external input pin TxEUD (Timer Tx External Up/Down Control Input). These options are selected by bits TxUD and TxUDE in the respective control register TxCON. When the up/down control is provided by software (bit TxUDE = 0), the count direction can be altered by setting or clearing bit TxUD. When bit TxUDE = 1, pin TxEUD is selected to be the controlling source of the count direction. However, bit TxUD can still be used to reverse the actual count direction, as shown in Table 14-1. The count direction can be changed regardless of whether or not the timer is running. Note: When pin TxEUD is used as external count direction control input, it must be configured as input (its corresponding direction control bit must be cleared). Table 14-1 Pin TxEUD X X 0 1 0 1 GPT1 Timer Count Direction Control Bit TxUDE 0 0 1 1 1 1 Bit TxUD 0 1 0 0 1 1 Count Direction Count Up Count Down Count Up Count Down Count Down Count Up Bit TxRDIR 0 1 0 1 1 0 The General Purpose Timer Units User's Manual GPT_X7, V2.0 14-6 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Timer 3 Output Toggle Latch The overflow/underflow signal of timer T3 is connected to a block named `Toggle Latch', shown in the timer mode diagrams. Figure 14-3 illustrates the details of this block. An overflow or underflow of T3 will clock two latches: The first latch represents bit T3OTL in control register T3CON. The second latch is an internal latch toggled by T3OTL's output. Both latch outputs are connected to the input control blocks of the auxiliary timers T2 and T4. The output level of the shadow latch will match the output level of T3OTL, but is delayed by one clock cycle. When the T3OTL value changes, this will result in a temporarily different output level from T3OTL and the shadow latch, which can trigger the selected count event in T2 and/or T4. When software writes to T3OTL, both latches are set or cleared simultaneously. In this case, both signals to the auxiliary timers carry the same level and no edge will be detected. Bit T3OE (overflow/underflow output enable) in register T3CON enables the state of T3OTL to be monitored via an external pin T3OUT. When T3OTL is linked to an external port pin (must be configured as output), T3OUT can be used to control external HW. If T3OE = 1, pin T3OUT outputs the state of T3OTL. If T3OE = 0, pin T3OUT outputs a high level (as long as the T3OUT alternate function is selected for the port pin). The trigger signals can serve as an input for the counter function or as a trigger source for the reload function of the auxiliary timers T2 and T4. As can be seen from Figure 14-3, when latch T3OTL is modified by software to determine the state of the output line, also the internal shadow latch is set or cleared accordingly. Therefore, no trigger condition is detected by T2/T4 in this case. The General Purpose Timer Units Set/Clear (SW) TxOE MUX 1 Overflow/ Underflow 1 TxOTL Shadow Latch 0 TxOUT To Port Logic Core Timer Toggle Latch Logic To Aux. Timer Input Logic mc_gpt0106_otl.vsd Figure 14-3 Block Diagram of the Toggle Latch Logic of Core Timer T3 User's Manual GPT_X7, V2.0 14-7 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary The General Purpose Timer Units 14.1.2 GPT1 Core Timer T3 Operating Modes Timer 3 in Timer Mode Timer mode for the core timer T3 is selected by setting bitfield T3M in register T3CON to 000B. In timer mode, T3 is clocked with the module's input clock fGPT divided by two programmable prescalers controlled by bitfields BPS1 and T3I in register T3CON. Please see Section 14.1.5 for details on the input clock options. T3IRQ fGPT Prescaler fT3 Count Core Timer T3 Toggle Latch T3OUT to T2/T4 BPS1 T3I T3R T3UD 0 =1 T3EUD T3UDE MCB05391 MUX Up/Down 1 Figure 14-4 Block Diagram of Core Timer T3 in Timer Mode User's Manual GPT_X7, V2.0 14-8 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Gated Timer Mode Gated timer mode for the core timer T3 is selected by setting bitfield T3M in register T3CON to 010B or 011B. Bit T3M.0 (T3CON.3) selects the active level of the gate input. The same options for the input frequency are available in gated timer mode as in timer mode (see Section 14.1.5). However, the input clock to the timer in this mode is gated by the external input pin T3IN (Timer T3 External Input). To enable this operation, the associated pin T3IN must be configured as input, that is, the corresponding direction control bit must contain 0. The General Purpose Timer Units T3IRQ fGPT Prescaler Gate Ctrl. fT3 Count Core Timer T3 Toggle Latch T3OUT to T2/T4 BPS1 T3IN T3I T3R T3UD 0 =1 T3EUD T3UDE MCB05392 MUX Up/Down 1 Figure 14-5 Block Diagram of Core Timer T3 in Gated Timer Mode If T3M = 010B, the timer is enabled when T3IN shows a low level. A high level at this line stops the timer. If T3M = 011B, line T3IN must have a high level in order to enable the timer. Additionally, the timer can be turned on or off by software using bit T3R. The timer will only run if T3R is 1 and the gate is active. It will stop if either T3R is 0 or the gate is inactive. Note: A transition of the gate signal at pin T3IN does not cause an interrupt request. User's Manual GPT_X7, V2.0 14-9 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Counter Mode Counter Mode for the core timer T3 is selected by setting bitfield T3M in register T3CON to 001B. In counter mode, timer T3 is clocked by a transition at the external input pin T3IN. The event causing an increment or decrement of the timer can be a positive, a negative, or both a positive and a negative transition at this line. Bitfield T3I in control register T3CON selects the triggering transition (see Table 14-2). T3IRQ Edge The General Purpose Timer Units T3IN Select Count Core Timer T3 Toggle Latch T3OUT to T2/T4 T3R T3I T3UD 0 =1 T3EUD T3UDE 1 MUX Up/Down MCB05393 Figure 14-6 Block Diagram of Core Timer T3 in Counter Mode Table 14-2 T3I 000 001 010 011 1XX GPT1 Core Timer T3 (Counter Mode) Input Edge Selection Triggering Edge for Counter Increment/Decrement None. Counter T3 is disabled Positive transition (rising edge) on T3IN Negative transition (falling edge) on T3IN Any transition (rising or falling edge) on T3IN Reserved. Do not use this combination For counter mode operation, pin T3IN must be configured as input (the respective direction control bit DPx.y must be 0). The maximum input frequency allowed in counter mode depends on the selected prescaler value. To ensure that a transition of the count input signal applied to T3IN is recognized correctly, its level must be held high or low for a minimum number of module clock cycles before it changes. This information can be found in Section 14.1.5. User's Manual GPT_X7, V2.0 14-10 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Incremental Interface Mode Incremental interface mode for the core timer T3 is selected by setting bitfield T3M in register T3CON to 110B or 111B. In incremental interface mode, the two inputs associated with core timer T3 (T3IN, T3EUD) are used to interface to an incremental encoder. T3 is clocked by each transition on one or both of the external input pins to provide 2-fold or 4-fold resolution of the encoder input. The General Purpose Timer Units T3IN Edge Count Core Timer T3 Toggle Latch T3OUT to T2/T4 Select T3R T3I T3 EDGE T3 RDIR _ >1 T3IRQ T3UD 0 =1 T3EUD Phase Detect T3UDE 1 MUX Change Detect T3M T3CH DIR T3M MCB05394 Figure 14-7 Block Diagram of Core Timer T3 in Incremental Interface Mode Bitfield T3I in control register T3CON selects the triggering transitions (see Table 14-3). The sequence of the transitions of the two input signals is evaluated and generates count pulses as well as the direction signal. So T3 is modified automatically according to the speed and the direction of the incremental encoder and, therefore, its contents always represent the encoder's current position. The interrupt request (T3IRQ) generation mode can be selected: In Rotation Detection Mode (T3M = 110B), an interrupt request is generated each time the count direction of T3 changes. In Edge Detection Mode (T3M = 111B), an interrupt request is generated each time a count edge for T3 is detected. Count direction, changes in the count direction, and count requests are monitored by status bits T3RDIR, T3CHDIR, and T3EDGE in register T3CON. User's Manual GPT_X7, V2.0 14-11 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Table 14-3 T3I 000 001 010 011 1XX The General Purpose Timer Units Core Timer T3 (Incremental Interface Mode) Input Edge Selection Triggering Edge for Counter Increment/Decrement None. Counter T3 stops. Any transition (rising or falling edge) on T3IN. Any transition (rising or falling edge) on T3EUD. Any transition (rising or falling edge) on any T3 input (T3IN or T3EUD). Reserved. Do not use this combination. The incremental encoder can be connected directly to the XC2000 without external interface logic. In a standard system, however, comparators will be employed to convert the encoder's differential outputs (such as A, A) to digital signals (such as A). This greatly increases noise immunity. Note: The third encoder output T0, which indicates the mechanical zero position, may be connected to an external interrupt input and trigger a reset of timer T3 (for example via PEC transfer from ZEROS). Signal Conditioning A A B B T0 T0 A Encoder Controller T3Input B T3Input T0 Interrupt MCS04372 Figure 14-8 Connection of the Encoder to the XC2000 For incremental interface operation, the following conditions must be met: * Bitfield T3M must be 110B or 111B. * Both pins T3IN and T3EUD must be configured as input, i.e. the respective direction control bits must be 0. * Bit T3UDE must be 1 to enable automatic external direction control. The maximum count frequency allowed in incremental interface mode depends on the selected prescaler value. To ensure that a transition of any input signal is recognized correctly, its level must be held high or low for a minimum number of module clock cycles before it changes. This information can be found in Section 14.1.5. User's Manual GPT_X7, V2.0 14-12 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary The General Purpose Timer Units As in incremental interface mode two input signals with a 90 phase shift are evaluated, their maximum input frequency can be half the maximum count frequency. In incremental interface mode, the count direction is automatically derived from the sequence in which the input signals change, which corresponds to the rotation direction of the connected sensor. Table 14-4 summarizes the possible combinations. Table 14-4 GPT1 Core Timer T3 (Incremental Interface Mode) Count Direction T3EUD Input Rising Up Down Falling Down Up Level on Respective T3IN Input other Input Rising Falling High Low Down Up Up Down Figure 14-9 and Figure 14-10 give examples of T3's operation, visualizing count signal generation and direction control. They also show how input jitter is compensated, which might occur if the sensor rests near to one of its switching points. Forward T3IN T3EUD Jitter Backward Jitter Forward Contents of T3 Up Down Up Note: This example shows the timer behaviour assuming that T3 counts upon any transition on input, i.e. T3I = '011 B'. MCT04373 Figure 14-9 Evaluation of Incremental Encoder Signals, 2 Count Inputs User's Manual GPT_X7, V2.0 14-13 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary The General Purpose Timer Units Forward T3IN T3EUD Jitter Backward Jitter Forward Contents of T3 Up Down Up Note: This example shows the timer behaviour assuming that T3 counts upon any transition on input T3IN, i.e. T3I = '001 B'. MCT04374 Figure 14-10 Evaluation of Incremental Encoder Signals, 1 Count Input Note: Timer T3 operating in incremental interface mode automatically provides information on the sensor's current position. Dynamic information (speed, acceleration, deceleration) may be obtained by measuring the incoming signal periods. This is facilitated by an additional special capture mode for timer T5 (see Section 14.2.5). User's Manual GPT_X7, V2.0 14-14 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary The General Purpose Timer Units 14.1.3 GPT1 Auxiliary Timers T2/T4 Control Auxiliary timers T2 and T4 have exactly the same functionality. They can be configured for timer mode, gated timer mode, counter mode, or incremental interface mode with the same options for the timer frequencies and the count signal as the core timer T3. In addition to these 4 counting modes, the auxiliary timers can be concatenated with the core timer, or they may be used as reload or capture registers in conjunction with the core timer. The start/stop function of the auxiliary timers can be remotely controlled by the T3 run control bit. Several timers may thus be controlled synchronously. The current contents of an auxiliary timer are reflected by its count register T2 or T4, respectively. These registers can also be written to by the CPU, for example, to set the initial start value. The individual configurations for timers T2 and T4 are determined by their bitaddressable control registers T2CON and T4CON, which are organized identically. Note that functions which are present in all 3 timers of block GPT1 are controlled in the same bit positions and in the same manner in each of the specific control registers. Note: The auxiliary timers have no output toggle latch and no alternate output function. GPT12E_T2CON Timer 2 Control Register 15 14 13 T2 ED GE rwh 12 T2 IR DIS rw 11 10 SFR (FF40H/A0H) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 T2 T2 R CH DIR DIR rh rwh - - T2 T2 T2 RC UDE UD rw rw rw T2R T2M T2I - - rw rw rw Field Bits Type Description GPT12E_T4CON Timer 4 Control Register 15 14 13 T4 ED GE rwh 12 T4 IR DIS rw 11 10 SFR (FF44H/A2H) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 T4 T4 R CH DIR DIR rh rwh - - T4 T4 T4 RC UDE UD rw rw rw T4R T4M T4I - - rw rw rw User's Manual GPT_X7, V2.0 14-15 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary The General Purpose Timer Units Field TxRDIR Bits 15 Type rh Description Timer Tx Rotation Direction 0 Timer x counts up 1 Timer x counts down Timer Tx Count Direction Change This bit is set each time the count direction of timer Tx changes. TxCHDIR must be cleared by SW. 0 No change in count direction was detected 1 A change in count direction was detected Timer Tx Edge Detection The bit is set each time a count edge is detected. TxEDGE must be cleared by SW. 0 No count edge was detected 1 A count edge was detected Timer Tx Interrupt Request Disable 0 Interrupt generation for TxCHDIR and TxEDGE interrupts in Incremental Interface Mode is enabled 1 Interrupt generation for TxCHDIR and TxEDGE interrupts in Incremental Interface Mode is disabled Timer Tx Remote Control 0 Timer Tx is controlled by its own run bit TxR 1 Timer Tx is controlled by the run bit T3R of core timer 3, not by bit TxR Timer Tx External Up/Down Enable1) 0 Input TxEUD is disconnected 1 Direction influenced by input TxEUD Timer Tx Up/Down Control1) 0 Timer Tx counts up 1 Timer Tx counts down Timer Tx Run Bit 0 Timer Tx stops 1 Timer Tx runs Note: This bit only controls timer Tx if bit TxRC = 0. TxCHDIR 14 rwh TxEDGE 13 rwh TxIRDIS 12 rw TxRC 9 rw TxUDE 8 rw TxUD 7 rw TxR 6 rw User's Manual GPT_X7, V2.0 14-16 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field TxM Bits [5:3] Type rw Description Timer Tx Mode Control (Basic Operating Mode) 000 Timer Mode 001 Counter Mode 010 Gated Timer Mode with gate active low 011 Gated Timer Mode with gate active high 100 Reload Mode 101 Capture Mode 110 Incremental Interface Mode (Rotation Detect.) 111 Incremental Interface Mode (Edge Detection) Timer Tx Input Parameter Selection Depends on the operating mode, see respective sections for encoding: Table 14-7 for Timer Mode and Gated Timer Mode Table 14-2 for Counter Mode Table 14-3 for Incremental Interface Mode The General Purpose Timer Units TxI [2:0] rw 1) See Table 14-1 for encoding of bits TxUD and TxUDE. Timer T2/T4 Run Control Each of the auxiliary timers T2 and T4 can be started or stopped by software in two different ways: * Through the associated timer run bit (T2R or T4R). In this case it is required that the respective control bit TxRC = 0. * Through the core timer's run bit (T3R). In this case the respective remote control bit must be set (TxRC = 1). The selected run bit is relevant in all operating modes of T2/T4. Setting the bit will start the timer, clearing the bit stops the timer. In gated timer mode, the timer will only run if the selected run bit is set and the gate is active (high or low, as programmed). Note: If remote control is selected T3R will start/stop timer T3 and the selected auxiliary timer(s) synchronously. Count Direction Control The count direction of the GPT1 timers (core timer and auxiliary timers) is controlled in the same way, either by software or by the external input pin TxEUD. Please refer to the description in Table 14-1. Note: When pin TxEUD is used as external count direction control input, it must be configured as input (its corresponding direction control bit must be cleared). User's Manual GPT_X7, V2.0 14-17 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary The General Purpose Timer Units 14.1.4 GPT1 Auxiliary Timers T2/T4 Operating Modes The operation of the auxiliary timers in the basic operating modes is almost identical with the core timer's operation, with very few exceptions. Additionally, some combined operating modes can be selected. Timers T2 and T4 in Timer Mode Timer mode for an auxiliary timer Tx is selected by setting its bitfield TxM in register TxCON to 000B. fTx Count fGPT Prescaler Auxiliary Timer Tx TxIRQ BPS1 TxI TxR T3R 0 1 MUX TxRC TxUD 0 =1 TxEUD TxUDE x = 2, 4 MCB05395 MUX Up/Down 1 Figure 14-11 Block Diagram of an Auxiliary Timer in Timer Mode User's Manual GPT_X7, V2.0 14-18 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Timers T2 and T4 in Gated Timer Mode Gated timer mode for an auxiliary timer Tx is selected by setting bitfield TxM in register TxCON to 010B or 011B. Bit TxM.0 (TxCON.3) selects the active level of the gate input. Note: A transition of the gate signal at line TxIN does not cause an interrupt request. The General Purpose Timer Units fGPT Prescaler Gate Ctrl. fTx Count Auxiliary Timer Tx TxIRQ BPS1 TxIN TxI TxM TxR T3R 0 1 MUX TxRC TxUD 0 =1 TxEUD TxUDE x = 2, 4 MCB05396 MUX Up/Down 1 Figure 14-12 Block Diagram of an Auxiliary Timer in Gated Timer Mode Note: There is no output toggle latch for T2 and T4. Start/stop of an auxiliary timer can be controlled locally or remotely. User's Manual GPT_X7, V2.0 14-19 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Timers T2 and T4 in Counter Mode Counter mode for an auxiliary timer Tx is selected by setting bitfield TxM in register TxCON to 001B. In counter mode, an auxiliary timer can be clocked either by a transition at its external input line TxIN, or by a transition of timer T3's toggle latch T3OTL. The event causing an increment or decrement of a timer can be a positive, a negative, or both a positive and a negative transition at either the respective input pin or at the toggle latch. Bitfield TxI in control register TxCON selects the triggering transition (see Table 14-5). TxIN T3 Toggle Latch 0 1 Select MUX Edge The General Purpose Timer Units Count Auxiliary Timer Tx TxIRQ TxI.2 TxR T3R TxI 0 1 MUX TxRC TxUD 0 =1 TxEUD TxUDE x = 2, 4 MCB05397 MUX Up/Down 1 Figure 14-13 Block Diagram of an Auxiliary Timer in Counter Mode Table 14-5 T2I/T4I X00 001 010 011 101 110 111 GPT1 Auxiliary Timer (Counter Mode) Input Edge Selection Triggering Edge for Counter Increment/Decrement None. Counter Tx is disabled Positive transition (rising edge) on TxIN Negative transition (falling edge) on TxIN Any transition (rising or falling edge) on TxIN Positive transition (rising edge) of T3 toggle latch T3OTL Negative transition (falling edge) of T3 toggle latch T3OTL Any transition (rising or falling edge) of T3 toggle latch T3OTL Note: Only state transitions of T3OTL which are caused by the overflows/underflows of T3 will trigger the counter function of T2/T4. Modifications of T3OTL via software will NOT trigger the counter function of T2/T4. User's Manual GPT_X7, V2.0 14-20 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary The General Purpose Timer Units For counter operation, pin TxIN must be configured as input (the respective direction control bit DPx.y must be 0). The maximum input frequency allowed in counter mode depends on the selected prescaler value. To ensure that a transition of the count input signal applied to TxIN is recognized correctly, its level must be held high or low for a minimum number of module clock cycles before it changes. This information can be found in Section 14.1.5. Timers T2 and T4 in Incremental Interface Mode Incremental interface mode for an auxiliary timer Tx is selected by setting bitfield TxM in the respective register TxCON to 110B or 111B. In incremental interface mode, the two inputs associated with an auxiliary timer Tx (TxIN, TxEUD) are used to interface to an incremental encoder. Tx is clocked by each transition on one or both of the external input pins to provide 2-fold or 4-fold resolution of the encoder input. Overflow Underflow TxIN Edge Count Auxiliary Timer Tx Select TxI TxR T3R 0 1 MUX Tx Edge Tx RDIR TxRC TxUD 0 =1 TxEUD Phase Detect TxUDE 1 MUX & _ >1 TxIRQ Change Detect TxM & TxCH DIR TxIRDIS TxM MCB05398 Figure 14-14 Block Diagram of an Auxiliary Timer in Incremental Interface Mode The operation of the auxiliary timers T2 and T4 in incremental interface mode and the interrupt generation are the same as described for the core timer T3. The descriptions, figures and tables apply accordingly. User's Manual GPT_X7, V2.0 14-21 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Timer Concatenation Using the toggle bit T3OTL as a clock source for an auxiliary timer in counter mode concatenates the core timer T3 with the respective auxiliary timer. This concatenation forms either a 32-bit or a 33-bit timer/counter, depending on which transition of T3OTL is selected to clock the auxiliary timer. * 32-bit Timer/Counter: If both a positive and a negative transition of T3OTL are used to clock the auxiliary timer, this timer is clocked on every overflow/underflow of the core timer T3. Thus, the two timers form a 32-bit timer. * 33-bit Timer/Counter: If either a positive or a negative transition of T3OTL is selected to clock the auxiliary timer, this timer is clocked on every second overflow/underflow of the core timer T3. This configuration forms a 33-bit timer (16-bit core timer + T3OTL + 16-bit auxiliary timer). As long as bit T3OTL is not modified by software, it represents the state of the internal toggle latch, and can be regarded as part of the 33-bit timer. The count directions of the two concatenated timers are not required to be the same. This offers a wide variety of different configurations. T3, which represents the low-order part of the concatenated timer, can operate in timer mode, gated timer mode or counter mode in this case. The General Purpose Timer Units T3IRQ fGPT T3IN Operating Mode Control T3R Count Core Timer T3 Toggle Latch T3OUT BPS1 TxI Up/Down TxIN 0 1 MUX Edge Count Select Auxiliary Timer Tx TxIRQ TxI.2 TxI TxR T3R 0 1 MUX Up/Down TxRC x = 2, 4 MCA05399 Figure 14-15 Concatenation of Core Timer T3 and an Auxiliary Timer User's Manual GPT_X7, V2.0 14-22 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Auxiliary Timer in Reload Mode Reload Mode for an auxiliary timer Tx is selected by setting bitfield TxM in the respective register TxCON to 100B. In reload mode, the core timer T3 is reloaded with the contents of an auxiliary timer register, triggered by one of two different signals. The trigger signal is selected the same way as the clock source for counter mode (see Table 14-5), i.e. a transition of the auxiliary timer's input TxIN or the toggle latch T3OTL may trigger the reload. Note: When programmed for reload mode, the respective auxiliary timer (T2 or T4) stops independently of its run flag T2R or T4R. The timer input pin TxIN must be configured as input if it shall trigger a reload operation. T3IRQ The General Purpose Timer Units fGPT T3IN Operating Mode Control T3R Count Core Timer T3 Toggle Latch T3OUT BPS1 TxI Up/Down TxIN 0 1 MUX Edge Reload Select TxIRQ TxI.2 TxI Auxiliary Timer Tx x = 2, 4 MCA05400 Figure 14-16 GPT1 Auxiliary Timer in Reload Mode Upon a trigger signal, T3 is loaded with the contents of the respective timer register (T2 or T4) and the respective interrupt request flag (T2IR or T4IR) is set. Note: When a T3OTL transition is selected for the trigger signal, the interrupt request flag T3IR will also be set upon a trigger, indicating T3's overflow or underflow. Modifications of T3OTL via software will NOT trigger the counter function of T2/T4. To ensure that a transition of the reload input signal applied to TxIN is recognized correctly, its level must be held high or low for a minimum number of module clock cycles, detailed in Section 14.1.5. The reload mode triggered by the T3 toggle latch can be used in a number of different configurations. The following functions can be performed, depending on the selected active transition: User's Manual GPT_X7, V2.0 14-23 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary The General Purpose Timer Units * If both a positive and a negative transition of T3OTL are selected to trigger a reload, the core timer will be reloaded with the contents of the auxiliary timer each time it overflows or underflows. This is the standard reload mode (reload on overflow/underflow). * If either a positive or a negative transition of T3OTL is selected to trigger a reload, the core timer will be reloaded with the contents of the auxiliary timer on every second overflow or underflow. * Using this "single-transition" mode for both auxiliary timers allows to perform very flexible Pulse Width Modulation (PWM). One of the auxiliary timers is programmed to reload the core timer on a positive transition of T3OTL, the other is programmed for a reload on a negative transition of T3OTL. With this combination the core timer is alternately reloaded from the two auxiliary timers. Figure 14-17 shows an example for the generation of a PWM signal using the "singletransition" reload mechanism. T2 defines the high time of the PWM signal (reloaded on positive transitions) and T4 defines the low time of the PWM signal (reloaded on negative transitions). The PWM signal can be output on pin T3OUT if T3OE = 1. With this method, the high and low time of the PWM signal can be varied in a wide range. Note: The output toggle latch T3OTL is accessible via software and may be changed, if required, to modify the PWM signal. However, this will NOT trigger the reloading of T3. User's Manual GPT_X7, V2.0 14-24 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary The General Purpose Timer Units Auxiliary Timer T2 0 1 Select Edge T2IN MUX Reload T2IRQ T2I.2 T2I T3IRQ fGPT T3IN Operating Mode Control T3R Count Core Timer T3 Toggle Latch T3OUT BPS1 T3I Up/Down T4IN 0 1 MUX Edge Reload Select T4IRQ T4I.2 T4I Auxiliary Timer T4 MCA05401 Figure 14-17 GPT1 Timer Reload Configuration for PWM Generation Note: Although possible, selecting the same reload trigger event for both auxiliary timers should be avoided. In such a case, both reload registers would try to load the core timer at the same time. If this combination is selected, T2 is disregarded and the contents of T4 is reloaded. User's Manual GPT_X7, V2.0 14-25 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Auxiliary Timer in Capture Mode Capture mode for an auxiliary timer Tx is selected by setting bitfield TxM in the respective register TxCON to 101B. In capture mode, the contents of the core timer T3 are latched into an auxiliary timer register in response to a signal transition at the respective auxiliary timer's external input pin TxIN. The capture trigger signal can be a positive, a negative, or both a positive and a negative transition. The two least significant bits of bitfield TxI select the active transition (see Table 14-5). Bit 2 of TxI is irrelevant for capture mode and must be cleared (TxI.2 = 0). Note: When programmed for capture mode, the respective auxiliary timer (T2 or T4) stops independently of its run flag T2R or T4R. The General Purpose Timer Units T3IRQ fGPT T3IN Operating Mode Control T3R Count Core Timer T3 Toggle Latch T3OUT BPS1 T3I Up/Down to Ty Edge TxIN Select Capture TxIRQ TxI Auxiliary Timer Tx x = 2, 4 y = 4, 2 MCA05402 Figure 14-18 GPT1 Auxiliary Timer in Capture Mode Upon a trigger (selected transition) at the corresponding input pin TxIN the contents of the core timer are loaded into the auxiliary timer register and the associated interrupt request flag TxIR will be set. For capture mode operation, the respective timer input pin TxIN must be configured as input. To ensure that a transition of the capture input signal applied to TxIN is recognized correctly, its level must be held high or low for a minimum number of module clock cycles, detailed in Section 14.1.5. User's Manual GPT_X7, V2.0 14-26 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary The General Purpose Timer Units 14.1.5 GPT1 Clock Signal Control All actions within the timer block GPT1 are triggered by transitions of its basic clock. This basic clock is derived from the system clock by a basic block prescaler, controlled by bitfield BPS1 in register T3CON (see Figure 14-2). The count clock can be generated in two different ways: * Internal count clock, derived from GPT1's basic clock via a programmable prescaler, is used for (gated) timer mode. * External count clock, derived from the timer's input pin(s), is used for counter mode. For both ways, the basic clock determines the maximum count frequency and the timer's resolution: Table 14-6 Basic Clock Selection for Block GPT1 BPS1 = 01B F(BPS1) =4 BPS1 = 00B2) BPS1 = 11B F(BPS1) =8 F(BPS1) = 16 BPS1 = 10B F(BPS1) = 32 Block Prescaler1) Prescaling Factor for GPT1: F(BPS1) Maximum External Count Frequency Input Signal Stable Time 2) Default after reset. fGPT/8 4 x tGPT fGPT/16 8 x tGPT fGPT/32 16 x tGPT fGPT/64 32 x tGPT 1) Please note the non-linear encoding of bitfield BPS1. Internal Count Clock Generation In timer mode and gated timer mode, the count clock for each GPT1 timer is derived from the GPT1 basic clock by a programmable prescaler, controlled by bitfield TxI in the respective timer's control register TxCON. The count frequency fTx for a timer Tx and its resolution rTx are scaled linearly with lower clock frequencies, as can be seen from the following formula: f GPT f Tx = ------------------------------------------- F ( BPS1 ) x 2 r Tx [ s ] = -------------------------------------------f GPT [ MHz ] F ( BPS1 ) x 2 [14.1] The effective count frequency depends on the common module clock prescaler factor F(BPS1) as well as on the individual input prescaler factor 2 User's Manual GPT_X7, V2.0 14-27 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary The General Purpose Timer Units Table 14-8 lists a timer's parameters (such as count frequency, resolution, and period) resulting from the selected overall prescaler factor and the applied system frequency. Note that some numbers may be rounded. Table 14-7 GPT1 Overall Prescaler Factors for Internal Count Clock Individual Common Prescaler for Module Clock1) Prescaler for Tx BPS1 = 01 BPS1 = 00B BPS1 = 11B BPS1 = 10B B TxI = 000B TxI = 001B TxI = 010B TxI = 011B TxI = 100B TxI = 101B TxI = 110B TxI = 111B 4 8 16 32 64 128 256 512 8 16 32 64 128 256 512 1024 16 32 64 128 256 512 1024 2048 32 64 128 256 512 1024 2048 4096 1) Please note the non-linear encoding of bitfield BPS1. Table 14-8 Frequency 2.5 MHz 1.25 MHz 625.0 kHz 312.5 kHz 156.25 kHz 78.125 kHz 39.06 kHz 19.53 kHz 9.77 kHz 4.88 kHz 2.44 kHz GPT1 Timer Parameters Resolution Period 400 ns 800 ns 1.6 s 3.2 s 6.4 s 12.8 s 25.6 s 51.2 s 102.4 s 204.8 s 409.6 s Overall Divider Factor System Clock = 40 MHz Frequency Resolution Period 10.0 MHz 5.0 MHz 2.5 MHz 1.25 MHz 625.0 kHz 312.5 kHz 100 ns 200 ns 400 ns 800 ns 1.6 s 3.2 s 6.55 ms 13.11 ms 26.21 ms 52.43 ms 104.9 ms 209.7 ms 419.4 ms 838.9 ms 1.678 s 3.355 s 6.711 s System Clock = 10 MHz 26.21 ms 4 52.43 ms 8 104.9 ms 16 209.7 ms 32 419.4 ms 64 838.9 ms 128 1.678 s 3.355 s 6.711 s 13.42 s 26.84 s 256 512 1024 2048 4096 156.25 kHz 6.4 s 78.125 kHz 12.8 s 39.06 kHz 19.53 kHz 9.77 kHz 25.6 s 51.2 s 102.4 s User's Manual GPT_X7, V2.0 14-28 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary External Count Clock Input The external input signals of the GPT1 block are sampled with the GPT1 basic clock (see Figure 14-2). To ensure that a signal is recognized correctly, its current level (high or low) must be held active for at least one complete sampling period, before changing. A signal transition is recognized if two subsequent samples of the input signal represent different levels. Therefore, a minimum of two basic clock periods are required for the sampling of an external input signal. Thus, the maximum frequency of an input signal must not be higher than half the basic clock. Table 14-9 summarizes the resulting requirements for external GPT1 input signals. Table 14-9 GPT1 External Input Signal Limits GPT1 Input System Clock = 40 MHz Divider Phase Max. Input Min. Level BPS1 Duration Frequency Hold Time 01B 00B 11B 10B 4 x tGPT 8 x tGPT 16 x tGPT 32 x tGPT 5.0 MHz 2.5 MHz 1.25 MHz 625.0 kHz 100 ns 200 ns 400 ns 800 ns The General Purpose Timer Units System Clock = 10 MHz Input Max. Input Min. Level Frequ. Frequency Hold Time Factor 1.25 MHz 625.0 kHz 312.5 kHz 156.25 kHz 400 ns 800 ns 1.6 s 3.2 s fGPT/8 fGPT/16 fGPT/32 fGPT/64 These limitations are valid for all external input signals to GPT1, including the external count signals in counter mode and incremental interface mode, the gate input signals in gated timer mode, and the external direction signals. User's Manual GPT_X7, V2.0 14-29 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary The General Purpose Timer Units 14.1.6 GPT1 Timer Registers GPT12E_T2 Timer 2 Count Register GPT12E_T3 Timer 3 Count Register GPT12E_T4 Timer 4 Count Register 15 14 13 12 11 10 SFR (FE40H/20H) SFR (FE42H/21H) SFR (FE44H/22H) 9 8 7 6 5 4 Reset Value: 0000H Reset Value: 0000H Reset Value: 0000H 3 2 1 0 Txvalue rwh Field Txvalue Bits [15:0] Type Description rwh Current timer value User's Manual GPT_X7, V2.0 14-30 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary The General Purpose Timer Units 14.1.7 Interrupt Control for GPT1 Timers When a timer overflows from FFFFH to 0000H (when counting up), or when it underflows from 0000H to FFFFH (when counting down), its interrupt request flag (T2IR, T3IR or T4IR) in register TxIC will be set. This will cause an interrupt to the respective timer interrupt vector (T2INT, T3INT or T4INT) or trigger a PEC service, if the respective interrupt enable bit (T2IE, T3IE or T4IE in register TxIC) is set. There is an interrupt control register for each of the three timers. GPT12E_T2IC Timer 2 Intr. Ctrl. Reg. 15 14 13 12 11 10 - SFR (FF60H/B0H) 9 8 7 6 5 4 Reset Value: - - 00H 3 2 1 0 GPX T2IR T2IE rw rwh rw ILVL rw GLVL rw GPT12E_T3IC Timer 3 Intr. Ctrl. Reg. 15 14 13 12 11 10 - SFR (FF62H/B1H) 9 8 7 6 5 4 Reset Value: - - 00H 3 2 1 0 GPX T3IR T3IE rw rwh rw ILVL rw GLVL rw GPT12E_T4IC Timer 4 Intr. Ctrl. Reg. 15 14 13 12 11 10 - SFR (FF64H/B2H) 9 8 7 6 5 4 Reset Value: - - 00H 3 2 1 0 GPX T4IR T4IE rw rwh rw ILVL rw GLVL rw Note: Please refer to the general Interrupt Control Register description for an explanation of the control fields. User's Manual GPT_X7, V2.0 14-31 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary The General Purpose Timer Units 14.2 Timer Block GPT2 From a programmer's point of view, the GPT2 block is represented by a set of SFRs as summarized below. Those portions of port and direction registers which are used for alternate functions by the GPT2 block are shaded. Data Registers T5 T6 CAPREL Control Registers T5CON T6CON Interrupt Control T5IC T6IC CRIC KSCFG Tx CAPREL TxCON TxIC KSCFG GPT2 Timer x Register GPT2 Capture/Reload Register GPT2 Timer x Control Register GPT2 Timer x Interrupt Ctrl. Reg. Kernel State Configuration Register m c_gpt 2_regist ers.vsd Figure 14-19 SFRs Associated with Timer Block GPT2 Both timers of block GPT2 (T5, T6) can run in one of 3 basic modes: Timer Mode, Gated Timer Mode, or Counter Mode. All timers can count up or down. Each timer of GPT2 is controlled by a separate control register TxCON. Each timer has an input pin TxIN (alternate pin function) associated with it, which serves as the gate control in gated timer mode, or as the count input in counter mode. The count direction (up/down) may be programmed via software or may be dynamically altered by a signal at the External Up/Down control input TxEUD (alternate pin function). An overflow/underflow of core timer T6 is indicated by the Output Toggle Latch T6OTL, whose state may be output on the associated pin T6OUT (alternate pin function). The auxiliary timer T5 may additionally be concatenated with core timer T6 (through T6OTL). The Capture/Reload register CAPREL can be used to capture the contents of timer T5, or to reload timer T6. A special mode facilitates the use of register CAPREL for both functions at the same time. This mode allows frequency multiplication. The capture function is triggered by the input pin CAPIN, or by GPT1 timer's T3 input lines T3IN and T3EUD. The reload function is triggered by an overflow or underflow of timer T6. Overflows/underflows of timer T6 may also clock the timers of the CAPCOM units. The current contents of each timer can be read or modified by the CPU by accessing the corresponding timer count registers T5 or T6, located in the non-bitaddressable SFR User's Manual GPT_X7, V2.0 14-32 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary The General Purpose Timer Units space (see Section 14.2.7). When any of the timer registers is written to by the CPU in the state immediately preceding a timer increment, decrement, reload, or capture operation, the CPU write operation has priority in order to guarantee correct results. The interrupts of GPT2 are controlled through the Interrupt Control Registers TxIC. These registers are not part of the GPT2 block. The input and output lines of GPT2 are connected to pins of Ports P3 and P5. The control registers for the port functions are located in the respective port modules. Note: The timing requirements for external input signals can be found in Section 14.2.6, Section 14.3 summarizes the module interface signals, including pins. T6CON.BPS2 f GPT 2n: 1 Basic clock GPT2 Timer T5 T5IN T5EUD T5 Mode Control U/D Clear Interrupt Request (T5IR) Capture CAPIN T3IN/ T3EUD CAPREL Mode Control GPT2 CAPREL Interrupt Request (CRIR) Interrupt Request (T6IR) Toggle FF Reload Clear GPT2 Timer T6 T6 Mode Control U/D T6OTL T6OUT T6IN T6EUD T6OUF mc_gpt0108_bldiax4.vsd Figure 14-20 GPT2 Block Diagram User's Manual GPT_X7, V2.0 14-33 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary The General Purpose Timer Units 14.2.1 GPT2 Core Timer T6 Control The current contents of the core timer T6 are reflected by its count register T6. This register can also be written to by the CPU, for example, to set the initial start value. The core timer T6 is configured and controlled via its bitaddressable control register T6CON. GPT12E_T6CON Timer 6 Control Register 15 14 13 12 11 10 SFR (FF48H/A4H) 9 8 7 6 T6R rw 5 4 T6M rw Reset Value: 0000H 3 2 1 T6I rw 0 T6 T6 SR CLR rw rw BPS2 rw T6 T6 T6 T6 OTL OE UDE UD rwh rw rw rw Field T6SR Bits 15 Type rw Description Timer 6 Reload Mode Enable 0 Reload from register CAPREL Disabled 1 Reload from register CAPREL Enabled Timer T6 Clear Enable Bit 0 Timer T6 is not cleared on a capture event 1 Timer T6 is cleared on a capture event GPT2 Block Prescaler Control Selects the basic clock for block GPT2 (see also Section 14.2.6) 00 fGPT/4 01 fGPT/2 10 fGPT/16 11 fGPT/8 Timer T6 Overflow Toggle Latch Toggles on each overflow/underflow of T6. Can be set or reset by software (see separate description) Overflow/Underflow Output Enable 0 Alternate Output Function Disabled 1 State of T6 toggle latch is output on pin T6OUT Timer T6 External Up/Down Enable1) 0 Input T6EUD is disconnected 1 Direction influenced by input T6EUD T6CLR 14 rw BPS2 [12:11] rw T6OTL 10 rwh T6OE 9 rw T6UDE 8 rw User's Manual GPT_X7, V2.0 14-34 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field T6UD Bits 7 Type rw Description Timer T6 Up/Down Control1) 0 Timer T6 counts up 1 Timer T6 counts down Timer T6 Run Bit 0 Timer T6 stops 1 Timer T6 runs Timer T6 Mode Control (Basic Operating Mode) 000 Timer Mode 001 Counter Mode 010 Gated Timer Mode with gate active low 011 Gated Timer Mode with gate active high 100 Reserved. Do not use this combination. 101 Reserved. Do not use this combination. 110 Reserved. Do not use this combination. 111 Reserved. Do not use this combination. Timer T6 Input Parameter Selection Depends on the operating mode, see respective sections for encoding: Table 14-15 for Timer Mode and Gated Timer Mode Table 14-11 for Counter Mode The General Purpose Timer Units T6R 6 rw T6M [5:3] rw T6I [2:0] rw 1) See Table 14-10 for encoding of bits T6UD and T6UDE. User's Manual GPT_X7, V2.0 14-35 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Timer T6 Run Control The core timer T6 can be started or stopped by software through bit T6R (timer T6 run bit). This bit is relevant in all operating modes of T6. Setting bit T6R will start the timer, clearing bit T6R stops the timer. In gated timer mode, the timer will only run if T6R = 1 and the gate is active (high or low, as programmed). Note: When bit T5RC in timer control register T5CON is set, bit T6R will also control (start and stop) the Auxiliary Timer T5. Count Direction Control The count direction of the GPT2 timers (core timer and auxiliary timer) can be controlled either by software or by the external input pin TxEUD (Timer Tx External Up/Down Control Input). These options are selected by bits TxUD and TxUDE in the respective control register TxCON. When the up/down control is provided by software (bit TxUDE = 0), the count direction can be altered by setting or clearing bit TxUD. When bit TxUDE = 1, pin TxEUD is selected to be the controlling source of the count direction. However, bit TxUD can still be used to reverse the actual count direction, as shown in Table 14-10. The count direction can be changed regardless of whether or not the timer is running. Table 14-10 GPT2 Timer Count Direction Control Pin TxEUD X X 0 1 0 1 Bit TxUDE 0 0 1 1 1 1 Bit TxUD 0 1 0 0 1 1 Count Direction Count Up Count Down Count Up Count Down Count Down Count Up The General Purpose Timer Units User's Manual GPT_X7, V2.0 14-36 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Timer 6 Output Toggle Latch The overflow/underflow signal of timer T6 is connected to a block named `Toggle Latch', shown in the timer mode diagrams. Figure 14-21 illustrates the details of this block. An overflow or underflow of T6 will clock two latches: The first latch represents bit T6OTL in control register T6CON. The second latch is an internal latch toggled by T6OTL's output. Both latch outputs are connected to the input control block of the auxiliary timer T5. The output level of the shadow latch will match the output level of T6OTL, but is delayed by one clock cycle. When the T6OTL value changes, this will result in a temporarily different output level from T6OTL and the shadow latch, which can trigger the selected count event in T5. When software writes to T6OTL, both latches are set or cleared simultaneously. In this case, both signals to the auxiliary timers carry the same level and no edge will be detected. Bit T6OE (overflow/underflow output enable) in register T6CON enables the state of T6OTL to be monitored via an external pin T6OUT. When T6OTL is linked to an external port pin (must be configured as output), T6OUT can be used to control external HW. If T6OE = 1, pin T6OUT outputs the state of T6OTL. If T6OE = 0, pin T6OUT outputs a high level (while it selects the timer output signal). As can be seen from Figure 14-21, when latch T6OTL is modified by software to determine the state of the output line, also the internal shadow latch is set or cleared accordingly. Therefore, no trigger condition is detected by T5 in this case. The General Purpose Timer Units Set/Clear (SW) TxOE MUX 1 Overflow/ Underflow 1 TxOTL Shadow Latch 0 TxOUT To Port Logic Core Timer Toggle Latch Logic To Aux. Timer Input Logic mc_gpt0106_otl.vsd Figure 14-21 Block Diagram of the Toggle Latch Logic of Core Timer T6 Note: T6 is also used to clock the timers in the CAPCOM units. For this purpose, there is a direct internal connection between the T6 overflow/underflow line and the CAPCOM timers (signal T6OUF). User's Manual GPT_X7, V2.0 14-37 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary The General Purpose Timer Units 14.2.2 GPT2 Core Timer T6 Operating Modes Timer 6 in Timer Mode Timer mode for the core timer T6 is selected by setting bitfield T6M in register T6CON to 000B. In this mode, T6 is clocked with the module's input clock fGPT divided by two programmable prescalers controlled by bitfields BPS2 and T6I in register T6CON. Please see Section 14.2.6 for details on the input clock options. T6IRQ fGPT Prescaler fT6 Count Core Timer T6 Toggle Latch T6OUT to T5/ BPS2 T6I T6R CAPREL T6UD 0 =1 T6EUD T6UDE 1 MUX T6OUF Up/Down MCB05403_X4 Figure 14-22 Block Diagram of Core Timer T6 in Timer Mode User's Manual GPT_X7, V2.0 14-38 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Gated Timer Mode Gated timer mode for the core timer T6 is selected by setting bitfield T6M in register T6CON to 010B or 011B. Bit T6M.0 (T6CON.3) selects the active level of the gate input. The same options for the input frequency are available in gated timer mode as in timer mode (see Section 14.2.6). However, the input clock to the timer in this mode is gated by the external input pin T6IN (Timer T6 External Input). To enable this operation, the associated pin T6IN must be configured as input (the corresponding direction control bit must contain 0). The General Purpose Timer Units T6IRQ fGPT Prescaler Gate Ctrl. fT6 Count Core Timer T6 Toggle Latch T6OUT to T5, BPS2 T6IN T6I T6R Clear CAPREL T6UD 0 =1 T6EUD T6UDE 1 MUX T6OUF Up/Down MCB05404_X4 Figure 14-23 Block Diagram of Core Timer T6 in Gated Timer Mode If T6M = 010B, the timer is enabled when T6IN shows a low level. A high level at this line stops the timer. If T6M = 011B, line T6IN must have a high level in order to enable the timer. Additionally, the timer can be turned on or off by software using bit T6R. The timer will only run if T6R is 1 and the gate is active. It will stop if either T6R is 0 or the gate is inactive. Note: A transition of the gate signal at pin T6IN does not cause an interrupt request. User's Manual GPT_X7, V2.0 14-39 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Counter Mode Counter mode for the core timer T6 is selected by setting bitfield T6M in register T6CON to 001B. In counter mode, timer T6 is clocked by a transition at the external input pin T6IN. The event causing an increment or decrement of the timer can be a positive, a negative, or both a positive and a negative transition at this line. Bitfield T6I in control register T6CON selects the triggering transition (see Table 14-11). T6IRQ Edge The General Purpose Timer Units T6IN Select Count Core Timer T6 Toggle Latch T6OUT to T5, T6R T6I T6UD 0 =1 T6EUD T6UDE 1 MUX Clear CAPREL T6OUF Up/Down MCB05405_X4 Figure 14-24 Block Diagram of Core Timer T6 in Counter Mode Table 14-11 GPT2 Core Timer T6 (Counter Mode) Input Edge Selection T6I 000 001 010 011 1XX Triggering Edge for Counter Increment/Decrement None. Counter T6 is disabled Positive transition (rising edge) on T6IN Negative transition (falling edge) on T6IN Any transition (rising or falling edge) on T6IN Reserved. Do not use this combination For counter mode operation, pin T6IN must be configured as input (the respective direction control bit DPx.y must be 0). The maximum input frequency allowed in counter mode depends on the selected prescaler value. To ensure that a transition of the count input signal applied to T6IN is recognized correctly, its level must be held high or low for a minimum number of module clock cycles before it changes. This information can be found in Section 14.2.6. User's Manual GPT_X7, V2.0 14-40 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary The General Purpose Timer Units 14.2.3 GPT2 Auxiliary Timer T5 Control Auxiliary timer T5 can be configured for timer mode, gated timer mode, or counter mode with the same options for the timer frequencies and the count signal as the core timer T6. In addition to these 3 counting modes, the auxiliary timer can be concatenated with the core timer. The contents of T5 may be captured to register CAPREL upon an external or an internal trigger. The start/stop function of the auxiliary timers can be remotely controlled by the T6 run control bit. Several timers may thus be controlled synchronously. The current contents of the auxiliary timer are reflected by its count register T5. This register can also be written to by the CPU, for example, to set the initial start value. The individual configurations for timer T5 are determined by its bitaddressable control register T5CON. Some bits in this register also control the function of the CAPREL register. Note that functions which are present in all timers of block GPT2 are controlled in the same bit positions and in the same manner in each of the specific control registers. Note: The auxiliary timer has no output toggle latch and no alternate output function. GPT12E_T5CON Timer 5 Control Register 15 14 13 CI rw 12 11 T5 CC rw 10 CT3 rw SFR (FF46H/A3H) 9 8 7 6 T5R rw 5 4 T5M rw Reset Value: 0000H 3 2 1 T5I rw 0 T5 T5 SC CLR rw rw T5 T5 T5 RC UDE UD rw rw rw Field T5SC Bits 15 Type rw Description Timer 5 Capture Mode Enable 0 Capture into register CAPREL Disabled 1 Capture into register CAPREL Enabled Timer T5 Clear Enable Bit 0 Timer T5 is not cleared on a capture event 1 Timer T5 is cleared on a capture event T5CLR 14 rw User's Manual GPT_X7, V2.0 14-41 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field CI Bits Type Description Register CAPREL Capture Trigger Selection (depending on bit CT3) 00 Capture disabled 01 Positive transition (rising edge) on CAPIN or any transition on T3IN 10 Negative transition (falling edge) on CAPIN or any transition on T3EUD 11 Any transition (rising or falling edge) on CAPIN or any transition on T3IN or T3EUD Timer T5 Capture Correction 0 T5 is just captured without any correction 1 T5 is decremented by 1 before being captured Timer T3 Capture Trigger Enable 0 Capture trigger from input line CAPIN 1 Capture trigger from T3 input lines T3IN and/or T3EUD Timer T5 Remote Control 0 Timer T5 is controlled by its own run bit T5R 1 Timer T5 is controlled by the run bit T6R of core timer 6, not by bit T5R Timer T5 External Up/Down Enable1) 0 Input T5EUD is disconnected 1 Direction influenced by input T5EUD Timer T5 Up/Down Control1) 0 Timer T5 counts up 1 Timer T5 counts down Timer T5 Run Bit 0 Timer T5 stops 1 Timer T5 runs Note: This bit only controls timer T5 if bit T5RC = 0. T5M [5:3] rw Timer T5 Mode Control (Basic Operating Mode) 000 Timer Mode 001 Counter Mode 010 Gated Timer Mode with gate active low 011 Gated Timer Mode with gate active high 1XX Reserved. Do not use this combination The General Purpose Timer Units [13:12] rw T5CC 11 rw CT3 10 rw T5RC 9 rw T5UDE 8 rw T5UD 7 rw T5R 6 rw User's Manual GPT_X7, V2.0 14-42 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field T5I Bits [2:0] Type rw Description Timer T5 Input Parameter Selection Depends on the operating mode, see respective sections for encoding: Table 14-15 for Timer Mode and Gated Timer Mode Table 14-11 for Counter Mode The General Purpose Timer Units 1) See Table 14-10 for encoding of bits T5UD and T5UDE. Timer T5 Run Control The auxiliary timer T5 can be started or stopped by software in two different ways: * Through the associated timer run bit (T5R). In this case it is required that the respective control bit T5RC = 0. * Through the core timer's run bit (T6R). In this case the respective remote control bit must be set (T5RC = 1). The selected run bit is relevant in all operating modes of T5. Setting the bit will start the timer, clearing the bit stops the timer. In gated timer mode, the timer will only run if the selected run bit is set and the gate is active (high or low, as programmed). Note: If remote control is selected T6R will start/stop timer T6 and the auxiliary timer T5 synchronously. User's Manual GPT_X7, V2.0 14-43 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary The General Purpose Timer Units 14.2.4 GPT2 Auxiliary Timer T5 Operating Modes The operation of the auxiliary timer in the basic operating modes is almost identical with the core timer's operation, with very few exceptions. Additionally, some combined operating modes can be selected. Timer T5 in Timer Mode Timer Mode for the auxiliary timer T5 is selected by setting its bitfield T5M in register T5CON to 000B. fT5 Count Auxiliary Timer T5 fGPT Prescaler T5IRQ BPS2 T5I T5R T6R 0 1 MUX Clear T5RC T5UD 0 =1 T5EUD T5UDE MCB05406_X4 MUX Up/Down 1 Figure 14-25 Block Diagram of Auxiliary Timer T5 in Timer Mode User's Manual GPT_X7, V2.0 14-44 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Timer T5 in Gated Timer Mode Gated timer mode for the auxiliary timer T5 is selected by setting bitfield T5M in register T5CON to 010B or 011B. Bit T5M.0 (T5CON.3) selects the active level of the gate input. Note: A transition of the gate signal at line T5IN does not cause an interrupt request. The General Purpose Timer Units fGPT Prescaler Gate Ctrl. fT5 Count Auxiliary Timer T5 T5IRQ BPS2 T5IN T5I Clear T5R T6R 0 1 MUX T5RC T5UD 0 =1 T5EUD T5UDE MCB05407_X4 MUX Up/Down 1 Figure 14-26 Block Diagram of Auxiliary Timer T5 in Gated Timer Mode Note: There is no output toggle latch for T5. Start/stop of the auxiliary timer can be controlled locally or remotely. Timer T5 in Counter Mode Counter mode for auxiliary timer T5 is selected by setting bitfield T5M in register T5CON to 001B. In counter mode, the auxiliary timer can be clocked either by a transition at its external input line T5IN, or by a transition of timer T6's toggle latch T6OTL. The event causing an increment or decrement of a timer can be a positive, a negative, or both a positive and a negative transition at either the respective input pin or at the toggle latch. Bitfield T5I in control register T5CON selects the triggering transition (see Table 14-12). User's Manual GPT_X7, V2.0 14-45 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary The General Purpose Timer Units T5IN T6 Toggle Latch 0 1 MUX Edge Count Select Auxiliary Timer T5 T5IRQ T5I.2 T5R T6R T5I 0 1 Clear MUX T5RC T5UD 0 =1 T5EUD T5UDE MCB05408_X4 MUX Up/Down 1 Figure 14-27 Block Diagram of Auxiliary Timer T5 in Counter Mode Table 14-12 GPT2 Auxiliary Timer (Counter Mode) Input Edge Selection T5I X00 001 010 011 101 110 111 Triggering Edge for Counter Increment/Decrement None. Counter T5 is disabled Positive transition (rising edge) on T5IN Negative transition (falling edge) on T5IN Any transition (rising or falling edge) on T5IN Positive transition (rising edge) of T6 toggle latch T6OTL Negative transition (falling edge) of T6 toggle latch T6OTL Any transition (rising or falling edge) of T6 toggle latch T6OTL Note: Only state transitions of T6OTL which are caused by the overflows/underflows of T6 will trigger the counter function of T5. Modifications of T6OTL via software will NOT trigger the counter function of T5. For counter operation, pin T5IN must be configured as input (the respective direction control bit DPx.y must be 0). The maximum input frequency allowed in counter mode depends on the selected prescaler value. To ensure that a transition of the count input signal applied to T5IN is recognized correctly, its level must be held high or low for a minimum number of module clock cycles before it changes. This information can be found in Section 14.2.6. User's Manual GPT_X7, V2.0 14-46 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Timer Concatenation Using the toggle bit T6OTL as a clock source for the auxiliary timer in counter mode concatenates the core timer T6 with the auxiliary timer T5. This concatenation forms either a 32-bit or a 33-bit timer/counter, depending on which transition of T6OTL is selected to clock the auxiliary timer. * 32-bit Timer/Counter: If both a positive and a negative transition of T6OTL are used to clock the auxiliary timer, this timer is clocked on every overflow/underflow of the core timer T6. Thus, the two timers form a 32-bit timer. * 33-bit Timer/Counter: If either a positive or a negative transition of T6OTL is selected to clock the auxiliary timer, this timer is clocked on every second overflow/underflow of the core timer T6. This configuration forms a 33-bit timer (16-bit core timer + T6OTL + 16-bit auxiliary timer). As long as bit T6OTL is not modified by software, it represents the state of the internal toggle latch, and can be regarded as part of the 33-bit timer. The count directions of the two concatenated timers are not required to be the same. This offers a wide variety of different configurations. T6, which represents the low-order part of the concatenated timer, can operate in timer mode, gated timer mode or counter mode in this case. The General Purpose Timer Units T6IRQ fGPT T6IN Operating Mode Control T6R Count Core Timer T6 Toggle Latch T6OUT BPS2 T6I Clear Up/Down T5IN 0 1 MUX Edge Count Select Auxiliary Timer T5 T5IRQ T5I.2 T5I T5R T6R 0 1 MUX Clear Up/Down T5RC MCA05409 Figure 14-28 Concatenation of Core Timer T6 and Auxiliary Timer T5 User's Manual GPT_X7, V2.0 14-47 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary The General Purpose Timer Units 14.2.5 GPT2 Register CAPREL Operating Modes The Capture/Reload register CAPREL can be used to capture the contents of timer T5, or to reload timer T6. A special mode facilitates the use of register CAPREL for both functions at the same time. This mode allows frequency multiplication. The capture function is triggered by the input pin CAPIN, or by GPT1 timer's T3 input lines T3IN and T3EUD. The reload function is triggered by an overflow or underflow of timer T6. In addition to the capture function, the capture trigger signal can also be used to clear the contents of timers T5 and T6 individually. The functions of register CAPREL are controlled via several bit(field)s in the timer control registers T5CON and T6CON. GPT2 Capture/Reload Register CAPREL in Capture Mode Capture mode for register CAPREL is selected by setting bit T5SC in control register T5CON (set bitfield CI in register T5CON to a non-zero value to select a trigger signal). In capture mode, the contents of the auxiliary timer T5 are latched into register CAPREL in response to a signal transition at the selected external input pin(s). Bit CT3 selects the external input line CAPIN or the input lines T3IN and/or T3EUD of GPT1 timer T3 as the source for a capture trigger. Either a positive, a negative, or both a positive and a negative transition at line CAPIN can be selected to trigger the capture function, or transitions on input T3IN or input T3EUD or both inputs, T3IN and T3EUD. The active edge is controlled by bitfield CI in register T5CON. Table 14-13 summarizes these options. Table 14-13 CAPREL Register Input Edge Selection CT3 X 0 0 0 1 1 1 CI 00 01 10 11 01 10 11 Triggering Signal/Edge for Capture Mode None. Capture Mode is disabled. Positive transition (rising edge) on CAPIN. Negative transition (falling edge) on CAPIN. Any transition (rising or falling edge) on CAPIN. Any transition (rising or falling edge) on T3IN. Any transition (rising or falling edge) on T3EUD. Any transition (rising or falling edge) on T3IN or T3EUD. User's Manual GPT_X7, V2.0 14-48 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary The General Purpose Timer Units Count Clock Clear Auxiliary Timer T5 T5IRQ Up/Down Edge CAPIN Select T5CLR 0 1 MUX Capture Capture Correction T5CC T3IN T3EUD Signal Select CT3 T5SC CAPREL Register CI CRIRQ Clear T6 T6CLR MCA05410 Figure 14-29 GPT2 Register CAPREL in Capture Mode When a selected trigger is detected, the contents of the auxiliary timer T5 are latched into register CAPREL and the interrupt request line CRIRQ is activated. The same event can optionally clear timer T5 and/or timer T6. This option is enabled by bit T5CLR in register T5CON and bit T6CLR in register T6CON, respectively. If TxCLR = 0 the contents of timer Tx is not affected by a capture. If TxCLR = 1 timer Tx is cleared after the current timer T5 value has been latched into register CAPREL. Note: Bit T5SC only controls whether or not a capture is performed. If T5SC is cleared the external input pin(s) can still be used to clear timer T5 and/or T6, or as external interrupt input(s). This interrupt is controlled by the CAPREL interrupt control register CRIC. When capture triggers T3IN or T3EUD are enabled (CT3 = 1), register CAPREL captures the contents of T5 upon transitions of the selected input(s). These values can be used to measure T3's input signals. This is useful, for example, when T3 operates in User's Manual GPT_X7, V2.0 14-49 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary The General Purpose Timer Units incremental interface mode, in order to derive dynamic information (speed, acceleration) from the input signals. For capture mode operation, the selected pins CAPIN, T3IN, or T3EUD must be configured as input. To ensure that a transition of a trigger input signal applied to one of these inputs is recognized correctly, its level must be held high or low for a minimum number of module clock cycles, detailed in Section 14.2.6. GPT2 Capture/Reload Register CAPREL in Reload Mode Reload mode for register CAPREL is selected by setting bit T6SR in control register T6CON. In reload mode, the core timer T6 is reloaded with the contents of register CAPREL, triggered by an overflow or underflow of T6. This will not activate the interrupt request line CRIRQ associated with the CAPREL register. However, interrupt request line T6IRQ will be activated, indicating the overflow/underflow of T6. CAPREL Register Reload T6SR T6IRQ Count Clock Core Timer T6 Toggle Latch T6OUT T6OUF to T5 MCA05411 Up/Down Figure 14-30 GPT2 Register CAPREL in Reload Mode User's Manual GPT_X7, V2.0 14-50 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary The General Purpose Timer Units GPT2 Capture/Reload Register CAPREL in Capture-And-Reload Mode Since the reload function and the capture function of register CAPREL can be enabled individually by bits T5SC and T6SR, the two functions can be enabled simultaneously by setting both bits. This feature can be used to generate an output frequency that is a multiple of the input frequency. Count Clock Clear Auxiliary Timer T5 T5IRQ Up/Down Edge CAPIN Select T5CLR 0 1 MUX Capture Capture Correction T5CC T3IN T3EUD Edge CT3 Select T5SC CAPREL Register CI CRIRQ Reload Clear T6SR T6IRQ T6CLR Count Clock Core Timer T6 Toggle Latch T6OUT T6OUF to T5 MCA05412 Up/Down Figure 14-31 GPT2 Register CAPREL in Capture-And-Reload Mode This combined mode can be used to detect consecutive external events which may occur aperiodically, but where a finer resolution, that means, more `ticks' within the time between two external events is required. For this purpose, the time between the external events is measured using timer T5 and the CAPREL register. Timer T5 runs in timer mode counting up with a frequency of e.g. fGPT/32. The external events are applied to pin CAPIN. When an external event occurs, User's Manual GPT_X7, V2.0 14-51 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary The General Purpose Timer Units the contents of timer T5 are latched into register CAPREL and timer T5 is cleared (T5CLR = 1). Thus, register CAPREL always contains the correct time between two events, measured in timer T5 increments. Timer T6, which runs in timer mode counting down with a frequency of e.g. fGPT/4, uses the value in register CAPREL to perform a reload on underflow. This means, the value in register CAPREL represents the time between two underflows of timer T6, now measured in timer T6 increments. Since (in this example) timer T6 runs 8 times faster than timer T5, it will underflow 8 times within the time between two external events. Thus, the underflow signal of timer T6 generates 8 `ticks'. Upon each underflow, the interrupt request line T6IRQ will be activated and bit T6OTL will be toggled. The state of T6OTL may be output on pin T6OUT. This signal has 8 times more transitions than the signal which is applied to pin CAPIN. Note: The underflow signal of Timer T6 can furthermore be used to clock one or more of the timers of the CAPCOM units, which gives the user the possibility to set compare events based on a finer resolution than that of the external events. This connection is accomplished via signal T6OUF. Capture Correction A certain deviation of the output frequency is generated by the fact that timer T5 will count actual time units (e.g. T5 running at 1 MHz will count up to the value 64H/100D for a 10 kHz input signal), while T6OTL will only toggle upon an underflow of T6 (i.e. the transition from 0000H to FFFFH). In the above mentioned example, T6 would count down from 64H, so the underflow would occur after 101 timing ticks of T6. The actual output frequency then is 79.2 kHz, instead of the expected 80 kHz. This deviation can be compensated for by activating the Capture Correction (T5CC = 1). If capture correction is active, the contents of T5 are decremented by 1 before being captured. The described deviation is eliminated (in the example, T5 would count up to the value 64H/100D, but the CAPREL register will capture the decremented value 63H/99D, T6 would count exactly 100 ticks, and the output frequency is 80 kHz). User's Manual GPT_X7, V2.0 14-52 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary The General Purpose Timer Units 14.2.6 GPT2 Clock Signal Control All actions within the timer block GPT2 are triggered by transitions of its basic clock. This basic clock is derived from the system clock by a basic block prescaler, controlled by bitfield BPS2 in register T6CON (see Figure 14-20). The count clock can be generated in two different ways: * Internal count clock, derived from GPT2's basic clock via a programmable prescaler, is used for (gated) timer mode. * External count clock, derived from the timer's input pin(s), is used for counter mode. For both ways, the basic clock determines the maximum count frequency and the timer's resolution: Table 14-14 Basic Clock Selection for Block GPT2 Block Prescaler1) BPS2 = 01B BPS2 = 00B2) F(BPS2) =4 BPS2 = 11B F(BPS2) =8 BPS2 = 10B F(BPS2) = 16 Prescaling Factor F(BPS2) for GPT2: F(BPS2) = 2 Maximum External fGPT/4 Count Frequency Input Signal Stable Time 2) Default after reset. fGPT/8 4 x tGPT fGPT/16 8 x tGPT fGPT/32 16 x tGPT 2 x tGPT 1) Please note the non-linear encoding of bitfield BPS2. Internal Count Clock Generation In timer mode and gated timer mode, the count clock for each GPT2 timer is derived from the GPT2 basic clock by a programmable prescaler, controlled by bitfield TxI in the respective timer's control register TxCON. The count frequency fTx for a timer Tx and its resolution rTx are scaled linearly with lower clock frequencies, as can be seen from the following formula: f GPT f Tx = ------------------------------------------- F ( BPS2 ) x 2 r Tx [ s ] = -------------------------------------------f GPT [ MHz ] F ( BPS2 ) x 2 [14.2] The effective count frequency depends on the common module clock prescaler factor F(BPS2) as well as on the individual input prescaler factor 2 User's Manual GPT_X7, V2.0 14-53 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary The General Purpose Timer Units Table 14-15 GPT2 Overall Prescaler Factors for Internal Count Clock Individual Common Prescaler for Module Clock1) Prescaler for Tx BPS2 = 01 BPS2 = 00B BPS2 = 11B BPS2 = 10B B TxI = 000B TxI = 001B TxI = 010B TxI = 011B TxI = 100B TxI = 101B TxI = 110B TxI = 111B 2 4 8 16 32 64 128 256 4 8 16 32 64 128 256 512 8 16 32 64 128 256 512 1024 16 32 64 128 256 512 1024 2048 1) Please note the non-linear encoding of bitfield BPS2. Table 14-16 lists a timer's parameters (such as count frequency, resolution, and period) resulting from the selected overall prescaler factor and the applied system frequency. Note that some numbers may be rounded. Table 14-16 GPT2 Timer Parameters System Clock = 10 MHz Frequency 5.0 MHz 2.5 MHz 1.25 MHz 625.0 kHz 312.5 kHz 156.25 kHz 78.125 kHz 39.06 kHz 19.53 kHz 9.77 kHz 4.88 kHz Resolution Period 200 ns 400 ns 800 ns 1.6 s 3.2 s 6.4 s 12.8 s 25.6 s 51.2 s 102.4 s 204.8 s Overall Divider Factor System Clock = 40 MHz Frequency Resolution Period 20.0 MHz 10.0 MHz 5.0 MHz 2.5 MHz 1.25 MHz 625.0 kHz 312.5 kHz 50 ns 100 ns 200 ns 400 ns 800 ns 1.6 s 3.2 s 3.28 ms 6.55 ms 13.11 ms 26.21 ms 52.43 ms 104.9 ms 209.7 ms 419.4 ms 838.9 ms 1.678 s 3.355 s 13.11 ms 2 26.21 ms 4 52.43 ms 8 104.9 ms 16 209.7 ms 32 419.4 ms 64 838.9 ms 128 1.678 s 3.355 s 6.711 s 13.42 s 256 512 1024 2048 156.25 kHz 6.4 s 78.125 kHz 12.8 s 39.06 kHz 19.53 kHz 25.6 s 51.2 s User's Manual GPT_X7, V2.0 14-54 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary External Count Clock Input The external input signals of the GPT2 block are sampled with the GPT2 basic clock (see Figure 14-20). To ensure that a signal is recognized correctly, its current level (high or low) must be held active for at least one complete sampling period, before changing. A signal transition is recognized if two subsequent samples of the input signal represent different levels. Therefore, a minimum of two basic clock periods are required for the sampling of an external input signal. Thus, the maximum frequency of an input signal must not be higher than half the basic clock. Table 14-17 summarizes the resulting requirements for external GPT2 input signals. Table 14-17 GPT2 External Input Signal Limits System Clock = 10 MHz Input Max. Input Min. Level Frequ. Frequency Hold Time Factor 2.5 MHz 1.25 MHz 625.0 kHz 312.5 kHz 200 ns 400 ns 800 ns 1.6 s GPT2 Divider BPS1 01B 00B 11B 10B Input System Clock = 40 MHz Phase Max. Input Min. Level Duration Frequency Hold Time 2 x tGPT 4 x tGPT 8 x tGPT 16 x tGPT 10.0 MHz 5.0 MHz 2.5 MHz 1.25 MHz 50 ns 100 ns 200 ns 400 ns The General Purpose Timer Units fGPT/4 fGPT/8 fGPT/16 fGPT/32 These limitations are valid for all external input signals to GPT2, including the external count signals in counter mode and the gate input signals in gated timer mode. User's Manual GPT_X7, V2.0 14-55 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary The General Purpose Timer Units 14.2.7 GPT2 Timer Registers GPT12E_T5 Timer 5 Count Register GPT12E_T6 Timer 6 Count Register 15 14 13 12 11 10 SFR (FE46H/23H) SFR (FE48H/24H) 9 8 7 6 5 4 Reset Value: 0000H Reset Value: 0000H 3 2 1 0 Txvalue rwh Field Txvalue Bits [15:0] Type Description rwh Current timer value GPT12E_CAPREL Capture/Reload Register 15 14 13 12 11 10 SFR (FE4AH/25H) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 CapRelvalue rwh Field CapRel value Bits [15:0] Type Description rwh Current reload value or Captured value User's Manual GPT_X7, V2.0 14-56 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary The General Purpose Timer Units 14.2.8 Interrupt Control for GPT2 Timers and CAPREL When a timer overflows from FFFFH to 0000H (when counting up), or when it underflows from 0000H to FFFFH (when counting down), its interrupt request flag (T5IR or T6IR) in register TxIC will be set. Whenever a transition according to the selection in bit field CI is detected at pin CAPIN, interrupt request flag CRIR in register CRIC is set. Setting any request flag will cause an interrupt to the respective timer or CAPREL interrupt vector (T5INT, T6INT or CRINT) or trigger a PEC service, if the respective interrupt enable bit (T5IE or T6IE in register TxIC, CRIE in register CRIC) is set. There is an interrupt control register for each of the two timers and for the CAPREL register. GPT12E_T5IC Timer 5 Intr. Ctrl. Reg. 15 14 13 12 11 10 - SFR (FF66H/B3H) 9 8 7 6 5 4 Reset Value: - - 00H 3 2 1 0 GPX T5IR T5IE rw rwh rw ILVL rw GLVL rw GPT12E_T6IC Timer 6 Intr. Ctrl. Reg. 15 14 13 12 11 10 - SFR (FF68H/B4H) 9 8 7 6 5 4 Reset Value: - - 00H 3 2 1 0 GPX T6IR T6IE rw rwh rw ILVL rw GLVL rw GPT12E_CRIC CAPREL Intr. Ctrl. Reg. 15 14 13 12 11 10 - SFR (FF6AH/B5H) 9 8 7 6 5 4 Reset Value: - - 00H 3 2 1 0 GPX CRIR CRIE rw rwh rw ILVL rw GLVL rw Note: Please refer to the general Interrupt Control Register description for an explanation of the control fields. User's Manual GPT_X7, V2.0 14-57 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary The General Purpose Timer Units 14.2.9 KSCCFG Register GPT12E_KSCCFG Kernel State Configuration Register SFR(FE1CH) 15 BP COM w 14 13 12 11 BP SUM w 10 9 8 7 BP NOM w 6 5 4 Reset Value: 0000H 3 2 1 0 0 COMCFG 0 SUMCFG 0 NOMCFG 0 BP MOD MOD EN EN w rw r rw r rw r rw r Field MODEN Bits 0 Type Description rw Module Enable This bit enables the module kernel clock and the module functionality. 0B The module is switched off. It does not react on mode control actions and the module clock is switched off immediately (without stop condition). The module does not react on read accesses and ignores write accesses. 1B The module is switched on. Note: This bit is reset by an application reset. Bit Protection for MODEN This bit enables the write access to the bit MODEN. It always reads 0. It is only active during the write access cycle. MODEN is not changed. 0B 1B MODEN is updated with the written value. Note: This bit is reset by an application reset. Normal Operation Mode Configuration This bit field defines the kernel mode applied in normal operation mode. 0XB The module is switched on. 1XB The module is switched off. This field is taken into account for CR = 00 or 11. Note: This bit is reset by an application reset. BPMODE 1 w NOMCFG [5:4] rw User's Manual GPT_X7, V2.0 14-58 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field BPNOM Bits 7 Type Description w Bit Protection for NOMCFG This bit enables the write access to the bit field NOMCFG. It always reads 0. It is only active during the write access cycle. 0B NOMCFG is not changed. 1B NOMCFG is updated with the written value. Note: This bit is reset by an application reset. SUMCFG [9:8] rw Suspend Mode Configuration This bit field defines the kernel mode applied in suspend mode. 0XB The module is switched on. 1XB The module is switched off. This field is taken into account for CR = 01. Note: This bit is reset by a debug reset. BPSUM 11 w Bit Protection for SUMCFG This bit enables the write access to the bit field SUMCFG. It always reads 0. It is only active during the write access cycle. SUMCFG is not changed. 0B 1B SUMCFG is updated with the written value. Note: This bit is reset by a debug reset. COMCFG [13:12] rw Clock Off Mode Configuration This bit field defines the kernel mode applied in clock off mode. 0XB The module is switched on. 1XB The module is switched off. This field is taken into account for CR = 10. Note: This bit is reset by an application reset. BPCOM 15 w Bit Protection for COMCFG This bit enables the write access to the bit field COMCFG. It always reads 0. It is only active during the write access cycle. 0B COMCFG is not changed. 1B COMCFG is updated with the written value. Note: This bit is reset by an application reset. 0 [3:2], 6, 10, 14 r Reserved; returns 0 if read; should be written with 0; The General Purpose Timer Units User's Manual GPT_X7, V2.0 14-59 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary The General Purpose Timer Units 14.3 Interfaces of the GPT Module Besides the described intra-module connections, the timer unit blocks GPT1 and GPT2 are connected to their environment in two basic ways (see Figure 14-32): * Internal connections interface the timers with on-chip resources such as clock generation unit, interrupt controller, or other timers. The GPT module is clocked with the XC2000 system clock, so fGPT = fSYS. * External connections interface the timers with external resources via port pins. System Control Unit fSYS = fG PT GPTDIS T2IN T2EUD T4IN P4.2 P4.3 P4.6 P4.7 P5.3 Port Logic P5.4 P6.1, P6.3, P7.0 P15.2 P15.4 P15.3 P15.5 P2.10 P6.2, P7.0, T2IRQ T3IRQ Interrupt Control Unit T4IRQ T5IRQ T6IRQ CRIRQ T4EUD T3IN General Purpose Timer Units T3EUD T3OUT T5IN T6IN T5EUD T6EUD CAPCOM2 Unit T6OUF CAPIN T6OUT MC_GPT0105_MODINTERFACE Figure 14-32 GPT Module Interfaces Port pins to be used for timer input signals must be switched to input (bitfield PC in the respective port control register must be 0xxxB). Port pins to be used for timer output signals must be switched to output and the alternate timer output signal must be selected (bitfield PC in the respective port control register must be 1xxxB). Note: For a description of the port control registers, please refer to Chapter 7. Interrupt nodes to be used for timer interrupt requests must be enabled and programmed to a specific interrupt level. User's Manual GPT_X7, V2.0 14-60 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Real Time Clock 15 Real Time Clock The Real Time Clock (RTC) module of the XC2000 basically consists of a chain of prescalers and timers. Its count clock is derived from the auxiliary oscillator or from the prescaled main oscillator. The RTC serves various purposes: * * * 48-bit timer for long term measurements System clock to determine the current time and date (the RTC's structure supports the direct representation of time and date) Cyclic time based interrupt (can be generated by any timer of the chain) A number of programming options as well as interrupt request signals adjust the operation of the RTC to the application's requirements. The RTC can continue its operation while the XC2000 is in certain power-saving modes, such that real time date and time information is provided. Control Registers RTC_CON RTCCLKCON E Data Registers RTC_T14REL E RTC_RELH RTC_RELL E E Counter Registers RTC_T14 RTC_RTCH RTC_RTCL T2CON E E E Interrupt Control RTC_ISNC RTC_IC E E RTC_CON RTCCLKCON RTC_ISNC RTC_IC Real Tim e Clock Control Register RTC Clock Control Register Interrupt Subnode Control Reg. RTC Interrupt Control Register RTC_T14 RTC_T14REL RTC_RTCH/L RTC_RELH/L Tim er T14 Count Register Tim er T14 Reload Register RTC Count Registers, High/Low RTC Reload Registers High/Low m c_rt cregx2k.vsd Figure 15-1 SFRs Associated with the RTC Module The RTC module consists of a chain of 3 divider blocks: * * * a selectable 8:1 divider (on - off) the reloadable 16-bit timer T14 the 32-bit RTC timer block (accessible via RTC_RTCH and RTC_RTCL), made of: - the reloadable 10-bit timer CNT0 - the reloadable 6-bit timer CNT1 - the reloadable 6-bit timer CNT2 - the reloadable 10-bit timer CNT3 All timers count upwards. Each of the five timers can generate an interrupt request. All requests are combined to a common node request. Note: The RTC registers are not affected by a functional reset in order to maintain the correct system time even when intermediate resets are executed. User's Manual RTC_X8, V2.1 15-1 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Real Time Clock 15.1 Defining the RTC Time Base The timer chain of the RTC is clocked with the count clock signal fRTC which is derived from internal sources (oscillators or PLL) or external sources (pins). The currently active clock source is selected by bitfield RTCCLKSEL in register RTCCLKCON. Optionally prescaled by a factor of 32 and/or 8, this is the basic RTC clock. Depending on the operating mode, timer T14 may provide the count increments used by the application and thus determine the input frequency of the RTC timer, that is, the RTC time base (see also Table 15-2). The RTC is also supplied with the system clock fSYS of the XC2000. This clock signal is used to control the RTC's logic blocks and its bus interface. To synchronize properly to the count clock, the system clock must run at least four times faster than the count clock, this means fSYS 4 x fCNT. RUN 0 32: 1 MUX 1 8: 1 MUX fRTC fCNT 1 0 RTC Count Clock PRE Async M ode Sync M ode 1 0 MUX fSYS RTC M odule Clock RTCCM MC_RTCCLOCKX2K Figure 15-2 RTC Clock Supply Block Diagram For an example, Table 15-1 lists the interrupt period range and the T14 reload values (for a time base of 1 s and 1 ms): Table 15-1 Oscillator Frequency 32.768 kHz RTC Time Base Examples T14 Intr. Period Min. Max. 30.52 s 16.0 s Reload Value A T14REL 8000H/F000H Base 1.000 s Reload Value B T14REL FFDFH/ FFFCH Base 1.007 ms/ 0.977 ms User's Manual RTC_X8, V2.1 15-2 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Real Time Clock Note: Select one value from the reload value pairs, depending if the 8:1 prescaler is disabled/enabled. Asynchronous Operation When the system clock frequency becomes lower than 4 x fCNT proper synchronization is not possible and count events may be missed. This can be the case, when the XC2000 reduces the system frequency to save power consumption. In these cases the RTC can be switched to Asynchronous Mode (by clearing bit RTCCM in register RTCCLKCON). In this mode the count registers are directly controlled by the count clock independent of the system clock (hence the name). Asynchronous operation ensures correct time-keeping even during power-save modes. However, as no synchronization between the count registers and the bus interface can be maintained in asynchronous mode, the RTC registers cannot be written. Read accesses may interfere with count events and, therefore, must be verified (e.g. by reading the same value with three consecutive read accesses). Note: The access restrictions in asynchronous mode are only meaningful if the system clock is not switched off, of course. Switching Clocking Modes The clocking mode of the RTC (synchronous or asynchronous) is selected via bit RTCCM in register RTCCLKCON. After reset, the RTC operates in Synchronous Mode (RTCCM = 1) with the 8:1 prescaler enabled. The selected clocking mode also affects the access to RTC registers. Bit ACCPOS in register RTC_CON indicates if full register access is possible (ACCPOS = 1, default after reset) or not (ACCPOS = 0). This also indicates the current clocking mode. Attention: Software should poll bit ACCPOS to determine the proper transition to the intended clocking mode. After switching to Asynchronous Mode (RTCCM = 0), bit ACCPOS = 0 indicates proper operation in Asynchronous Mode. In this case the system clock can be stopped or reduced. After switching to Synchronous Mode, (RTCCM = 1), bit ACCPOS = 1 indicates proper operation in Synchronous Mode. In this case the RTC registers can again be accessed properly (read and write). Note: The RTC might lose a counting event (edge of fCNT) when switching from synchronous mode to asynchronous mode while the 8:1 prescaler is disabled. For these applications it is, therefore, recommended to set up the RTC with the 8:1 prescaler enabled. User's Manual RTC_X8, V2.1 15-3 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Increased RTC Accuracy through Software Correction The accuracy of the XC2000's RTC is determined by the oscillator frequency and by the respective prescaling factor (excluding or including T14 and the 8:1 prescaler). The accuracy limit generated by the prescaler is due to the quantization of a binary counter (where the average is zero), while the accuracy limit generated by the oscillator frequency is due to the difference between the ideal and real frequencies (and therefore accumulates over time). This effect is predictable and can be compensated. The total accuracy of the RTC can be further increased via software for specific applications that demand a high time accuracy. The key to the improved accuracy is knowledge of the exact oscillator frequency. The relation of this frequency to the expected ideal frequency is a measure of the RTC's deviation. The number of cycles, N, after which this deviation causes an error of 1 cycle can be easily computed. So, the only action is to correct the count by 1 after each series of N cycles. The correction may be made cyclically, for instance, within an interrupt service routine, or by evaluating a formula when the RTC registers are read (for this the respective "last" RTC value must be available somewhere). Note: For the majority of applications, however, the standard accuracy provided by the RTC's structure will be more than sufficient. Adjusting the current RTC value would require reading and then writing the complete 48-bit value. This can only be accomplished by three successive accesses each. To avoid the hassle of reading/writing multi-word values, the RTC incorporates a correction option to simply add or suppress one count pulse. This is done by setting bit T14INC or T14DEC, respectively, in register RTC_CON. This will add an extra count pulse (T14INC) upon the next count event, or suppress the next count event (T14DEC). The respective bit remains set until its associated action has been performed and is automatically cleared by hardware after this event. Note: Setting both bits, T14INC and T14DEC, at the same time will have no effect on the count values. Real Time Clock User's Manual RTC_X8, V2.1 15-4 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Real Time Clock 15.2 RTC Run Control If the RTC shall operate bit RUN in register RTC_CON must be set (default after reset). Bit RUN can be cleared, for example, to exclude certain operation phases from time keeping. The RTC can be completely disabled by clearing the corresponding bit MODEN in register RTC_KSCCFG. Note: A valid count clock is required for proper RTC operation, of course. The RTC is reset by a power reset, a functional reset does not affect the RTC registers and its operation (RTC_IC will be reset, however). The initialization software must ensure the proper RTC operating mode. The RTC control register RTC_CON selects the basic operation of the RTC module. RTC_CON Control Register 15 ACC POS rh 14 13 12 11 10 - ESFR (F110H/88H) 9 8 7 6 5 4 Reset Value: 8003H 3 2 1 0 REF T14 T14 PRE RUN CLK INC DEC rw rwh rwh rw rw Field ACCPOS Bits 15 Type rh Description RTC Register Access Possible 0 No write access is possible, only asynchronous reads 1 Registers can be read and written RTC Input Source Prescaler (32:1) Disable 0 Input Prescaler enabled 1 Input Prescaler disabled Increment Timer T14 Value Setting this bit to 1 adds one count pulse upon the next count event, thus incrementing T14. This bit is cleared by hardware after incrementation. Decrement Timer T14 Value Setting this bit to 1 suppresses the next count event, thus decrementing T14. This bit is cleared by hardware after decrementation. RTC Input Source Prescaler (8:1) Enable 0 Prescaler disabled 1 Prescaler enabled REFCLK 4 rw T14INC 3 rwh T14DEC 2 rwh PRE 1 rw User's Manual RTC_X8, V2.1 15-5 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field RUN Bits 0 Type rw Description RTC Run Bit 0 RTC stopped 1 RTC runs Real Time Clock User's Manual RTC_X8, V2.1 15-6 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Real Time Clock 15.3 RTC Operating Modes The RTC can be configured for several operating modes according to the purpose it is meant to serve. These operating modes are configured by selecting appropriate reload values and interrupt signals. fRTC RUN M UX :32 M UX :8 Interrupt Sub Node CNT INT0 CNT INT1 CNT INT2 RTCINT CNT INT3 PRE REFCLK REL-Register T14REL 10 Bits 6 Bits 6 Bits 10 Bits f CNT T14 T14-Register 10 Bits 6 Bits 6 Bits 10 Bits CNT-Register M CB05568B Figure 15-3 RTC Block Diagram RTC Register Access The actual value of the RTC is indicated by the three registers T14, RTCL, and RTCH. As these registers are concatenated to build the RTC counter chain, internal overflows occur while the RTC is running. When reading or writing the RTC value, such internal overflows must be taken into account to avoid reading/writing corrupted values. Care must be taken, when reading the timer(s), as this requires up to three read accesses to the different registers with an inherent time delay between the accesses. An overflow from T14 to RTCL and/or from RTCL to RTCH might occur between the accesses, which needs to be taken into account appropriately. For example, reading/writing 0000H from/to RTCH and then accessing RTCL could produce a corrupted value as RTCL may overflow before it can be accessed. In this case, RTCH would be 0001H. The same precautions must be taken for T14 and T14REL. User's Manual RTC_X8, V2.1 15-7 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Real Time Clock Timer T14 and its reload register are accessed via dedicated locations. The four RTC counters CNT3 ... CNT0 are accessed via the two 16-bit RTC timer registers, RTCH and RTCL. The associated four reload values REL3 ... REL0 are accessed via the two 16-bit RTC reload registers, RELH and RELL. Prescaler T14 and T14 Reload Registers RTC_T14 T14 Count Register 15 14 13 12 11 10 ESFR(F0D2H/69H) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 T14CNT rwh Field T14CNT Bits [15:0] Typ rwh Description T14 counter RTC_T14REL T14 Reload Register 15 14 13 12 11 10 ESFR(F0D0H/68H) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 T14REL rw Field T14REL Bits [15:0] Typ rw Description T14 reload value User's Manual RTC_X8, V2.1 15-8 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Real Time Clock RTC_RTCH RTC Timer High Register 15 14 13 12 11 10 ESFR (F0D6H/6BH) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 CNT3 rwh CNT2 rwh Field CNTx (x = 3 ... 2) Bits [15:6], [5:0] Type rwh Description RTC Timer Count Section CNTx An overflow of bitfield CNT2 triggers a count pulse to count section CNT3 followed by a reload of CNT2 from bitfield REL2. In addition, an interrupt request is triggered. RTC_RTCL RTC Timer Low Register 15 14 13 12 11 10 ESFR (F0D4H/6AH) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 CNT1 rwh CNT0 rwh Field CNTx (x = 1 ... 0) Bits Type Description RTC Timer Count Section CNTx An overflow of bitfield CNTx triggers a count pulse to the next count section CNTx+1 followed by a reload of CNTx from bitfield RELx. In addition, an interrupt request is triggered. [15:10], rwh [9:0] User's Manual RTC_X8, V2.1 15-9 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary RTC_RELH RTC Reload High Register 15 14 13 12 11 10 Real Time Clock ESFR (F0CEH/67H) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 REL3 rw REL2 rw Field RELx (x = 3 ... 2) Bits [15:6], [5:0] Type rw Description RTC Reload Value RELx This bitfield is copied to bitfield CNTx upon an overflow of count section CNTx. RTC_RELL RTC Reload Low Register 15 14 13 12 11 10 ESFR (F0CCH/66H) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 REL1 rw REL0 rw Field RELx (x = 1 ... 0) Bits Type Description RTC Reload Value RELx This bitfield is copied to bitfield CNTx upon an overflow of count section CNTx. [15:10], rw [9:0] Note: The registers of the RTC receive their reset values only upon a power reset. User's Manual RTC_X8, V2.1 15-10 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Real Time Clock 15.4 48-bit Timer Operation The concatenation of timers T14 and COUNT0 ... COUNT3 can be regarded as a 48-bit timer which is clocked with the RTC input frequency, optionally divided by the prescaler. The reload registers T14REL, RELL, and RELH must be cleared to produce a true binary 48-bit timer. However, any other reload value may be used. Reload values other than zero must be used carefully, due to the individual sections of the RTC timer with their own individual overflows and reload values. The maximum usable timespan is 248 ( 1014) T14 input clocks (assuming no prescaler), which would equal more than 200 years at an oscillator frequency of 32 kHz. 15.5 System Clock Operation A real time system clock can be maintained that keeps on running also during power saving modes (optionally) and indicates the current time and date. This is possible because the RTC module is not affected by a functional reset. After a power reset, however, the RTC is reset and cleared. The resolution for this clock information is determined by the input clock of timer T14. By selecting appropriate reload values each cascaded timer can represent directly a part of the current time and/or date. Due to its width, T14 can adjust the RTC to the intended range of operation (time or date). The maximum usable timespan is achieved when T14REL is loaded with 0000H and so T14 divides by 216. System Clock Example The RTC count clock is fOSCa (8:1 prescaler off). By selecting appropriate reload values the RTC timers directly indicate the current time (see Figure 15-4 and Table 15-2). 3E8H REL3 04H REL2 04H REL1 018H REL0 FFDFH T14REL CNT3 Hours CNT2 Minutes CNT1 Seconds CNT0 1/1000 Seconds T14 Prescaler fCNT = 32.768 kHz MCA05414 Figure 15-4 RTC Configuration Example Note: This setup can generate an interrupt request every millisecond, every second, every minute, every hour, or every day. User's Manual RTC_X8, V2.1 15-11 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Real Time Clock Each timer in the chain divides the clock by (2 1) T14 errors in the first example (ms) can be compensated either by choosing an adapted value for REL0, or by using software correction. 15.6 Cyclic Interrupt Generation The RTC module can generate an interrupt request whenever one of the timers overflows and is reloaded. This interrupt request may be used, for example, to provide a system time tick independent of the CPU frequency without loading the general purpose timers, or to wake-up regularly from sleep mode. The interrupt cycle time can be adjusted by choosing appropriate reload values and by enabling the appropriate interrupt request. In this mode, the other operating modes can be combined. For example, a reload value of T14REL = F9C0H (216 - 1600) generates a T14 interrupt request every 50 ms to wake-up the system regularly. Still the subsequent timers can be configured to represent the time or build a binary counter, however with a different time base. User's Manual RTC_X8, V2.1 15-12 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Real Time Clock 15.7 RTC Interrupt Generation The overflow signals of each timer of the RTC timer chain can generate an interrupt request. The RTC's interrupt subnode control register ISNC combines these requests to activate the common RTC interrupt request line RTC_IRQ. Each timer overflow sets its associated request flag in register ISNC. Individual enable bits for each request flag determine whether this request also activates the common interrupt line. The enabled requests are ORed together on this line (see Figure 15-5). The interrupt handler can determine the source of an interrupt request via the specific request flags and must clear them after appropriate processing (not cleared by hardware). The common node request bit is automatically cleared when the interrupt handler is vectored to. Note: If only one source is enabled, no additional software check is required, of course. Both the individual request and the common interrupt node must be enabled. Register RTC_ISNC CNT3 Overflow Set CNT3 IR SW Clear Set CNT2 IR SW Clear Set CNT1 IR SW Clear Set CNT0 IR SW Clear Set T14 IR SW Clear & T14 IE MCB05415 & CNT3 IE CNT2 Overflow & CNT2 IE _ >1 CNT1 Overflow & CNT1 IE Interrupt Request RTC_IRQ CNT0 Overflow & CNT0 IE T14 Overflow Figure 15-5 Interrupt Block Diagram User's Manual RTC_X8, V2.1 15-13 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary RTC_ISNC Interrupt Subnode Ctrl. Reg. 15 14 13 12 11 10 - Real Time Clock ESFR (F10CH/86H) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 CNT CNT CNT CNT CNT CNT CNT CNT T14 T14 3IR 3IE 2IR 2IE 1IR 1IE 0IR 0IE IR IE rwh rw rwh rw rwh rw rwh rw rwh rw Field CNTxIR (x = 3 ... 0) CNTxIE (x = 3 ... 0) T14IR Bits Type Description Section CNTx Interrupt Request Flag 0 No request pending 1 This source has raised an interrupt request Section CNTx Interrupt Enable Control Bit 0 Interrupt request is disabled 1 Interrupt request is enabled T14 Overflow Interrupt Request Flag 0 No request pending 1 This source has raised an interrupt request T14 Overflow Interrupt Enable Control Bit 0 Interrupt request is disabled 1 Interrupt request is enabled 9, 7, 5, rwh 3 8, 6, 4, rw 2 1 rwh T14IE 0 rw Note: The interrupt request flags in register ISNC must be cleared by software. They are not cleared automatically when the service routine is entered. RTC_IC RTC Interrupt Ctrl. Reg. 15 14 13 12 11 10 - ESFR (F19CH/CEH) 9 8 GPX rw 7 6 5 4 Reset Value: 0000H 3 2 1 0 RTC RTC IR IE rwh rw ILVL rw GLVL rw Note: Please refer to the general Interrupt Control Register description for an explanation of the control fields. Register RTC_IC is not part of the RTC module and is reset with any system reset. User's Manual RTC_X8, V2.1 15-14 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Real Time Clock 15.8 KSCCFG Register RTC_KSCCFG Kernel State Configuration Register ESFR(F010H) 15 BP COM w 14 0 r 13 12 11 BP SUM w 10 0 r 9 8 7 BP NOM w 6 0 r 5 4 Reset Value: 0001H 3 0 r 2 1 0 BP MOD MOD EN EN w rw COMCFG rw SUMCFG rw NOMCFG rw Field MODEN Bits 0 Type Description rw Module Enable This bit enables the module kernel clock and the module functionality. 0B The module is switched off. It does not react on mode control actions and the module clock is switched off immediately (without stop condition). The module does not react on read accesses and ignores write accesses. 1B The module is switched on. Note: This bit is reset by an application reset. Bit Protection for MODEN This bit enables the write access to the bit MODEN. It always reads 0. It is only active during the write access cycle. 0B MODEN is not changed. 1B MODEN is updated with the written value. Note: This bit is reset by an application reset. Normal Operation Mode Configuration This bit field defines the kernel mode applied in normal operation mode. 0XB The module is switched on. 1XB The module is switched off. This field is taken into account for CR = 00 or 11. Note: This bit is reset by an application reset. BPMODE 1 w NOMCFG [5:4] rw User's Manual RTC_X8, V2.1 15-15 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field BPNOM Bits 7 Type Description w Bit Protection for NOMCFG This bit enables the write access to the bit field NOMCFG. It always reads 0. It is only active during the write access cycle. 0B NOMCFG is not changed. 1B NOMCFG is updated with the written value. Note: This bit is reset by an application reset. SUMCFG [9:8] rw Suspend Mode Configuration This bit field defines the kernel mode applied in suspend mode. 0XB The module is switched on. 1XB The module is switched off. This field is taken into account for CR = 01. Note: This bit is reset by a debug reset. BPSUM 11 w Bit Protection for SUMCFG This bit enables the write access to the bit field SUMCFG. It always reads 0. It is only active during the write access cycle. SUMCFG is not changed. 0B 1B SUMCFG is updated with the written value. Note: This bit is reset by a debug reset. COMCFG [13:12] rw Clock Off Mode Configuration This bit field defines the kernel mode applied in clock off mode. 0XB The module is switched on. 1XB The module is switched off. This field is taken into account for CR = 10. Note: This bit is reset by an application reset. BPCOM 15 w Bit Protection for COMCFG This bit enables the write access to the bit field COMCFG. It always reads 0. It is only active during the write access cycle. 0B COMCFG is not changed. 1B COMCFG is updated with the written value. Note: This bit is reset by an application reset. 0 [3:2], 6, 10, 14 r Reserved; returns 0 if read; should be written with 0; Real Time Clock User's Manual RTC_X8, V2.1 15-16 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16 Analog to Digital Converter The Analog to Digital Converter module (ADC) of the XC2000 allows the conversion of analog input values into discrete digital values based on the successive approximation method. With this method, the conversion result is elaborated bit by bit, starting with the most significant bit. As a consequence, an analog to digital conversion requires a certain number of clock cycles. This chapter is structured as follows: * * * Introduction (see Section 16.1) Operating the ADC (see Section 16.2) Module implementation in XC2000 (see Section 16.3) 16.1 Introduction This section gives an overview about the feature set of the ADC module and introduces the general structure. It describes the: * * * * * * * * * ADC block diagram with two kernels (see Section 16.1.1) Feature set description (see Section 16.1.2) Abbreviations (see Section 16.1.3) Kernel overview (see Section 16.1.4) Conversion request handling (see Section 16.1.5) Conversion result handling (see Section 16.1.6) Interrupt structure (see Section 16.1.7) Electrical models (see Section 16.1.8) Transfer characteristics and error definitions (see Section 16.1.9) User's Manual ADC, UM_V0.1D6 16-1 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.1.1 ADC Block Diagram The ADC module contains 2 independent kernels (ADC0, ADC1) that can operate autonomously or can be synchronized to each other. An ADC kernel is a unit used to convert an analog input signal into a digital value and provides means for triggering conversions, data handling and storage. With this structure, parallel conversion of up to two analog input channels is supported. ADC kernel 0 analog inputs AD converter conversion control ADC kernel 1 analog inputs AD converter conversion control data (result) handling request control ADC_2_kernels data (result) handling request control bus interface Figure 16-1 ADC Module Block Diagram ... ... User's Manual ADC, UM_V0.1D6 16-2 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.1.2 * * * * Feature Set Features of each ADC kernel: Analog supply voltage range from 3.3 V (minimum) to 5 V (nominal) for VDDPA Input voltage range from 0 V to analog supply voltage VDDPA Input multiplexer for a maximum of 16 possible analog input channels Performance for 10-bit resolution (@fADCI = 16 MHz): - conversion time less than 1.5 s, 2 LSB10 TUE1) @ supply voltage VDDPA = 5 V - conversion time about 1.5 s, tbd LSB10 TUE @ supply voltage VDDPA = 3.3 V One standard reference input (VAREF) and one alternative reference input (CH0) available 3 conversion request sources for external or timer-driven events, auto-scan, programmable sequences, SW-driven conversions, etc. Synchronization of the ADC kernels for concurrent conversion starts and parallel sampling and measuring of analog input signals, e.g. for phase current measurements in AC drives Control capability for an external analog multiplexer, respecting the additional set up time Adjustable sampling times to accommodate output impedance of different analog signal sources (sensors, etc.) Possibility to cancel running conversions on demand with automatic restart Flexible interrupt generation (possibility of PEC support) Limit checking to reduce interrupt load (e.g. for temperature measurements or overload detection, only values exceeding a programmable level lead to an interrupt) Programmable data reduction filter, e.g. for digital anti-aliasing filtering, by adding a programmable number of conversion results Independent result registers (8 independent registers) Support of conversion result FIFO mechanism to allow a longer interrupt latency Support of suspend and power saving modes Individually programmable reference selection for each channel, e.g. to allow measurements of 3.3 V and 5 V signals in the full measurement range with the same ADC kernel * * * * * * * * * * * * * 1) This value reflects the ADC module capability in an adapted electrical environment, e.g. characterized by "clean" routing of analog and digital signals and separation of analog and digital PCB areas, low noise on analog power supply (< 30 mV), low switching activity of digital pins near to the ADC, etc. User's Manual ADC, UM_V0.1D6 16-3 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.1.3 Abbreviations The following acronyms and terms are used in the ADC chapter: Table 16-1 Abbreviation ADC DNL FIFO INL LSBn Abbreviations in ADC chapter Meaning analog to digital converter differential non-linearity error first-in-first-out data buffer mechanism integral non-linearity error finest granularity of the analog value in digital format, represented by one least significant bit of the conversion result with n bits resolution (measurement range divided in 2n equally distributed steps) peripheral event controller (DMA-like mechanism of 16 bit controller) system control unit of the device total unadjusted error PEC SCU TUE User's Manual ADC, UM_V0.1D6 16-4 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.1.4 * ADC Kernel Overview Each ADC kernel comprises: An analog to digital converter with a maximum of 16 analog inputs (CH0 - CH15). This block selects an input signal and translates the analog voltage into a digital value. Not all analog input channels are necessarily available in all packages, please refer to the implementation description in Section 16.3. A conversion control unit defining the conversion parameters like the length of the sample phase, the resolution and the reference for each conversion. The length of the sample phase and the resolution depend on the type of sensor (or other analog sources) connected to the ADC. These values are similar for several channels and, therefore, are grouped together to form the so-called input classes. Each channel can be individually assigned to an input class to define these parameters. The conversion control also handles the start conditions for the conversions, such as the immediate start (cancel-inject-repeat), overwrite of former results (wait-for-read), or synchronization of the ADC kernels (parallel conversions). Additionally, an external analog multiplexer can be controlled by the output signals EMUX[2:0] of each ADC kernel. A request control unit defining which analog input channel has to be converted next. It contains 3 request sources that can trigger conversions depending on different events, such as edges of PWM or timer signals or events at port pins. Each request source can trigger either 1, up to 4, or up to 16 conversions in a sequence. A result handling unit providing 8 result registers for the conversion results. The conversion result of each analog input channel can be directed to one of the result registers to be stored there. The result handling block also supports data reduction (e.g. for digital anti-aliasing filtering) by automatically adding up to 4 conversion results before informing the CPU that new data is available. Additionally, the results registers can be concatenated to FIFO structures to provide storage capability for more than one conversion result without overwriting previous data. This feature also helps to handle CPU latency effects. An interrupt generation unit issuing interrupt requests to the CPU depending on ADC events. The interrupt generation in the ADC kernels support different mechanisms, e.g. some interrupts can be coupled to a value range of the conversion result (limit checking), some interrupts can be used to transport conversion data to locations in memory for further treatment, and other interrupts are generated after a complete sequence of conversions. * * * * User's Manual ADC, UM_V0.1D6 16-5 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter standard analog reference VAREF analog reference ground VAGND analog input channel CH0 ... ADC kernel interrupt generation analog input channel CH15 external multiplexer control EMUX[2:0] AD converter result handling conversion control request control ADC_kernel _overv Figure 16-2 ADC Kernel Block Diagram The number NCONV10 of fADCI clock cycles needed for a 10-bit conversion is given by the following equation: NCONV10 = 17 (minimum sample time + conversion time) + additional sample time An additional sample time can be programmed to adapt to application requirements (the minimum sample time of 2 clock cycles of fADCA part can be extended by a programmable value). User's Manual ADC, UM_V0.1D6 16-6 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.1.5 Conversion Request Unit The conversion request unit of each ADC kernel autonomously handles the generation of conversion requests. It contains three independent request sources that are connected to several modules to trigger the start of a conversion. A request source defines the analog input channel to be converted if a defined event occurs. For example, a trigger pulse from a timer unit generating a PWM signal can start the conversion of a single input channel or a programmed sequence of input channels. Depending on the application, the request sources can be triggered by different events, either issued by other modules or under SW control. As a consequence, there can be two or more conversion requests pending at the same time. To allow the user to adapt the request source mechanism to the application needs, the trigger capability, the channel number(s) to be converted, and the priority can be individually programmed for each request source. An arbiter block regularly scans the request sources for pending conversion requests and acts upon the conversion request with the highest priority. This conversion request is forwarded to the converter to start the conversion of the requested channel. request control request source 2 timer unit(s) (4-stage queue) ADC kernel request source 1 (16-ch scan) external request(s) request source arbiter analog part request source 0 (1-stage queue) ADC_request_handling Figure 16-3 Conversion Request Unit The functional characteristics of the request sources are adapted to the most common application requirements. In all request sources, a continuous operation or a single-shot operation can be selected. For continuous operation, the programmed sequence of conversions requests are continuously issued (once started), whereas in single-shot mode, each sequence of conversion requests has to be explicitly started. The trigger for a conversion request or a sequence can be handled under SW control or can be User's Manual ADC, UM_V0.1D6 16-7 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter synchronized to ADC-external events, such as timer signals or port pins. For each request source, the user can select an input signal (from 4 possible signals REQTRx[D:A]) as trigger input REQTRx and an input signal (from 4 possible signals REQGTx[D:A]) as gating input REQGTx. * Request source 0 (1-stage sequential source) can issue a conversion request for a single input channel. The channel number can directly be programmed. This mechanism could be used for SW-controlled conversion requests or HWtriggered conversions of a single input channel. If programmed with a high priority, it can interrupt the sequences of the other request sources to inject a single conversion. Request source 1 (16-channel scan source) can issue conversion requests for a sequence of up to 16 input channels. It can be programmed which channel takes part in this sequence. The sequence always starts with the highest enabled channel number and continues towards lower channel numbers (order defined by the channel number, each channel can be converted only once per sequence). This mechanism could be used to scan input channels permanently or on a regular time base. For example, if programmed with a low priority, some input channels can be scanned in a background task to update information that is not time-critical. Request source 2 (4-stage sequential source) can issue a conversion request for a sequence of up to 4 input channels. The channel numbers can be freely programmed, especially multiple conversions of the same channel within the sequence are supported. This mechanism could be used to support application-specific conversion sequences that can not be covered by the scanning mechanism of request source 1. Especially for timing-critical sequences containing multiple conversions of the same channel, request source 2 should be used. For example, if programmed with a medium priority, some input channels can be converted when a specified event occurs (e.g. synchronized to a PWM) while the scan of other input channels of the background task (handled by request source 1) is interrupted. * * User's Manual ADC, UM_V0.1D6 16-8 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.1.6 * Conversion Result Unit The conversion result unit comprises: A set of 8 result registers for storing the conversion results. A pointer mechanism for each analog input channel distributes the conversion results to the result registers. Especially for auto-scan applications, this feature simplifies PEC use (only one PEC channel needed to transfer a complete auto-scan sequence into the device memory). The result registers provide valid flags to indicate if new data has been stored since it has been read out (new data indication). A result FIFO mechanism for conversion results handling with a "relaxed" CPU timing. Result registers not directly used as target for a conversion result can be concatenated to form a result FIFO. This structure allows to store a sequence of conversion results before the CPU has to interact. A digital anti-aliasing or data reduction filter, accumulating a programmable number of conversion results before generating a result event interrupt. This feature can be used to avoid CPU intervention on each conversion result if a certain number of conversion results are added before further treatment, especially for fast conversions sequences and averaging of results. A wait-for-read mechanism can be enabled independently for each result register to delay conversions targeting a result register that has not yet been read out. A flexible interrupt generation based on result register events. A result register event occurs if a new valid data word becomes available in a result register and can be read out. Especially when using data reduction or digital anti-aliasing filtering, the result register event indicates that the final result is available. Result register read view compatible to the ADC result register on XC16x devices available at one address and a new read view for data reduction capability at another address. Debugger support for ADC result registers supporting read out of ADC conversion results without changing the result status (new data indication). * * * * * * * User's Manual ADC, UM_V0.1D6 16-9 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.1.7 Interrupt Structure Each ADC kernel provides 4 independent service request output signals (SR[3:0]) used for interrupt handling (SRx signals connected to interrupt control registers). The interrupt generation inside the ADC kernel is based on three different types of events: * Channel events: A channel event is detected if a conversion is finished and the conversion result is within a programmable value range. This type of event can be used to check if analog input values are inside or out of a nominal operating range, especially to reduce CPU load for background tasks. This allows the user to interrupt the CPU only if the specified conversion result range is met (or not met) instead of comparing each result by SW. Result events: A result event is detected if a new result is available in a result register and can be read out, e.g. to store the data in memory for further treatment by SW. This type of event can be used to trigger a read action by the CPU (or PEC). Especially when using data reduction or digital anti-aliasing filtering, not all finished conversion leads to a new result. Furthermore, when using a result FIFO, a result event decouples the CPU (PEC) read out from the channel events and tolerates a higher interrupt latency. The result register structure allows to use a single PEC channel for a complete auto-scan sequence by triggering the read out by a result event (if the conversion results of all channels taking part in the auto-scan sequence target the same result register, e.g. with FIFO mechanism or with a wait-for-read condition to avoid data loss). Request source events: A request source event is detected if a scan source has completely finished the requested conversion sequence. For a sequential source, the user can define where inside a conversion sequence a request source event is generated. This type of event can be used to inform the CPU that a conversion sequence has reached a defined state and SW can start the treatment of the related results in a block. * * Each ADC event is indicated by a dedicated flag that can be cleared by SW. An interrupt can be generated (if enabled) for each event, independently from the status of the corresponding event indication flag. This structure ensures efficient PEC handling of ADC events (the ADC event can generate an interrupt without the need to clear the indication flag). A node pointer mechanism allows the user to group interrupts events by selecting which service request output signals SRx becomes activated by which event. Each ADC event can be individually directed to one of the service request output signals to adapt easily to application needs. Note: A conversion can lead to three interrupts, one of each type. In this case, the ADC module first triggers the request source event interrupt, then the channel event interrupt, followed by the result event interrupt (all within a few fADC clock cycles). User's Manual ADC, UM_V0.1D6 16-10 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.1.8 Electrical Models Each conversion of an analog input voltage into a digital value consists of two consecutive phases. During the sample phase, the input voltage is sampled and prepared for the following conversion phase. A simplified model for the sample phase describes the input signal path, whereas a second simplified model for the conversion phase is related to the reference voltage handling. 16.1.8.1 Input Signal Path The ADC kernel in the XC2000 is based on one switched capacitor field for measurement with a total capacity represented by CAIN and a small static capacitor at each input pin. During the sample phase, the capacitor field CAIN is connected to one of the analog input CHx via an input multiplexer. The multiplexer is modeled by ideal switches and series resistors RAIN. Only the switch to the selected analog input is closed during the sample phase. During the conversion phase or while no conversion is running (ADC is idle), all switches are open. The voltage at the analog input channel CHx is represented by VAINx. CH15 ... ADC kernel R AIN R EXT CHx CH0 ... VS C EXT VAINx VAGND C AIN VC ADC_signal_path_model Figure 16-4 Signal Path Model A simplified model for the analog input signal path is given in Figure 16-4. An analog voltage source (value VS) with an internal impedance of REXT delivers the analog input that should be converted. During the sample phase the corresponding switch is closed and the capacitor field CAIN is charged. Due to the low-pass behavior of the resulting RC combination, the voltage VC to be actually converted does not immediately follow VS. The value REXT of the analog voltage source and the desired precision of the conversion strongly define the required length of the sample phase. To reduce the influence of RREXT and to filter input noise, it is recommended to introduce User's Manual ADC, UM_V0.1D6 16-11 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter a fast external blocking capacitor CEXT at the analog input pin of the ADC. Like this, mainly CEXT delivers the charge during the sample phase. This structure allows a significantly shorter sample phase than without a blocking capacitor, because the lowpass time constant defining the sample time is mainly given by the values of RAIN and CAIN. Additionally, the capacitor CAIN is automatically precharged to a voltage of approximately the half of the standard reference voltage VAREF to minimize the average difference between VAINx and VC at the beginning of a sample phase. Due to varying parameters and parasitic effects, the precharge voltage of CAIN is typically smaller than VAREF / 2. On the other hand, the charge redistribution between CEXT and CAIN leads to a voltage change of VAINx during the sample phase. In order to keep this voltage change lower than 1 LSBn, it is recommended to use an external blocking capacitor CEXT in the range of at least 2n x CAIN. The resulting low-pass filter of REXT and CEXT should be dimensioned in a way to allow VAINx to follow VS between two sample phases of the same analog input channel. Please note that, especially at high temperatures, the analog input structure of an ADC can lead to a leakage current and introduces an error due to a voltage drop over REXT. The ADC input leakage current increases if the input voltage level is close to the analog supply ground VSS or to the analog power supply VDDPA. It is recommended to use an operating range for the input voltage between approximately 3% and 97% of VDDPA to reduce input leakage values. Furthermore, the leakage is influenced by an overload condition at adjacent analog inputs. During an overload condition, an input voltage exceeding the supply range is applied at an input and the built-in protection circuit limits the resulting input voltage. This leads to an overload current through the protection circuit that is translated (by a coupling factor) into an additional leakage at adjacent inputs. 16.1.8.2 Reference Path During the conversion phase, parts of the capacitor field CAIN are switched to a reference input or to VAGND. The ADC kernel supports two possible reference inputs, VAREF as standard reference and CH0 as alternative reference. The reference selection between both possibilities is handled individually for each analog input channel. For example, this structure allows conversions of 5 V and 3.3 V based analog input signals with the same ADC kernel. A high accuracy of the conversion results requires a stable and noise-free reference voltage and analog supply voltages during the conversion phase. Instable voltages or noise on the supply or reference inputs lead to a reduced conversion accuracy. Please note that noise can also be introduced into the ADC module by other modules, e.g. by switching of neighboring pins. It is strongly recommended to carefully decouple analog from digital signal domains. Due to the switching of parts of CAIN, the ADC requires a dynamic current at the selected reference input. Thus, the impedance RAREF of the reference voltage source VR has to User's Manual ADC, UM_V0.1D6 16-12 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter be low enough to supply the reference current during the conversion phase. An external blocking capacitor CAREF should be used to supply the peak currents and to minimize the current delivered by the reference source. Due to the charge redistribution between CAREF and parts of CAIN, the voltage VAREF decreases during the conversion phase. In order to limit the error introduced by this effect to 1/2 LSBn, the external blocking capacitor CAREF for the reference input should be at least 2n x CAIN. The reference current IAREF introduces a voltage drop at RAREF that should not be neglected for the calculation of the overall accuracy. The average reference current during a conversion depends on the reference voltage level and the time tCONV between two conversion starts. IAREF = CAIN x VAREF / tCONV CH0 R AREF IAREF VR C AREF VAREF VAGND VAREF ADC kernel R AIN C AIN VC ADC_ref_path_model Figure 16-5 Reference Path Model User's Manual ADC, UM_V0.1D6 16-13 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.1.9 Transfer Characteristics and Error Definitions The ideal transfer characteristic of the ADC translates a continuous analog input voltage into a discrete digital value out of a result range of 2n steps for n bit resolution over a measurement range between 0 and a reference voltage. Each digital value in the available result range (from 0 to 2n-1) represents an input voltage range that is defined by the reference voltage divided by 2n. This range (called quantization step) represents the smallest granularity (called LSBn) that can be handled by the ADC. Due to the discrete character of the digital result, each ADC conversion result has a systeminherent quantization uncertainty of 0.5 LSBn. According to the ideal transfer characteristics, the first digital transition (between the digital values 0 and 1) takes place when the analog input reaches 0.5 LSBn. An analog input voltage above the reference voltage leads to a saturation of the digital result at 2n-1. Deviations of the conversion result from the ideal transfer characteristics can appear: * An offset error is the deviation from the ideal transfer characteristics for an input voltage close to 0. It describes the difference between 0.5 LSBn and the input voltage where the first digital transition (between the values of 0 and 1) occurs. A gain error is the deviation from the ideal transfer characteristics for an input voltage close to the reference voltage. It describes the difference between the reference voltage and the input voltage where the last digital transition (between the values of 2n-2 and 2n-1) occurs. A differential non-linearity error (DNL) describes the variations in the analog input voltage between two adjacent digital conversion results, over the full measurement range. If each step between the digital conversion results x and x+1 is exactly 1 LSBn, the DNL value is zero. If the DNL value is lower than 1 LSBn, the possibility of missing codes is excluded. A missing code occurs if not all values of the possible conversion result range can be reached. An integral non-linearity error (INL) describes the maximum difference between the transfer characteristics between the first and the last point of the measurement range and the real transfer characteristics (without quantization uncertainty, offset and gain errors). The total unadjusted error (TUE) describes the maximum deviation between a real conversion result and the ideal transfer characteristics over a given measurement range. Since some of these errors noted above can compensate each other, the TUE value generally is much less than the sum of the individual errors. The TUE also covers production process variations and internal noise effects (if switching noise is generated by the system, this generally leads to an increased TUE value). * * * * User's Manual ADC, UM_V0.1D6 16-14 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2 Operating the ADC This section describes the kernel functions and how to operate the kernel. It provides the functional description and the associated register descriptions. * * * * * * * * * * * * * * * * * * Register overview (see Section 16.2.1) Enabling the ADC module for configuration of the behavior for the different device operating modes (see mode control description in Section 16.2.2). Enabling the converter for operation or selecting the desired power saving mode (see Section 16.2.3) Selecting the appropriate frequency for the converter and for the request source arbiter (see Section 16.2.4). General ADC registers (see Section 16.2.5) Configuring the request source arbiter (see Section 16.2.6) Arbiter registers (see Section 16.2.7) Scan request source handling (see Section 16.2.8) Scan request source registers (see Section 16.2.9) Sequential request source handling (see Section 16.2.10) Sequential request source registers (see Section 16.2.11) Configuring the channel-related functions (see Section 16.2.12) Channel-related registers (see Section 16.2.13) Conversion result handling (see Section 16.2.14) Conversion request handling (see Section 16.2.15) External multiplexer control (see Section 16.2.16) Synchronization for parallel conversions (see Section 16.2.17) Additional feature registers (see Section 16.2.18) General module, kernel and arbiter operation: Request source operation: Channel and result register operation: Additional features: User's Manual ADC, UM_V0.1D6 16-15 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2.1 Register Overview Table 16-2 shows all registers required for programming the ADC module. It summarizes the ADC kernel registers and defines their relative addresses and the reset values. The relative addresses have to be added to the base addresses for the ADC kernels (see Section 16.3.1) to obtain the absolute address for each register. The prefix "ADCx_" has to be added to the register names in this table for each ADC kernel to distinguish registers of the different kernels. In this naming convention, x indicates the kernel number. All ADC registers (including KSCFG.NOMCFG and KSCFG.COMCFG) are reset by a class 3 reset, whereas bit field KSCFG.SUMCFG is reset by a class 1 reset. Note: Register bits marked "w" always deliver 0 when read. Table 16-2 Short Name ADC Module Register Summary Description Rel. 1) See Addr. Page General Registers PISEL KSCFG2) GLOBCTR GLOBSTR Port Input Select Register Kernel State Configuration Register Global Control Register Global Status Register 04H 0CH 10H 12H Page 16-31 Page 16-24 Page 16-26 Page 16-28 Arbiter Registers ASENR RSPR0 Arbitration Slot Enable Register Request Source Priority Register 0 18H 14H Page 16-37 Page 16-38 Channel-Related Registers CHCTR0-15 INPCR0 Channel Control Register 0-15 Input Class Register 0 20H3EH C0H Page 16-68 Page 16-70 User's Manual ADC, UM_V0.1D6 16-16 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Table 16-2 Short Name INPCR1 LCBR0 LCBR1 LCBR2 LCBR3 CHINFR CHINCR CHINPR0 CHINPR4 CHINPR8 CHINPR12 ALR0 ADC Module Register Summary (cont'd) Description Input Class Register 1 Limit Checking Boundary Register 0 Limit Checking Boundary Register 1 Limit Checking Boundary Register 2 Limit Checking Boundary Register 3 Channel Event Indication Flag Register Channel Event Indication Clear Register Channel Interrupt Node Pointer Register 0 Channel Interrupt Node Pointer Register 4 Channel Interrupt Node Pointer Register 8 Channel Interrupt Node Pointer Register 12 Alias Register 0 Rel. 1) See Addr. Page C2H 84H 86H 88H 8AH 90H 92H 98H 9AH 9CH 9EH 1CH Page 16-70 Page 16-71 Page 16-71 Page 16-71 Page 16-71 Page 16-72 Page 16-73 Page 16-74 Page 16-74 Page 16-75 Page 16-76 Page 16-77 Analog to Digital Converter Result Registers RESR0-7 RESRA0-7 RESRV0-7 RESRAV0-7 Result Register 0-7, normal view Result Register 0-7, view A Result Register 0-7, view V Result Register 0-7, view AV 40H4EH 50H5EH 60H6EH 70H7EH Page 16-86 Page 16-87 Page 16-86 Page 16-87 User's Manual ADC, UM_V0.1D6 16-17 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Table 16-2 Short Name VFR RSSR RCR0-7 EVINFR EVINCR EVINPR0 EVINPR8 EVINPR12 ADC Module Register Summary (cont'd) Description Valid Flag Register Result Status Shadow Register Result Control Register 0-7 Event Indication Flag Register Event Indication Clear Register Event Interrupt Node Pointer Register 0 Event Interrupt Node Pointer Register 8 Event Interrupt Node Pointer Reg. 12 Rel. 1) See Addr. Page 80H 82H B0HBEH A0H A2H A8H ACH AEH Page 16-89 Page 16-88 Page 16-90 Page 16-92 Page 16-93 Page 16-94 Page 16-94 Page 16-95 Analog to Digital Converter Request Source 0 Registers QMR0 QSR0 Q0R0 QBUR0 QINR0 Queue 0 Mode Register Queue 0 Status Register Queue 0 Register 0 Queue 0 Backup Register Queue 0 Input Register E0H E2H E4H Page 16-52 Page 16-55 Page 16-57 E6H Page 16-59 shared Page 16-61 Request Source 1 Registers CRCR1 CRPR1 Conversion Request 1 Control Register Conversion Request 1 Pending Register E8H EAH Page 16-43 Page 16-44 User's Manual ADC, UM_V0.1D6 16-18 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Table 16-2 Short Name CRMR1 ADC Module Register Summary (cont'd) Description Conversion Request 1 Mode Register Rel. 1) See Addr. Page ECH Page 16-45 Analog to Digital Converter Request Source 2 Registers QMR2 QSR2 Q0R2 QBUR2 QINR2 Queue 2 Mode Register Queue 2 Status Register Queue 2 Register 0 Queue 2 Backup Register Queue 2 Input Register F0H F2H F4H Page 16-52 Page 16-55 Page 16-57 F6H Page 16-59 shared Page 16-61 Additional Function Register EMCTR EMENR SYNCTR 1) 2) External Multiplexer Control Register External Multiplexer Enable Register Synchronization Control Register D0H D6H 1AH Page 16-102 Page 16-103 Page 16-104 Short 8-bit addresses are not available for kernel registers of this module. Register KSCFG is available only in the address range of ADC0, named ADC0_KSCFG. Note: The addresses 00H, 02H, 06H, 08H, 16H, C4H, C6H, 8CH, 8EH, A4H, A6H, and AAH are reserved for future use. User's Manual ADC, UM_V0.1D6 16-19 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2.2 Mode Control The mode control concept for system control tasks, such as power saving, or suspend request for debugging, allows to program the module behavior under different device operating conditions. The behavior of the ADC kernels can be programmed for each of the device operating modes, that are requested by the global state control part of the SCU. It is advantageous that the ADC kernels of an ADC module show an identical behavior regarding the device operating modes (e.g. to avoid that a non-suspended kernel waits for a suspended kernel to start a synchronized conversion). Therefore, the ADC module has a common associated register ADC0_KSCFG defining the behavior of all kernels of the module in the following device operating modes: * Normal operation: This operating mode is the default operating mode when neither a suspend request nor a clock-off request are pending. The module clock is not switched off and the ADC registers can be read or written. The kernel behavior is defined by KSCFG.NOMCFG. Suspend mode: This operating mode is requested when a suspend request (issued by a debugger) is pending in the device. The module clock is not switched off and the ADC registers can be read or written. The kernel behavior is defined by KSCFG.SUMCFG. Clock-off mode: This operating mode is requested for power saving purposes. The module clock is switched off automatically when all kernels of the ADC module reached their specified state in a stop mode. In this case, ADC registers can not be accessed. The kernel behavior is defined by KSCFG.COMCFG. A current conversion of an analog value: If the request control unit has found a pending conversion request, the conversion can be started. This start has to be enabled by the mode control. If the current kernel mode allows the conversion start (run modes 0 and 1), it will be executed. If the kernel mode does not allow a start (stop modes 0 and 1), the conversion is not started. The start request is not cancelled, but frozen. A "frozen" conversion is started as programmed if the kernel mode is changed to a run mode again. An arbiter round: The start of a new arbiter round has to be enabled by the kernel modes. In stop mode 1, a new arbiter round will not start. * * For the ADC module, the following internal actions can be influenced by mode control: * * The behavior of the ADC kernels can be programmed for each of the device operating modes (normal operation, suspend mode, clock-off mode). Therefore, the ADC kernels support four kernel modes, as shown in Table 16-3. User's Manual ADC, UM_V0.1D6 16-20 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Table 16-3 Kernel Mode run mode 0 run mode 1 stop mode 0 ADC Kernel Behavior Kernel Behavior kernel operation as specified, no impact on data transfer (same behavior for run mode 0 and run mode 1) Code 00B 01B Analog to Digital Converter A currently running AD conversion is completely finished and 10B the result is treated. Pending conversion request to start a new conversion are not taken into account (but not deleted). They start conversions after entering a run mode as programmed. The arbiter continues as programmed. Like stop mode 0, but the arbiter is stopped after it has finished 11B its arbitration round. stop mode 1 Generally, bit field KSCFG.NOMCFG should be configured for run mode 0 as default setting for standard operation. If the ADC kernels should not react to a suspend request (and to continue operation as in normal mode), bit field KSCFG.SUMCFG has to be configured with the same value as KSCFG.NOMCFG. If the ADC kernels should show a different behavior and stop operation when a specific stop condition is reached, the code for stop mode 0 or stop mode 1 has to be written to KSCFG.SUMCFG. A similar mechanism applies for the clock-off mode with the possibility to program the desired behavior by bit field KSCFG.COMCFG. Note: The stop mode selection strongly depends on the application needs and it is very unlikely that different stop modes are required in parallel in the same application. As a result, only one stop mode type (either 0 or 1) should be used in the bit fields in register KSCFG. Do not mix stop mode 0 and stop mode 1 and avoid transitions from stop mode 0 to stop mode 1 (or vice versa) for the ADC module. If the module clock is disabled by KSCFG.MODEN = 0 or in clock-off mode when the stop condition is reached (in stop mode 0 or 1), the module can not be accessed by read or write operations (except register KSCFG that can always be accessed). As a consequence, it can not be configured. Please note that bit KSCFG.MODEN should only be set by SW while all configuration fields are configured for run mode 0. User's Manual ADC, UM_V0.1D6 16-21 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2.3 Module Activation and Power Saving Modes The converter of the ADC supports specific power down modes allowing an automatic reduction of the power consumption between two conversions. The following modes are determined by bit field GLOBSTR.ANON: * ANON = 00B: Converter switched off (default after reset) The complete converter is switched off and held in its reset state, conversions are not possible. To start a conversion, ANON has to be programmed to the desired mode. A maximum wake-up time of about 10 s has to be respected before starting a conversion. Furthermore, digital logic blocks are set to their initial state. ANON = 01B: Slow stand-by mode The converter enters a power reduction mode after each conversion. It switches automatically to normal operation if a conversion is requested. A maximum wake-up time of about 10 s has to be added to the sample time. This leads to the lowest power consumption for the ADC supply with wake-up capability. ANON = 10B: Fast stand-by mode The converter enters a power reduction mode with less reduction than in slow standby mode after each conversion. It switches automatically to normal operation if a conversion is requested. A maximum wake-up time of about 3 s has to be added to the sample time. This leads to a reduced power consumption for the ADC supply compared to normal operation. ANON = 11B: Normal operation Conversions are always possible with the desired sample time. The converter stays active permanently. * * * User's Manual ADC, UM_V0.1D6 16-22 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2.4 Clocking Scheme The different parts of an ADC kernel are driven by clock signals that are based on the clock fADC of the bus that is used to access the ADC module. * The analog clock fADCI is used as internal clock for the converter and defines the conversion length and the sample time. It can be adjusted by programming bit field GLOBCTR.DIVA. The digital clock fADCD is used for the arbiter and defines the duration of an arbiter round. It can be adjusted by programming bit field GLOBCTR.DIVD. All other digital structures (such as interrupts, etc.) are directly driven by the module clock fADC. * * clock generation unit (in SCU) ADC kernel module clock fADC divider for fADCI analog clock fADCI divider for fADCD digital clock fADCD interrupts, etc. converter arbiter ADC_clocking Figure 16-6 Clocking Scheme Note: If the clock generation for the converter of the ADC falls below a minimum value or is stopped during a running conversion, the conversion result can be corrupted. For correct ADC results, the frequency of fADCI must not exceed the range indicated in the electrical characteristics chapter. User's Manual ADC, UM_V0.1D6 16-23 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2.5 General ADC Registers 16.2.5.1 Kernel State Configuration Register The kernel state configuration register KSCFG allows the selection of the desired kernel modes for the different device operating modes. Bit fields KSCFG.NOMCFG and KSCFG.COMCFG are reset by a class 3 reset. Bit field KSCFG.SUMCFG is reset by a class 1 reset. This register is a common register for all ADC kernels and can be accessed in the address range of ADC0. Note: The coding of the bit fields NOMCFG, SUMCFG and COMCFG is described in Table 16-3. ADC0_KSCFG Kernel State Configuration Register XSFR(0CH) 15 BP COM w 14 0 r 13 12 11 10 0 r 9 8 7 6 0 r 5 4 Reset Value: 0000H 3 0 r 2 1 0 BP MOD MOD EN EN w rw BP COMCFG SUM rw w BP SUMCFG NOM rw w NOMCFG rw Field MODEN Bits 0 Type Description rw Module Enable This bit enables the module kernel clock and the module functionality. 0B The module is switched off immediately (without respecting a stop condition). It does not react on mode control actions and the module clock is switched off. The module does not react on read accesses and ignores write accesses (except to KSCFG). 1B The module is switched on and can operate. After writing 1 to MODEN, it is recommended to read register KSCFG to avoid pipeline effects in the control block before accessing other ADC registers. User's Manual ADC, UM_V0.1D6 16-24 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field BPMODEN Bits 1 Type Description w Bit Protection for MODEN This bit enables the write access to the bit MODEN. It always reads 0. 0B MODEN is not changed. 1B MODEN is updated with the written value. Normal Operation Mode Configuration This bit field defines the kernel mode applied in normal operation mode. 00B Run mode 0 is selected. 01B Run mode 1 is selected. 10B Stop mode 0 is selected. 11B Stop mode 1 is selected. Bit Protection for NOMCFG This bit enables the write access to the bit field NOMCFG. It always reads 0. 0B NOMCFG is not changed. 1B NOMCFG is updated with the written value. Suspend Mode Configuration This bit field defines the kernel mode applied in suspend mode. Coding like NOMCFG. Bit Protection for SUMCFG This bit enables the write access to the bit field SUMCFG. It always reads 0. SUMCFG is not changed. 0B 1B SUMCFG is updated with the written value. Clock Off Mode Configuration This bit field defines the kernel mode applied in clock-off mode. Coding like NOMCFG. Bit Protection for COMCFG This bit enables the write access to the bit field COMCFG. It always reads 0. 0B COMCFG is not changed. 1B COMCFG is updated with the written value. Reserved returns 0 if read; should be written with 0; Analog to Digital Converter NOMCFG [5:4] rw BPNOM 7 w SUMCFG [9:8] rw BPSUM 11 w COMCFG [13:12] rw BPCOM 15 w 0 [3:2], 6, 10, 14 r Note: The bit protection bits BPxxx allow partly modification of the configuration bits with a single write operation (without the need of a read-modify-write mechanism handled by the CPU). User's Manual ADC, UM_V0.1D6 16-25 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2.5.2 Global Control Register The global control register contains bits to control the timing of the arbiter and the general enable function for the converter. GLOBCTR Global Control Register 15 ARB M rw 14 13 0 rw 12 11 10 9 XSFR(10H) 8 7 6 5 4 Reset Value: 00FFH 3 2 1 0 ARBRND rw ANON rw DIVD rw DIVA rw Field DIVA Bits [5:0] Type Description rw Divider Factor for Analog Internal Clock This bit field defines the number of fADC clock cycles to generate the fADCI clock for the converter (used as internal base for the conversions and the sample time calculation). 00H fADCI = fADC 01H fADCI = fADC / 2 02H fADCI = fADC / 3 ... 3FH fADCI = fADC / 64 Divider Factor for Digital Arbiter Clock This bit field defines the number of fADC clock cycles within each arbitration slot (each arbitration slots last one periods of fADCD). It is recommended to use the default setting 00B to obtain the minimum arbiter reaction time. 00B fADCD = fADC 01B fADCD = fADC / 2 10B fADCD = fADC / 3 11B fADCD = fADC / 4 Analog Part Switched On This bit field defines the setting of bit field GLOBSTR.ANON (bit description see there) if this kernel is the synchronization master or without synchronization feature. For a synchronization slave, this bit field is not taken into account. DIVD [7:6] rw ANON [9:8] rw User's Manual ADC, UM_V0.1D6 16-26 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field ARBRND Bits [11:10] Type Description rw Arbitration Round Length This bit field defines the number of arbitration slots per arbitration round (arbitration round length = tARB). 00B An arbitration round contains 4 arbitration slots (tARB = 4 / fADCD). 01B An arbitration round contains 8 arbitration slots (tARB = 8 / fADCD). 10B An arbitration round contains 16 arbitration slots (tARB = 16 / fADCD). 11B An arbitration round contains 20 arbitration slots (tARB = 20 / fADCD). Reserved for Future Use This bit field is reserved for future use and has to be written with 000B. Arbitration Mode This bit field defines whether the arbiter runs permanently or only while at least one conversion request is pending. The arbiter runs permanently. This setting has 0B to be chosen in a synchronization slave (see Section 16.2.17). 1B The arbiter only runs if at least one conversion request of an enabled request source is pending. This setting leads to a reproducible latency from an incoming request to the conversion start if the converter is idle. Synchronized conversions are not supported. Analog to Digital Converter 0 [14:12] rw ARBM 15 rw User's Manual ADC, UM_V0.1D6 16-27 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2.5.3 Global Status Register The status control register contains bits indicating the current status of a conversion. GLOBSTR Global Status Register 15 0 r 14 13 12 CSRC rh 11 10 SYN RUN rh 9 XSFR(12H) 8 7 6 5 CHNR rh 4 Reset Value: 0000H 3 2 0 r 1 0 ANON rh SAM BU PLE SY rh rh Field BUSY Bits 0 Type Description rh Analog Part Busy This bit indicates that a conversion is currently running. The converter is idle. 0B 1B A conversion is currently running. Sample Phase This bit indicates that an analog input signal is currently sampled. The converter is not in the sampling phase. 0B 1B The converter is in the sampling phase. Channel Number This bit field indicates which analog input channel is currently converted. This information is updated when a new conversion is started. SAMPLE 1 rh CHNR [7:3] rh User's Manual ADC, UM_V0.1D6 16-28 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field ANON Bits [9:8] Type Description rh Analog Part Switched On This bit field defines the operation mode of the converter. It monitors either bit field GLOBCTR.ANON of the same ADC kernel (in master mode or without synchronization feature) or bit field GLOBCTR.ANON of the ADC kernel selected as synchronization master for this kernel (in slave mode). This ensures that all kernels of a synchronization group can be controlled with a single write operation to bit field GLOBCTR of the synchronization master. 00B The converter is switched off and conversions are not possible. The arbiter finishes its current arbitration round (if running) and then remains in the idle state. 01B The converter of the ADC module is switched on and conversions are possible. The automatic power-down capability of the converter is enabled, leading to the lowest power consumption of the ADC supply with wake-up capability, but a longer wake-up time before each conversion. 10B The converter of the ADC module is switched on and conversions are possible. The automatic power-down capability of the converter is enabled, leading to a reduced power consumption of the ADC supply, but a shorter wake-up time before each conversion. 11B The converter of the ADC module is switched on and conversions are possible. The automatic power-down capability of the converter is disabled leading to the nominal power consumption of the ADC supply. Analog to Digital Converter User's Manual ADC, UM_V0.1D6 16-29 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field SYNRUN Bits 10 Type Description rh Synchronous Conversion Running This bit indicates that a synchronized (= parallel) conversion is currently running. 0B There is no synchronized conversion running (either there is no conversion currently running or a synchronized conversion has not been requested). A running conversion can be cancelled and repeated in case of a new incoming conversion request with higher priority. 1B A synchronized conversion is running. This conversion can not be cancelled while running. Higher priority requests can trigger conversions only after the end of a synchronized conversion. Currently Converted Request Source This bit field indicates the arbitration slot number of the current conversion (if BUSY = 1, a conversion is still running) or of the last conversion (if BUSY = 0, no conversion is running). This bit field is updated with each conversion start. 000B The channel requested by the request source of arbitration slot 0 is (has been) converted. 001B The channel requested by the request source of arbitration slot 1 is (has been) converted. 010B The channel requested by the request source of arbitration slot 2 is (has been) converted. other combinations are reserved Reserved returns 0 if read; should be written with 0; Analog to Digital Converter CSRC [13:11] rh 0 2, [15:14] r User's Manual ADC, UM_V0.1D6 16-30 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2.5.4 Input Select Registers Register PISEL contains bit fields selecting the input signal for the trigger and gating inputs of the request sources. The connections depending on the device implementation, please refer to the implementation chapter for details. Note: For signals connected to inputs with a synchronization stage, a synchronization delay of two fADC clock cycles has to be taken into account. PISEL Port Input Select Register 15 14 0 r 13 12 0 rw 11 10 9 XSFR(04H) 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 REQTR2 rw REQGT2 rw REQTR1 rw REQGT1 rw REQTR0 rw REQGT0 rw Field REQGT0 Bits [1:0] Type Description rw Input Select for REQGT0 of Source 0 This bit field defines the input signal used for the module input REQGT0 of the request source 0. 00B The input signal REQGT0A is selected. 01B The input signal REQGT0B is selected. 10B The input signal REQGT0C is selected. 11B The input signal REQGT0D is selected. Input Select for REQTR0 of Source 0 This bit field defines the input signal used for the module input REQTR0 of the request source 0. 00B The input signal REQTR0A is selected. 01B The input signal REQTR0B is selected. 10B The input signal REQTR0C is selected. 11B The input signal REQTR0D is selected. Input Select for REQGT1 of Source 1 This bit field defines the input signal used for the module input REQGT1 of the request source 1. 00B The input signal REQGT1A is selected. 01B The input signal REQGT1B is selected. 10B The input signal REQGT1C is selected. 11B The input signal REQGT1D is selected. REQTR0 [3:2] rw REQGT1 [5:4] rw User's Manual ADC, UM_V0.1D6 16-31 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field REQTR1 Bits [7:6] Type Description rw Input Select for REQTR1 of Source 1 This bit field defines the input signal used for the module input REQTR1 of the request source 1. 00B The input signal REQTR1A is selected. 01B The input signal REQTR1B is selected. 10B The input signal REQTR1C is selected. 11B The input signal REQTR1D is selected. Input Select for REQGT2 of Source 2 This bit field defines the input signal used for the module input REQGT2 of the request source 2. 00B The input signal REQGT2A is selected. 01B The input signal REQGT2B is selected. 10B The input signal REQGT2C is selected. 11B The input signal REQGT2D is selected. Input Select for REQTR2 of Source 2 This bit field defines the input signal used for the module input REQTR2 of the request source 2. 00B The input signal REQTR2A is selected. 01B The input signal REQTR2B is selected. 10B The input signal REQTR2C is selected. 11B The input signal REQTR2D is selected. Reserved for Future Extension returns 0 if read; should be written with 0; Reserved returns 0 if read; should be written with 0; Analog to Digital Converter REQGT2 [9:8] rw REQTR2 [11:10] rw 0 0 12 [15:13] rw r User's Manual ADC, UM_V0.1D6 16-32 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2.6 Request Source Arbiter The request source arbiter evaluates which analog input channel has to be converted. Therefore, it regularly polls the request sources one after the other for pending conversion requests. The polling sequence is based on time slots with programmable length, called arbitration slots. If a request source is disabled or if no request source is available for an arbitration slot, the slot is considered as being empty and has no influence on the evaluation of the arbitration winner. After reset, all request sources are disabled and have to be enabled by bits in register ASENR to take part in the arbitration process. The number of arbitration slots forming an arbitration round can be programmed to obtain a similar arbiter timing for different devices, even if the number of available request sources differs from one device to another. At the end of each arbitration round, the arbiter has determined the request source with the highest priority and a pending conversion request. This arbitration result is stored as arbitration winner for further actions. If a conversion is started in an arbitration round, this arbitration round does not deliver an arbitration winner. In the XC2000, the following request sources are available: * * Request source 0 in arbitration slot 0: 1-stage sequential source This request source can issue a conversion request for a single input channel. Request source 1 in arbitration slot 1: 16-channel scan source This request source can issue a conversion request sequence of up to 16 input channels in a defined order. Request source 2 in arbitration slot 2: 4-stage sequential source This request source can issue a conversion request sequence of up to 4 input channels in a freely programmable order. Last arbitration slot of the arbitration round: Synchronization source In this slot, the arbiter checks for a synchronized request from another ADC kernel and does not evaluate any internal request source. A request for a synchronized conversion is always handled with the highest priority in a synchronization slave kernel (pending requests from other sources are not considered). * * arbitration round arbitration winner found conversion can be started ADC_arbiter_round arbitration slot 0 polling of request source 0 arbitration slot 1 polling of request source 1 arbitration slot 2 polling of request source 2 arbitration slot 3 check for synchronized start request Figure 16-7 Arbitration Round User's Manual ADC, UM_V0.1D6 16-33 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter The period tARB of an arbitration round is given by: tARB = N x (GLOBCTR.DIVD + 1) / fADC with N being 4, 8, 16, or 20 as defined by GLOBCTR.ARBRND The period of the arbitration round introduces a timing granularity to detect an incoming conversion request signal and the earliest point to start the related conversion. This granularity can introduce a jitter of maximum one arbitration round. The jitter can be reduced by minimizing the period of an arbitration round (numbers of arbitration slots and their length). To achieve a reproducible reaction time (constant delay without jitter) between the trigger event of a conversion request (e.g. by a timer unit or due to an external event) and the start of the related conversion, mainly the following two options exist. For both options, the converter has to be idle and other conversion requests must not be pending for at least one arbiter round before the trigger event occurs: * If bit GLOBCTR.ARBM = 0, the arbiter runs permanently. In this mode, synchronized conversions of more than one ADC kernel are possible. The trigger for the conversion triggers has to be generated synchronously to the arbiter timing. Incoming triggers should have exactly n-times the granularity of the arbiter (n = 1, 2, 3, ...). In order to allow some flexibility, the duration of an arbitration slot can be programmed in cycles of fADC. If bit GLOBCTR.ARBM = 1, the arbiter stops after an arbitration round when no conversion request have been found pending any more. The arbiter is started again if at least one enabled request source indicates a pending conversion request. The trigger of a conversion request does need not to be synchronous to the arbiter timing. In this mode, parallel conversions are not possible for synchronization slave kernels. * 16.2.6.1 Request Source Priority Each request source has an individually programmable priority to be able to adapt to different applications (see register RSPR0). The priorities define the order the request sources are handled by the arbiter if two or more request sources indicate pending conversion requests at the same time. Starting with request source 0, the arbiter checks if an enabled request source has a pending request for a conversion. The arbitration winner is the request source with a pending conversion request and the highest priority that has been found first in an arbitration round. 16.2.6.2 Conversion Start Modes To start the requested conversion of the arbitration winner, the following aspects are automatically taken into consideration by the arbiter: * If the converter is currently idle (no conversion running), the conversion of the arbitration winner is started immediately. User's Manual ADC, UM_V0.1D6 16-34 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary * Analog to Digital Converter * * If a conversion is currently running, the arbitration winner is compared to the priority of the currently running conversion. In the case that the current conversion has the same or a higher priority, it is completed. Then, the conversion of the arbitration winner is started. If a conversion is currently running, the arbitration winner is compared to the priority of the currently running conversion. In the case that the current conversion has the lower priority and the arbiter winner has been programmed for wait-for-start mode, the currently running conversion is completed. Then, the conversion of the arbitration winner is started. This mode can be used if the timing requirement for the higher priority conversions allow a jitter (between t3 and t4 in Figure 16-8) in the range of a running conversion. If a conversion is currently running, the arbitration winner is compared to the priority of the currently running conversion. In the case that the current conversion has the lower priority and the arbiter winner has been programmed for cancel-inject-repeat mode, the current conversion is aborted immediately if a new request with a higher priority has been found, unless both requests target the same result register with wait-for-read active (see Section 16.2.14.2). The conversion of the arbitration winner is started after the abort action. The aborted conversion request is restored in the request source that has requested the aborted conversion. As a consequence, it takes part again in the next arbitration round. Please note that the abort mechanism can take between 1 and 3 fADCI cycles, depending on the state of the current conversion. This mode can be used if higher priority conversions only tolerate a small jitter (between t8 and t9 in Figure 16-8). t1 request channel B request channel A conversions t2 t3 t6 t8 A t4 B t5 t7 A t9 B t10 A t11 wait-for-start mode cancel-inject-repeat mode ADC_conv_starts Figure 16-8 Conversion Start Modes User's Manual ADC, UM_V0.1D6 16-35 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter The conversion start mode can be individually programmed for each request source by bits in register RSPR0 and is applied to all channels requested by the source. Figure 16-8 shows the influence of both conversion start modes on the conversion sequence if two request sources generate conversion requests. In this example, channel A is issued by a request source with a lower priority than the request source requesting the conversion of channel B. * * t1: The trigger event for channel A occurs and a conversion request is activated. t2: At the end of the arbitration round, channel A is determined as arbitration winner, the conversion of channel A is started. With the start of the conversion, the related conversion request is cleared. t3: The trigger event for channel B occurs and a conversion request is activated. In wait-for-read mode, the currently running conversion of channel A is finished normally. t4: After the conversion of channel A is finished, the conversion of channel B is started. With the start of the conversion, the related conversion request is cleared. t5: The conversion of channel B is finished. t6: The trigger event for channel A occurs and a conversion request is activated. t7: At the end of the arbitration round, channel A is determined as arbitration winner, the conversion of channel A is started. With the start of the conversion, the related conversion request is cleared. t8: The trigger event for channel B occurs and a conversion request is activated. t9: At the end of the arbitration round, channel B is determined as arbitration winner. In cancel-inject-repeat mode, the currently running conversion of channel A is aborted and the conversion of channel B is started. With the abort of the conversion, the related conversion request is set again. With the start of the conversion, the related conversion request is cleared. t10: The conversion of channel B is finished. In the meantime, the pending request for channel A has been identified as arbitration winner and the conversion of channel A is started. With the start of the conversion, the related conversion request is cleared. t11: The conversion of channel A is finished. * * * * * * * * * User's Manual ADC, UM_V0.1D6 16-36 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2.7 Arbiter Registers 16.2.7.1 Arbitration Slot Enable Register The arbitration slot enable register contains bits to enable/disable the conversion request treatment in the arbitration slots. ASENR Arbitration Slot Enable Register 15 14 13 12 11 10 9 0 r XSFR(18H) 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 AS AS AS EN2 EN1 EN0 rw rw rw Field ASENx (x = 0-2) Bits x Type Description rw Arbitration Slot x Enable Each bit enables an arbitration slot of the arbiter round. ASEN0 enables the arbitration slot 0, ASEN1 the slot 1, etc. If an arbitration slot is disabled, the arbitration slot is considered as being empty. A pending conversion request of a request source connected to this slot is not taken into account for arbitration. The request source bits are not modified by write actions to ASENR. The corresponding arbitration slot is disabled. 0B Conversions are not requested, even for the request source(s) with request bit(s) pending. To support ARBM = 1, the request source in arbitration slot x must not request any conversion while ASENx = 0. Conversion requests of the related request source should be cleared by SW before disabling a previously enabled arbitration slot. 1B The corresponding arbitration slot is enabled. Conversions are requested for the request source(s) with pending request bit(s). Reserved returns 0 if read; should be written with 0; 0 [15:3] r User's Manual ADC, UM_V0.1D6 16-37 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2.7.2 Request Source Priority Register The request source priority register contains bits to define the request source priority and the conversion start mode. The priority and conversion start mode settings of an enabled request source must not be changed by SW. If a request source is disabled, the setting can be changed by SW if a currently running conversion requested by this source is finished. RSPR0 Request Source Priority Register 0 XSFR(14H) 15 14 0 r 13 12 11 CSM 2 rw 10 0 r 9 8 7 CSM 1 rw 6 0 r 5 4 Reset Value: 0000H 3 CSM 0 rw 2 0 r 1 0 PRIO 2 rw PRIO 1 rw PRIO 0 rw Field PRIO0, PRIO1, PRIO2 Bits [1:0], [5:4], [9:8] Type Description rw Priority of Request Source x This bit field defines the priority of the conversion request source x, located in arbitration slot x. 00B Lowest priority is selected. ... 11B Highest priority is selected. Conversion Start Mode of Request Source x This bit defines the conversion start mode of the conversion request source x, located in arbitration slot x. 0B Wait-for-start mode is selected. 1B Cancel-inject-repeat mode is selected. Reserved returns 0 if read; should be written with 0; CSM0, CSM1, CSM2 3, 7, 11 rw 0 2, 6, 10, r [15:12] User's Manual ADC, UM_V0.1D6 16-38 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2.8 Scan Request Source Handling A scan request source can issue conversion requests for a sequence of up to 16 input channels. It can be programmed individually for each input channel if it takes part in the scan sequence. The scan sequence always starts with the highest enabled channel number and continues towards lower channel numbers (order defined by the channel number, each channel can be converted only once per sequence). trigger inputs REQTRx[D:A] REQTRx conversion request control load event trigger & gating unit gating inputs REQGTx[D:A] request source event REQGTx conversion requests pending request request handling scan request source x status request source arbiter ADC_scan_reqsr Figure 16-9 Scan Request Source 16.2.8.1 Overview A scan request source performs the: * Conversion request control: The conversion request control defines if an analog input channel takes part in the scan sequence (see bits in register CRCR1). The programmed register value is kept unchanged by an ongoing scan sequence. Conversion request pending: The pending conversion requests indicate if an input channel has to be converted in an ongoing scan sequence (see bits in register CRPR1). A conversion request can only be issued to the request source arbiter if at least one pending bit is set. With each conversion start that has been triggered by the scan request source, the corresponding pending bit is automatically cleared. The scan sequence is considered finished and a request source event is generated if the last conversion triggered by the scan source is finished and all pending bits have been cleared. Request handling: The request handling blocks interfaces with the request source arbiter. It requests conversion due to pending bits in the scan sequence and handles the conversion 16-39 V1.0, 2007-06 * * User's Manual ADC, UM_V0.1D6 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter * status information. If a conversion triggered by the scan request source is aborted due to a conversion request from another request source with a higher priority, the corresponding pending bit is automatically set. This mechanism ensures that an aborted conversion takes part in the next arbitration round and does not get lost. The control of the scan sequence is done based on bits in register CRMR1. Trigger and gating signal handling: The trigger and gating unit interfaces with signals and modules outside the ADC module that can request conversions. For example, a timer unit can issue a request signal to synchronize conversions to PWM events. A load event starts a scan sequence by modifying the request pending bits according to the request control bits. 16.2.8.2 Scan Sequence Operation To operate a scan request source, the following aspects should be taken into account: * * The bits in register CRCRx have to be programmed to define the channels participating in the scan sequence. If a trigger or gating function by external signals is desired, the gating and trigger inputs have to be defined by bit fields REQTRx and REQGTx in register PISEL (the value of x defines the number of the arbitration slot where the scan source is connected). The gating mechanism has to be defined by CRMRx.ENGT. The corresponding arbitration slot has to be enabled to accept conversion requests from the scan source (see register ASENR). The load event has to be defined by bits in CRMRx to start a scan sequence. If a load event occurs while CRMRx.LDM = 0, the content of CRCRx is copied to CRPRx (overwrite). This setting allows starting a new scan sequence and to "forget" remaining pending bits if a load event occurs while a scan sequence is running. If a load event occurs while CRMRx.LDM = 1, the content of CRCRx is bit-wisely logical OR-combined to CRPRx (no overwrite). This setting allows starting a new scan sequence without "forgetting" remaining pending bits if a load event occurs while a scan sequence is running. * * * * * To start a scan sequence, the following mechanisms are supported to generate a load event: * An external trigger signal can be selected to start a scan sequence controlled by HW by an external module or signal, e.g. a timer unit or an input pin. The trigger feature is enabled by CRMRx.ENTR = 1. The load event is generated if a rising edge is detected at the selected trigger input. A load event is generated under SW control by writing CRMRx.LDEV = 1. This mechanism starts a scan sequence without modifying the bits in register CRCRx. A data write action to CRCRx does not lead to a load event (first prepare the channel control, then start the sequence). * User's Manual ADC, UM_V0.1D6 16-40 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary * Analog to Digital Converter * If SW writes data to register CRPRx, the written data is stored in register CRCRx and a load event is generated automatically. This mechanism starts a scan sequence with the channels defined by the written data (the sequence is defined and started with a single data write action, e.g. under PEC control). A load event is generated each time a scan sequence has finished and the request source event occurs if bit CRMRx.SCAN = 1. This setting leads to a permanent repetition of the scan sequence. To stop or abort an ongoing scan sequence, the following mechanisms are supported: * An external gating signal can be selected to stop and to continue a scan sequence at any point in time controlled by an external module or signal, e.g. a timer unit or an input pin. The gating feature can be enabled and the polarity of the gating signal REQGTx can be selected by CRMRx.ENGT. The gating mechanism does not modify the contents of the conversion pending bits, but only prevents the request handling block from issuing conversion requests to the arbiter. The arbiter can be disabled by SW for this arbiter slot by clearing the corresponding bit ASENR.ASENx. This mechanism does not modify the contents of the conversion pending bits, but only prevents the arbiter from accepting requests from the request handling block. The pending request bits can be cleared by writing bit CRMRx.CLRPND = 1. It is recommended to stop the scan sequence before clearing the pending bits. * * 16.2.8.3 Request Source Event and Interrupt A request source event of a scan source occurs if the last conversion of a scan sequence is finished (all pending bits = 0). A request source event interrupt can be generated based on a request source event according to the structure shown in Figure 16-10. If a request source event is detected, it sets the corresponding indication flag in register EVINFR. These flags can also be set by writing a 1 to the corresponding bit position, whereas writing 0 has no effect. The indication flags can be cleared by SW by writing a 1 to the corresponding bit position in register EVINCR. The service request output line SRx that is selected by the request source event interrupt node pointer bit fields in register EVINPR0 becomes activated each time the related request source event is detected or the related bit position in register EVINFR is written with a 1. The request source events and the result events share the same registers. The request source event is located at the bit position in register EVINFR: * Event 1: Request source event of scan source in arbitration slot 1. User's Manual ADC, UM_V0.1D6 16-41 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter request source event indication flag EVINFR. EVINFx set request source event interrupt enable CRMRx. ENSI request source event interrupt node pointer EVINPRy. EVINPx to SR0 scan sequence finished to SR1 request source event to SR2 to SR3 ADC_scan_source_int Figure 16-10 Interrupt Generation of a Scan Request Source User's Manual ADC, UM_V0.1D6 16-42 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2.9 Scan Request Source Registers 16.2.9.1 Conversion Request Control Register These registers contain the control and status bits of the scan request source(s). The index 1 describes the number of the arbitration slot where the request source is taking part in the arbitration. The conversion request control register contains the bits that are copied to the pending register when the load event occurs. This register can be accessed at two different addresses. One address for read and write access is given for CRCRx (leading to the attribute "rw"). The second address only used for write actions is given for CRPRx (leading to the additional attribute "h"). CRCR1 Conversion Request 1 Control Register XSFR(E8H) 15 CH 15 rwh 14 CH 14 rwh 13 CH 13 rwh 12 CH 12 rwh 11 CH 11 rwh 10 CH 10 rwh 9 CH 9 rwh 8 CH 8 rwh 7 CH 7 rwh 6 CH 6 rwh 5 CH 5 rwh 4 CH 4 rwh Reset Value: 0000H 3 CH 3 rwh 2 CH 2 rwh 1 CH 1 rwh 0 CH 0 rwh Field CHx (x = 0-15) Bits x Type Description rwh Channel Bit x Each bit corresponds to one analog input channel, the channel number CHx is defined by the bit position x in this register. 0B The analog channel CHx will not be requested for conversion by this scan request source. 1B The analog channel CHx will be requested for conversion by this scan request source. User's Manual ADC, UM_V0.1D6 16-43 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2.9.2 Conversion Request Pending Register The conversion request pending register contains the bits that are requesting a conversion of the corresponding analog channel. A write operation to CRPRx leads to a data write to the bits in CRCRx with an automatic load event generation (leading to the attribute "w"). A read operation to CRPRx delivers the pending bits (leading to the attribute "rh"). CRPR1 Conversion Request 1 Pending Register XSFR(EAH) 15 14 13 12 11 10 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 CHP CHP CHP CHP CHP CHP CHP CHP CHP CHP CHP CHP CHP CHP CHP CHP 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh Field CHPx (x = 0-15) Bits x Type Description rwh Channel Pending Bit x Write view: A write to this address targets the bits in register CRCR1. Read view: Each bit corresponds to one analog channel, the channel number CHx is defined by the bit position in the register. 0B The analog channel CHx is not requested for conversion by this request source. 1B The analog channel CHx is requested for conversion by this request source. User's Manual ADC, UM_V0.1D6 16-44 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2.9.3 Conversion Request Mode Register The conversion request mode register contains bits to configure the desired operating mode of the scan request source. CRMR1 Conversion Request 1 Mode Register XSFR(ECH) 15 14 13 0 r 12 11 10 9 8 7 6 0 r 5 LD M rw 4 SC AN rw Reset Value: 0000H 3 EN SI rw 2 EN TR rw 1 0 LD CLR REQ EV PND GT w w rh ENGT rw Field ENGT Bits [1:0] Type Description rw Enable Gate This bit field enables the gating functionality for the request source. 00B The request source does not issue conversion requests. 01B The request source issues conversion requests if at least one pending bit is set. 10B The request source issues conversion requests if at least one pending bit is set and the selected gating signal REQGTx = 1. 11B The request source issues conversion requests if at least one pending bit is set and the selected gating signal REQGTx = 0. Enable External Trigger This bit enables the external trigger possibility. If enabled, the load event takes place if a rising edge is detected at the selected trigger input signal REQTR. 0B The external trigger is disabled. 1B The external trigger is enabled. Enable Source Interrupt This bit enables the request source interrupt generation if a request source event occurs (last pending conversion is finished). 0B The request source interrupt is disabled. 1B The request source interrupt is enabled. 16-45 V1.0, 2007-06 ENTR 2 rw ENSI 3 rw User's Manual ADC, UM_V0.1D6 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field SCAN Bits 4 Type Description rw Autoscan Enable This bit enables a permanent scan functionality. If enabled, the load event is automatically generated if a request source event occurs. 0B The permanent scan functionality is disabled. 1B The permanent scan functionality is enabled. Load Event Mode This bit defines the transfer mechanism triggered by the load event. With the load event, the value of register 0B CRCRx is copied to the pending register CRPRx (overwrite). 1B With the load event, the value of register CRCRx is bit-wisely logical OR combined to the pending register CRPRx. Request Gate Level This bit monitors the level at the REQGT input. The level is 0. 0B 1B The level is 1. Clear Pending Bits 0B No action. 1B The bits in register CRPRx are cleared. Generate Load Event No action. 0B 1B A load event is generated. Reserved returns 0 if read; should be written with 0; Analog to Digital Converter LDM 5 rw REQGT 7 rh CLRPND 8 w LDEV 9 w 0 6, [15:10] r User's Manual ADC, UM_V0.1D6 16-46 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2.10 Sequential Request Source Handling Sequential request sources have been introduced to allow short conversion sequences with freely programmable channel numbers (contrary to a scan request source with a fixed conversion order for the enabled channels). Two versions of the sequential sources are available in each ADC kernel: * Request source in arbitration slot 2: This request source can handle a sequence of up to 4 input channels (4-stage queue for 4 entries). This mechanism could be used to support application-specific conversion sequences, especially for timing-critical sequences containing multiple conversions of the same channel. Request source in arbitration slot 0: This request source can handle a single input channel (1-stage queue for 1 entry). This mechanism could be used for SW-controlled conversion requests or HWtriggered conversions of a single input channel (to "inject" a single conversion into a running sequence). * trigger inputs REQTR queue input refill trigger & gating unit gating inputs request source event E V intermediate queue stages queue stage 0 request source arbiter REQGT wait for trigger request request handling abort restart status sequential request source backup stage ADC_seq_reqsrc Figure 16-11 Sequential Request Source The internal structure and the handling of the sequential sources is similar for both versions. The programmed sequence is stored in a queue buffer (based on a FIFO mechanism) with at least one queue stage (stage 0) and a backup stage for aborted conversions. The only difference between both versions is given by the number of intermediate queue stages for storing the sequence. The request source in arbitration User's Manual ADC, UM_V0.1D6 16-47 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter slot 0 does not provide intermediate queue stages (1-stage queue with only queue stage 0), whereas the one in arbitration slot 2 provides 3 intermediate queue stages in additional to queue stage 0 (leading to a 4-stage queue). 16.2.10.1 Overview A sequential request source performs the: * Queue input: The queue input represents the programming interface where the sequence is defined (see QINR0, QINR2). It does not provide any buffer capability, but handles the filling of the queue buffer (queue stage 0 plus optional intermediate queue stages) by writing data to it. The contents of the queue stages can not be directly modified by program, except by the command for flushing the complete queue. The queue input also handles the refill mechanism, an automatic re-insertion of a started conversion from queue stage 0 (including the control parameters) as new queue input. This feature allows a single setup (by SW) of a conversion sequence and multiple repetitions of the same sequence without the need to re-program it each time. A conversion sequence is repeated automatically if all queue entries of the sequence are setup for refill mode. Queue stage 0: The contents of this queue stage defines which channel will be requested next for a conversion (see Q0R0, Q0R2). It also defines if the request should be triggered by an external event or if the requested conversion should follow the previous one as soon as possible. It also enables the request source interrupt generation after the conversion. The contents of this queue stage is cleared when the requested conversion is started and the next queue entry can be handled (if available). Queue backup stage: The queue backup stage is used to store the request control parameters when a conversion requested by this request source is aborted. A validation bit indicates that the aborted conversion has to be requested next (before the current contents of queue stage 0) to maintain the original sequence (see QBUR0, QBUR2). Request handling: The request handling block interfaces with the request source arbiter. It requests a conversion due to a valid information in queue stage 0 and handles the conversion status information. The control of the queue sequence is done based on bits in registers QMR0 (for the request source in arbitration slot 0) and QMR2 (for the arbitration slot 2). Trigger and gating signal handling: The trigger and gating unit interfaces with signals and modules outside the ADC module that can request conversions. For example, a timer unit can issue a request signal to synchronize conversions to PWM events. A trigger event can start a conversion request for the entry in queue stage 0 (see QMR0, QMR2). An event flag 16-48 V1.0, 2007-06 * * * * User's Manual ADC, UM_V0.1D6 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter QSRx.EV indicates that a trigger event has been detected (rising edge of selected trigger input signal REQTRx if enabled by QMRx.ENTR or write action with QMRx.TREV = 1). This bit is cleared with each conversion start requested by this source or by writing bits CEV = 1, FLUSH = 1, or CLRV = 1. 16.2.10.2 Sequential Source Operation To operate a sequential request source, the following aspects should be taken into account: * The sequence has to be initialized by writing to the queue input QINR0 (for arbitration slot 0) or QINR2 (for arbitration slot 2) when using the refill mechanism. Each write access corresponds to one conversion request. The desired sequence should be completely initialized before enabling the request source, because with enabled refill feature, write accesses by SW to QINRx are not allowed. If a trigger or gating function by external signals is desired, the gating and trigger inputs have to be defined by bit fields REQTRx and REQGTx in register PISEL (the value of x defines the number of the arbitration slot where the request source is connected). The gating mechanism has to be defined by QMRx.ENGT. If an external trigger mechanism is desired, it has to be enabled by QMRx.ENTR = 1. The corresponding arbitration slot has to be enabled to accept conversion requests from the sequential source (see register ASENR). * * * * To start a sequence of a sequential request source, the following mechanisms are supported: * An external trigger signal can be selected to start a scan sequence controlled by HW by an external module or signal, e.g. a timer unit or an input pin. The trigger feature is enabled by QMRx.ENTR = 1. The trigger event is generated if a rising edge is detected at the selected trigger input. A trigger event is generated under SW control by writing QMRx.TREV = 1. This mechanism starts a request if queue stage 0 contains valid data (or the queue backup stage respectively). A write operation to a queue input leads to a (new) valid queue entry. If the queue is empty (no valid entry), the written data arrives in queue stage 0 and starts a conversion request (if enabled by QMRx.ENGT and without waiting for an external trigger). If the refill mechanism is used, the queue inputs must not be written while the queue is running. Write operations to a completely filled queue are ignored. * * To stop or abort an ongoing sequence of a sequential request source, the following mechanisms are supported: * An external gating signal can be selected to stop and to continue a sequence at any point in time controlled by an external module or signal, e.g. a timer unit or an input pin. The gating feature can be enabled and the polarity of the gating signal can be 16-49 V1.0, 2007-06 User's Manual ADC, UM_V0.1D6 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter * * * selected by QMRx.ENGT. The gating mechanism does not modify the queue entries, but only prevents the request handling block from issuing conversion requests to the arbiter. The arbiter can be disabled by SW for this arbiter slot by clearing the corresponding bit ASENR.ASENx. This mechanism does not modify the queue entries, but only prevents the arbiter from accepting requests from the request handling block. The next pending queue entry is cleared by writing bit QMRx.CLRV = 1. It is recommended to stop the sequence before clearing a queue entry (ENGT = 00B). If the queue backup stage contains a valid entry, this one is cleared, otherwise a valid entry in queue register 0 is cleared. All queue entries are cleared by writing bit QMRx.FLUSH = 1. It is recommended to stop the sequence before clearing queue entries. 16.2.10.3 Request Source Event and Interrupt A request source event occurs when a conversion that has been requested by this source is completely finished. The interrupt enable bits are located in the queue 0 register (if this has not been a repeated start after an abort) or in the queue backup register (if this has been a repeated start after an abort). A request source event interrupt can be generated based on a request source event according to the structure shown in Figure 16-12. If a request source event is detected, it sets the corresponding indication flag in register EVINFR. These flags can also be set by writing a 1 to the corresponding bit position, whereas writing 0 has no effect. The indication flags can be cleared by SW by writing a 1 to the corresponding bit position in register EVINCR. The service request output line SRx that is selected by the request source event interrupt node pointer bit fields in register EVINPR0 becomes activated each time the related request source event is detected or the related bit position in register EVINFR is written with a 1. The request source events and the result events share the same registers. The request source event is located at the bit position in register EVINFR: * * Event 0: Request source event of sequential source in arbitration slot 0. Event 2: Request source event of sequential source in arbitration slot 2. User's Manual ADC, UM_V0.1D6 16-50 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter request source event indication flag EVINFR. EVINFx set request source event interrupt enable Q0Rx. ENSI request source event interrupt node pointer EVINPRy. EVINPx conversion finished triggered by request source request source event 0 to SR0 to SR1 to SR2 to SR3 1 QBURx. ENSI QBURx. V ADC_seq_source_int Figure 16-12 Interrupt Generation of a Sequential Request Source User's Manual ADC, UM_V0.1D6 16-51 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2.11 Sequential Source Registers 16.2.11.1 Queue Mode Register These registers contain the control and status bits of a sequential source. The index 0/2 describes the number of the arbitration slot where the request source is taking part in the arbitration. The queue mode register contains bits used to set the request source in the desired mode. Note: Before SW modifies the queue content by QMR.CLRV or QMR.FLUSH, all HW actions related to this queue have to be finished. Therefore, the arbitration slot has to be disabled and SW has to wait for at least two arbitration rounds (to be sure that this request source can no longer be an arbitration winner). Then, it has to check GLOBSTR.CRSC and GLOBSTR.BUSY to be sure that a conversion triggered by this request source is no longer running. Then SW can read QBURx and Q0Rx and can start modification of the queue content. QMR0 Queue 0 Mode Register QMR2 Queue 2 Mode Register 15 14 0 r 13 12 11 CEV w 10 FLU SH w 9 TR EV w XSFR(E0H) XSFR(F0H) 8 CLR V w 7 6 5 0 r 4 Reset Value: 0000H Reset Value: 0000H 3 2 EN TR rw 1 0 ENGT rw User's Manual ADC, UM_V0.1D6 16-52 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter Field ENGT Bits [1:0] Type Description rw Enable Gate This bit field enables the gating functionality for the request source. 00B The request source does not issue conversion requests. 01B The request source issues conversion requests if a valid conversion request is pending in the queue 0 register or in the backup register. 10B The request source issues conversion requests if a valid conversion request is pending in the queue 0 register or in the backup register and the selected gating signal REQGTx = 1. 11B The request source issues conversion requests if a valid conversion request is pending in the queue 0 register or in the backup register and the selected gating signal REQGTx = 0. Enable External Trigger This bit enables the external trigger possibility. 0B The external trigger is disabled and the trigger event is not generated. 1B The external trigger is enabled and a trigger event is generated if a rising edge is detected at the selected trigger input signal for REQTRx. Clear V Bit 0B No action. 1B The next pending valid queue entry in the sequence and the event flag EV are cleared. If there is a valid entry in the queue backup register (QBUR.V = 1), this entry is cleared, otherwise the entry in queue register 0 is cleared. ENTR 2 rw CLRV 8 w User's Manual ADC, UM_V0.1D6 16-53 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field TREV Bits 9 Type Description w Trigger Event 0B No action. 1B A trigger event is generated by SW. If the a valid entry in the request source waits for a trigger event, a conversion request is started. Flush Queue No action. 0B All entries in the queue (including the backup 1B stage) and the event flag EV are cleared. The queue contains no more valid entry. Clear Event Flag 0B No action. 1B Bit EV is cleared. Reserved returns 0 if read; should be written with 0; Analog to Digital Converter FLUSH 10 w CEV 11 w 0 [7:3], [15:8] r User's Manual ADC, UM_V0.1D6 16-54 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2.11.2 Queue Status Register The queue status register contains bits indicating the status of the sequential source. The filling level and the empty information refer to the queue intermediate stages (if available) and to the queue register 0. An aborted conversion stored in the backup stage is not indicated by these bits (therefore, see QBURx.V). QSR0 Queue 0 Status Register QSR2 Queue 2 Status Register 15 14 13 12 0 r 11 10 9 XSFR(E2H) XSFR(F2H) 8 EV rh 7 REQ GT rh 6 0 r 5 EMP TY rh 4 Reset Value: 0020H Reset Value: 0020H 3 0 r 2 1 FILL rh 0 Field FILL Bits [1:0] Type Description rh Filling Level1) This bit field indicates how many queue entries are valid in the sequential source. It is incremented each time a new entry is written to QINRx or by an enabled refill mechanism. It is decremented each time a requested conversion has been started. A new entry is ignored if the filling level has reached its maximum value. 00B EMPTY = 1:There is no valid entry in the queue. EMPTY = 0:There is 1 valid entries in the queue. 01B There are 2 valid entries in the queue. 10B There are 3 valid entries in the queue. 11B There are 4 valid entries in the queue. Queue Empty This bit indicates if the sequential source contains valid entries. 0B There are FILL+1 valid entries in the queue. 1B There are no valid entries (queue is empty). EMPTY 5 rh User's Manual ADC, UM_V0.1D6 16-55 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field REQGT Bits 7 Type Description rh Request Gate Level This bit monitors the level at the selected REQGT input. 0B The level is 0. 1B The level is 1. Event Detected This bit indicates that an event has been detected while at least one valid entry has been in the queue (queue register 0 or backup stage). Once set, this bit is cleared automatically when the requested conversion is started. 0B A trigger event has not been detected. 1B A trigger event has been detected. Reserved returns 0 if read; should be written with 0; Analog to Digital Converter EV 8 rh 0 1) [4:2], 6, [15:9] r This bit field is always 00B for the 1-stage queue in arbitration slot 0. User's Manual ADC, UM_V0.1D6 16-56 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2.11.3 Queue 0 Register The queue registers 0 monitor the status of the pending request (queue stage 0). Q0R0 Queue 0 Register 0 Q0R2 Queue 2 Register 0 15 14 13 12 0 r 11 10 9 XSFR(E4H) XSFR(F4H) 8 V rh 7 EX TR rh 6 EN SI rh 5 RF rh 4 Reset Value: 0000H Reset Value: 0000H 3 2 1 0 REQCHNR rh Field REQCHNR Bits [4:0] Type Description rh Request Channel Number This bit field indicates the requested channel number. Refill This bit indicates if the pending request is discarded after the conversion start or if it is automatically refilled into the queue input of the request queue. The request is discarded after the conversion 0B start. 1B The request is refilled into the queue after the conversion start. Enable Source Interrupt This bit indicates if a request source event interrupt is generated when the conversion is finished. 0B The request source event interrupt generation is disabled. 1B The request source event interrupt generation is enabled. External Trigger This bit indicates if a valid queue entry immediately leads to a conversion request or if the request handler waits for a trigger event. 0B The request handler does not wait for a trigger event. 1B The request handler waits for a trigger event. RF 5 rh ENSI 6 rh EXTR 7 rh User's Manual ADC, UM_V0.1D6 16-57 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field V Bits 8 Type Description rh Request Channel Number Valid This bit indicates if the queue register 0 contains a valid queue entry. 0B The queue entry is not valid and does not lead to a conversion request. 1B The queue entry is valid and leads to a conversion request. Reserved returns 0 if read; should be written with 0; Analog to Digital Converter 0 [15:9] r User's Manual ADC, UM_V0.1D6 16-58 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2.11.4 Queue Backup Register The queue backup registers monitor the status of an aborted sequential request. The registers QBURx and QINRx share the same register address. A read operation at this register address will deliver the "rh" bits of register QBURx. A write operation to this address will target the "w" bits in register QINRx. QBUR0 Queue 0 Backup Register QBUR2 Queue 2 Backup Register 15 14 13 12 0 r 11 10 9 XSFR(E6H) XSFR(F6H) 8 V rh 7 EXT R rh 6 EN SI rh 5 RF rh 4 Reset Value: 0000H Reset Value: 0000H 3 2 1 0 REQCHNR rh Field REQCHNR Bits [4:0] Type Description rh Request Channel Number This bit field contains the channel number of an aborted conversion that has been requested by this request source. Refill This bit contains the refill bit of an aborted conversion that has been requested by this request source. Enable Source Interrupt This bit contains the request source event interrupt enable bit of an aborted conversion that has been requested by this request source. External Trigger This bit contains the external trigger bit of an aborted conversion that has been requested by this request source. RF 5 rh ENSI 6 rh EXTR 7 rh User's Manual ADC, UM_V0.1D6 16-59 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field V Bits 8 Type Description rh Request Channel Number Valid This bit indicates if the entry in the queue backup register is valid (REQCHNR, RF, TR and ENSI are valid). Bit V is set if a running conversion that has been requested by this request source is aborted. It is cleared when the repeated conversion is started. The backup register does not contain a valid 0B entry. 1B The backup register contains a valid entry. It will be requested before a valid entry in queue register 0 will be requested. Reserved returns 0 if read; should be written with 0; Analog to Digital Converter 0 [15:9] r User's Manual ADC, UM_V0.1D6 16-60 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2.11.5 Queue Input Register The queue input register is the entry point for conversion requests of a sequential request source. The registers QBURx and QINRx share the same register address. A read operation at this register address will deliver the "rh" bits of register QBURx. A write operation to this address will target the "w" bits in register QINRx. QINR0 Queue Input Register 0 QINR2 Queue Input Register 2 15 14 13 12 0 r 11 10 9 XSFR(E6H) XSFR(F6H) 8 7 EX TR w 6 EN SI w 5 RF w 4 Reset Value: 0000H Reset Value: 0000H 3 2 1 0 REQCHNR w Field REQCHNR RF Bits [4:0] 5 Type Description w w Request Channel Number This bit field defines the requested channel number. Refill This bit defines the refill functionality for this queue entry. The content of this queue entry is not entered 0B again in QINRx when the related conversion is started. 1B The content of this queue entry is automatically entered again in QINRx when the related conversion is started. Enable Source Interrupt This bit defines the source interrupt functionality. 0B A request source event interrupt is not generated if the related conversion is finished. A request source event interrupt is generated 1B if the related conversion is finished. ENSI 6 w User's Manual ADC, UM_V0.1D6 16-61 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field EXTR Bits 7 Type Description w External Trigger This bit defines the external trigger functionality. 0B A valid queue entry immediately leads to a conversion request. A valid queue entry waits for a trigger event to 1B occur before issuing a conversion request. Reserved returns 0 if read; should be written with 0; Analog to Digital Converter 0 [15:8] r User's Manual ADC, UM_V0.1D6 16-62 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2.12 Channel-Related Functions The channel control unit defines the conversion settings, that can be programmed individually for each analog input channel. Therefore, a channel control register CHCTRx (x = 0 - 15) is associated to each analog input channel CHx. After the arbiter has determined the channel to be converted, the defined settings are applied to the AD converter, comprising information about: * Conversion parameters: Bit field ICLSEL defines which input class is taken into account for the conversion (see Section 16.2.12.1). Reference selection: Bit field REFSEL defines which reference input is used for the conversion (see Section 16.2.12.2) Channel event handling: Bit fields LCC, BNDASEL, and BNDBSEL define which boundaries are used for limit checking (see Section 16.2.12.4) and which channel event leads to a channel event interrupt (see Section 16.2.12.5). Synchronous conversion request: Bit SYNC defines if the channel triggers a synchronized conversion (see Section 16.2.17). * * * In addition to the general channel control, the ADC kernel supports a mechanism (named alias feature, see Section 16.2.12.3) to redirect a conversion request to another channel number. 16.2.12.1 Input Classes An input class defines the length of the sample phase and the resolution of the conversion. In most applications, the characteristics of the input circuitries (RC input lowpass filter and impedance of the signal source) are quite similar for several analog input signals, leading to similar timings for the sample phase of these channels. As a consequence, input channels with similar parameters can be grouped together to form an input class. All channels with the same ICLSEL setting belong to the same input class and have the same sample phase length and resolution. In the XC2000, 2 input classes are supported. Registers INPCRx (x = 0 - 1) can be programmed to adjust the sample time and the resolution to the application requirements independently for each input class. The default setting of these registers lead to the minimum sample phase length of 2 fADCI cycles and conversions with 10 bits resolution. If this default setting fits to the application requirements, bit fields CHCTRx (x = 0 - 15).ICLSEL and registers INPCRx (x = 0 - 1) need not to be changed. User's Manual ADC, UM_V0.1D6 16-63 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2.12.2 Reference Selection The conversion result of the ADC is always referring to a reference voltage. The maximum digital result value (full scale) is obtained if the analog input voltage equals the reference voltage. In order to support more than one measurement range with full scale digital representation, the user can select between the standard reference input VAREF and an alternative reference input at the analog input channel CH0 for each ADC kernel. The reference selection can be individually programmed for each input channel. This feature can be used to connect 5 V based sensors and 3.3 V based sensors to the same ADC kernel. In this case, one set of input channels refers to the standard reference input, whereas the other one refers to the voltage level at input CH0. Please note that the smallest granularity 1 LSBn for n bit resolution refers to the selected reference voltage. The granularity becomes very small if a low reference voltage is applied, and as a consequence, the resulting TUE increases due to noise effects. Therefore it is recommended to avoid small reference voltages. 16.2.12.3 Alias Feature The ADC kernel provides an alias feature, allowing a re-direction of conversion requests for channels CH0 or CH1 to other channel numbers. This feature can be used to measure the same input channel and to store the conversion results in two different result registers. * The same signal can be measured twice without the need to read out the conversion result to avoid data loss. This allows triggering both conversions quickly one after the other and being independent from CPU interrupt latency. The sensor signal is connected to only one input channel (instead of two analog inputs). This saves input pins in low-cost applications and only the leakage of one input has to be considered in the error calculation. Even if the analog input CH0 is used as alternative reference (see Figure 16-13), the internal trigger and data handling features for channel CH0 can be used. The channel settings for both conversions can be different (boundary values, interrupts, etc.). If a sequential conversion request source has been set up, a conversion request for channels CH0 or CH1 can be easily directed to other input channels without flushing the queue. * * * * In typical low-cost AC-drive applications, only one common current sensor is used to determine the phase currents. Depending on the applied PWM pattern, the measured value has different meanings and the sample points have to be precisely located in the PWM period. Figure 16-13 shows an example where the sensor signal is connected to one input channel (CHx) but two conversions are triggered for two different channels (CHx and CH0). With the alias feature, a conversion request for CH0 leads to a conversion of the analog input CHx instead of CH0, but taking into account the settings for CH0. Although the same analog input (CHx) has been measured, the conversion User's Manual ADC, UM_V0.1D6 16-64 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter results can be stored and read out from the result registers RESRx (conversion triggered for CHx) and RESRy (conversion triggered for CH0). Additionally, different interrupts or limit boundaries can be selected, enabled or disabled. sensor reference PWM timer CHx RESRx RESR0 ADC CH0 trigger CH0 trigger CHx ADC_alias Figure 16-13 Alias Feature 16.2.12.4 Limit Checking The limit checking mechanism automatically compares each conversion result to two boundary values (boundaries A and B). For each channel, the user can select these boundaries from a set of 4 programmable values (LCBR0 to LCBR3). With this structure, the conversion result range is split into three areas: * * * Area I: The conversion result is below or equal to both boundaries. Area II: The conversion result is above one boundary and below or equal to the other boundary. Area III: The conversion result is above both boundaries. boundaries A channel number B analog part arbiter conversion finished conversion result limit checking channel event ADC_channel_events_overv Figure 16-14 Channel Event Generation User's Manual ADC, UM_V0.1D6 16-65 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter Bit field LCC in the channel control register defines the condition to generate a channel event, leading to a channel event interrupt: * * * * * * * * LCC = 000B: No trigger, the channel event generation is disabled. LCC = 001B: A channel event is generated if the conversion result is not in area I. LCC = 010B: A channel event is generated if the conversion result is not in area II. LCC = 011B: A channel event is generated if the conversion result is not in area III. LCC = 100B: A channel event is always generated (regardless of the boundaries). LCC = 101B: A channel event is generated if the conversion result is in area I. LCC = 110B: A channel event is generated if the conversion result is in area II. LCC = 111B: A channel event is generated if the conversion result is in area III. Figure 16-15 shows an example for limit checking where channel events are generated only if the conversion results are not in the normal operating range defined by area II (LCC = 010B). Typical applications for limit checking are temperature monitoring or overcurrent sensing. As long as the measured temperature value is below a boundary value, the CPU does not need to be informed. In this case, a channel event should be generated only if the conversion result is in area III (LCC = 111B) to indicate an over-temperature condition. If the conversion of the analog temperature input signal is part of an auto-scan sequence autonomously triggered on a regular time base, the CPU load for the temperature monitoring is zero until the over-temperature condition is detected. In the case of an over-current protection, the channel event can be used to disable PWM generation to reduce the current (in the XC2000, an interrupt output line of the ADC module is connected to a corresponding input of the CCU6x units to allow fast reactions without CPU intervention). conv ersion result range for n bit res olution area III area II area I conversion results with channel events 2 -1 boundary B n conversion results without channel events conversion results with channel events boundary A 0 ADC_limit_check Figure 16-15 Limit Checking Note: It is also possible to select the same boundary register for boundaries A and B. In this case, the conversion result range is split into two ranges (area II is empty). User's Manual ADC, UM_V0.1D6 16-66 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2.12.5 Channel Event Interrupts A channel event interrupt can be generated based on a channel event according to the structure shown in Figure 16-16. If a channel event is detected, it sets the corresponding indication flag in register CHINFR. These flags can also be set by writing a 1 to the corresponding bit position, whereas writing 0 has no effect. The indication flags can be cleared by SW by writing a 1 to the corresponding bit position in register CHINCR. to SR0 channel event to SR1 channel event flags FC0 FC1 . .. channel event node pointers CHENP0 CHENP1 . .. to SR2 to SR3 channel number FC15 CHENP15 ADC_channel_events_routing Figure 16-16 Channel Event Interrupt Generation The service request output line SRx that is selected by the channel node pointer bit fields in registers CHINPR0, CHINPR4, CHINPR8, or CHINPR12 is activated each time the related channel event is detected or the related bit position in register CHINFR is written with a 1. User's Manual ADC, UM_V0.1D6 16-67 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2.13 Channel-Related Registers 16.2.13.1 Channel Control Registers The channel control registers contain bits to select the targeted result register, to control the limit check mechanism and to select an input class. The channel control register 0 defines the settings for the input channel CH0, etc. CHCTRx (x = 0 - 15) Channel x Control Register 15 0 r 14 13 RESR SEL rw 12 11 10 XSFR(20H + x * 2) 9 REF SEL rw 8 7 SYN C rw 6 5 LCC rw 4 Reset Value: 0000H 3 2 1 0 ICL SEL rw BNDB SEL rw BNDA SEL rw Field BNDASEL Bits [1:0] Type Description rw Boundary A Selection This bit field defines which boundary will be taken as boundary A for the limit checking. 00B The value given by register LCBR0 is selected. 01B The value given by register LCBR1 is selected. 10B The value given by register LCBR2 is selected. 11B The value given by register LCBR3 is selected. Boundary B Selection This bit field defines which boundary will be taken as boundary B for the limit checking. 00B The value given by register LCBR0 is selected. 01B The value given by register LCBR1 is selected. 10B The value given by register LCBR2 is selected. 11B The value given by register LCBR3 is selected. Limit Check Control This bit field defines the behavior of the limit checking mechanism. Please refer to the coding in Section 16.2.12.4 on Page 16-65. BNDBSEL [3:2] rw LCC [6:4] rw User's Manual ADC, UM_V0.1D6 16-68 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field SYNC Bits 7 Type Description rw Synchronization Request This bit defines if a conversion request for this channel leads to a synchronized (parallel) conversion with other ADC kernels. This bit is only taken into account if the ADC kernel is a potential conversion master (SYNCTR.STSEL = 00), otherwise it is considered to be 0. 0B This channel does not request a synchronized conversion. 1B This channel requests a synchronized conversion if the ADC kernel is a potential synchronization master. Reference Input Selection This bit field defines the reference source for this channel. 00B The standard reference input VAREF is selected. 01B The alternative reference input CH0 is selected. 10B reserved, do not use 11B reserved, do not use Input Class Selection These bits are used to select the input class. 00B The input class 0 is selected. 01B The input class 1 is selected. 10B reserved, do not use 11B reserved, do not use Result Register Selection This bit field defines which result register will be the target of the conversion result of this channel. 000B The result register 0 is selected. 001B The result register 1 is selected. ... 111B The result register 7 is selected. Reserved returns 0 if read; should be written with 0; Analog to Digital Converter REFSEL [9:8] rw ICLSEL [11,10] rw RESRSEL [14:12] rw 0 15 r User's Manual ADC, UM_V0.1D6 16-69 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2.13.2 Input Class Registers The input class registers contain bits to control the sample time and the resolution for each input class. The input class register 0 defines the settings for the input class 0, etc. INPCRx (x = 0 - 1) Input Class Register x 15 14 13 0 r 12 11 10 XSFR(C0H + x * 2) 9 DW rw 8 7 6 5 4 Reset Value: 0000H 3 STC rw 2 1 0 Field STC Bits [7:0] Type Description rw Sample Time Control This bit field defines the additional length of the sample phase, given in analog clock cycles fADCI. A minimum sample phase of 2 analog clock cycles is extended by the programmed value. sample phase length = (2 + STC) / fADCI Data Width This bit field defines how many bits are converted for the result1). The MSBs of conversion results with different DW settings are left aligned in the result bit fields. Bit positions that are not converted are 0. 00B The result is 10 bits wide. 01B reserved, do not use 10B The result is 8 bits wide. 11B reserved, do not use Reserved returns 0 if read; should be written with 0; DW [9:8] rw 0 1) [15:10] r The setting 00B is default. In case a 10-bit AD converter is used, the combinations 01B and 11B are ignored by the converter and treated like 00B. User's Manual ADC, UM_V0.1D6 16-70 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2.13.3 Limit Check Boundary Registers The bit fields in these registers define compare value (boundary) for the limit checking unit. The reset values of the boundaries are defined as 10%, 90%, 33% and 66% of the complete result range (in 12 bit representation). LCBR0 Limit Check Boundary Register 0 LCBR1 Limit Check Boundary Register 1 LCBR2 Limit Check Boundary Register 2 LCBR3 Limit Check Boundary Register 3 15 14 0 r 13 12 11 10 9 XSFR(84H) XSFR(86H) XSFR(88H) XSFR(8AH) 8 7 6 5 4 Reset Value: 0198H Reset Value: 0E64H Reset Value: 0554H Reset Value: 0AA8H 3 2 1 0 r 0 BOUNDARY rw Field BOUNDARY Bits [11:2] Type Description rw Boundary for Limit Checking This bit field contains the value for the limit checking unit that is compared to the actual conversion result. The result of the limit check is used for the generation of the channel event, see Section 16.2.12.4. Reserved returns 0 if read; should be written with 0; 0 [1:0], [15:12] r User's Manual ADC, UM_V0.1D6 16-71 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2.13.4 Channel Event Indication Flag Register The channel event indication flag register CHINFR monitors the detected channel events. CHINFR Channel Event Indication Flag RegisterXSFR(90H) 15 14 13 12 11 10 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 CHIN CHIN CHIN CHIN CHIN CHIN CHIN CHIN CHIN CHIN CHIN CHIN CHIN CHIN CHIN CHIN F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh Field CHINFx (x = 0 - 15) Bits x Type Description rwh Channel x Event Indication Flag Flag CHINFx indicates that a channel event for channel x has been detected. Writing a 0 has no effect, whereas writing a 1 sets the written bit position and generates the corresponding interrupt request. 0B A channel x event has not yet been detected. 1B A channel x event has been detected. User's Manual ADC, UM_V0.1D6 16-72 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2.13.5 Clear Channel Event Indication Register Writing a 1 to a bit position in the channel indication clear register CHINCR clears the corresponding channel event indication flag CHINFx in register CHINFR. If a channel event is detected when the corresponding bit position is written with a 1, flag CHINFx is cleared. CHINCR Channel Event Indication Clear Register XSFR(92H) 15 14 13 12 11 10 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 CHIN CHIN CHIN CHIN CHIN CHIN CHIN CHIN CHIN CHIN CHIN CHIN CHIN CHIN CHIN CHIN C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 w w w w w w w w w w w w w w w w Field CHINCx (x = 0 - 15) Bits x Type Description w Clear Channel Indication Flag 0 No action. 1 Flag CHINFR.x is cleared. User's Manual ADC, UM_V0.1D6 16-73 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2.13.6 Channel Interrupt Node Pointer Registers The bit fields in these registers define the service request output ADCx_SR[3:0] that is used to signal a channel event interrupt. CHINPR0 Channel Interrupt Node Pointer Register 0 XSFR(98H) 15 0 r 14 13 12 11 0 r 10 9 8 7 0 r 6 5 4 Reset Value: 0000H 3 0 r 2 1 0 CHINP3 rw CHINP2 rw CHINP1 rw CHINP0 rw Field CHINP0, CHINP1, CHINP2, CHINP3 Bits [1:0], [5:4], [9:8], [13:12] Type Description rw Interrupt Node Pointer for Channel x This bit field selects which service request output indicates a channel event interrupt of channel x. 00B Service request output SR0 is selected. 01B Service request output SR1 is selected. 10B Service request output SR2 is selected. 11B Service request output SR3 is selected. Reserved returns 0 if read; should be written with 0; 0 [3:2], [7:6], [11:10], [15:14] r CHINPR4 Channel Interrupt Node Pointer Register 4 XSFR(9AH) 15 0 r 14 13 12 11 0 r 10 9 8 7 0 r 6 5 4 Reset Value: 0000H 3 0 r 2 1 0 CHINP7 rw CHINP6 rw CHINP5 rw CHINP4 rw User's Manual ADC, UM_V0.1D6 16-74 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter Field CHINP4, CHINP5, CHINP6, CHINP7 Bits [1:0], [5:4], [9:8], [13:12] Type Description rw Interrupt Node Pointer for Channel x This bit field selects which service request output indicates a channel event interrupt of channel x. 00B Service request output SR0 is selected. 01B Service request output SR1 is selected. 10B Service request output SR2 is selected. 11B Service request output SR3 is selected. Reserved returns 0 if read; should be written with 0; 0 [3:2], [7:6], [11:10], [15:14] r CHINPR8 Channel Interrupt Node Pointer Register 8 XSFR(9CH) 15 0 r 14 13 12 11 0 r 10 9 8 7 0 r 6 5 4 Reset Value: 0000H 3 0 r 2 1 0 CHINP11 rw CHINP10 rw CHINP9 rw CHINP8 rw Field CHINP8, CHINP9, CHINP10, CHINP11 Bits [1:0], [5:4], [9:8], [13:12] Type Description rw Interrupt Node Pointer for Channel x This bit field selects which service request output indicates a channel event interrupt of channel x. 00B Service request output SR0 is selected. 01B Service request output SR1 is selected. 10B Service request output SR2 is selected. 11B Service request output SR3 is selected. Reserved returns 0 if read; should be written with 0; 0 [3:2], [7:6], [11:10], [15:14] r User's Manual ADC, UM_V0.1D6 16-75 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary CHINPR12 Channel Interrupt Node Pointer Register 12 XSFR(9EH) 15 0 r 14 13 12 11 0 r 10 9 8 7 0 r 6 5 4 Analog to Digital Converter Reset Value: 0000H 3 0 r 2 1 0 CHINP15 rw CHINP14 rw CHINP13 rw CHINP12 rw Field CHINP12, CHINP13, CHINP14, CHINP15 Bits [1:0], [5:4], [9:8], [13:12] Type Description rw Interrupt Node Pointer for Channel x This bit field selects which service request output indicates a channel event interrupt of channel x. 00B Service request output SR0 is selected. 01B Service request output SR1 is selected. 10B Service request output SR2 is selected. 11B Service request output SR3 is selected. Reserved returns 0 if read; should be written with 0; 0 [3:2], [7:6], [11:10], [15:14] r User's Manual ADC, UM_V0.1D6 16-76 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2.13.7 Alias Register The alias register contains bits to change a requested channel number from CH0 and CH1 to another channel number, see also Section 16.2.12.3. The programmed alias channel number is replacing the internally requested number for analog input multiplexer (of the converter). The internally requested channel number is taken into account for all other internal actions and the synchronization request. ALR0 Alias Register 0 15 14 0 r 13 12 0 rw 11 10 9 XSFR(1CH) 8 7 6 0 r 5 4 0 rw Reset Value: 0100H 3 2 1 0 ALIAS1 rw ALIAS0 rw Field ALIAS0 Bits [3:0] Type Description rw Alias Value for CH0 Conversion Requests The channel indicated in this bit field is converted instead of channel CH0. The conversion is done with the settings defined for channel CH0. Alias Value for CH1 Conversion Requests The channel indicated in this bit field is converted instead of channel CH1. The conversion is done with the settings defined for channel CH1. Reserved for Future Use Bit is reserved for future use and has to be written with 0B. Reserved returns 0 if read; should be written with 0; ALIAS1 [11:8] rw 0 4, 12 rw 0 [7:5], [15:13] r User's Manual ADC, UM_V0.1D6 16-77 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2.14 * * * * * Conversion Result Handling The result generation part handles the: Storage of the conversion results (see Section 16.2.14.1) Wait-for-read mode (see Section 16.2.14.2) Result event interrupts (see Section 16.2.14.3) Result FIFO buffer (see Section 16.2.14.4) Data reduction or anti-aliasing filtering (see Section 16.2.14.5) AD conversion stage conversion finished result registers 0-7 set condition data valid flags data reduction unit Figure 16-17 Conversion Result Handling result events ADC_result_handling 16.2.14.1 Storage of Conversion Results For each analog input channel, the associated channel control register CHCTRx (x = 0 15) contains a pointer bit field (RESRSEL) defining the result register to store the conversion result of this channel. This structure allows the user to direct conversion results of different channels to one or more result registers. Depending on the application needs (data reduction, auto-scan, alias feature, result FIFO, etc.), the user can distribute the conversion results to minimize CPU load or to be more tolerant against interrupt latency. An individual data valid flag VFR.VFx for each result register indicates that "new" valid data has been stored in the corresponding result register and can be read out. Due to different result handling mechanisms, the conversion result can be represented in different ways: * Data reduction filter disabled: The conversion result is maximum 10 bits wide with the MSB of the conversion result being always at bit position 11 and the remaining LSBs filled with 0. The data valid flag is set and a result event occurs each time a new conversion result is stored in the result register. It is possible to share a result register among several analog input channels. Data reduction filter enabled: The conversion result is maximum 10 bits wide with the MSB of the conversion result being always at bit position 11 and the remaining LSBs filled with 0. The additional bits [13:12] show the MSBs of the data accumulation. The data valid flag is set and a result event occurs each time a data reduction 16-78 V1.0, 2007-06 * User's Manual ADC, UM_V0.1D6 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter sequence is finished and the final result is available in the result register. The channel number is not included in the result register read view. In order to support a wait-for-read and FIFO buffer features, the valid flag has to be cleared automatically when SW does a read access or the result is transferred into another FIFO element (if result FIFO buffering is enabled). This behavior is contradictory to debugging requirements. For debugging, it has to be possible to introduce read or write commands into the normal program flow, e.g. to monitor conversion results. If a debugger reads out a result register, it would change the status of the conversion result from valid = "new" (not yet read out) to "old" (already read out). This would have an undesired impact on the application. Therefore, the read views with "V" deliver the same value as the read views without "V", but without clearing the valid bit. As a result, a debugger using read views with "V" can monitor the conversion results without influencing their status for the application. The application requirements for results with enabled or disabled data reduction filter being different and debugger accesses can occur, four different scenarios with different result register read views are supported. The four read views refer to the same result register contents, but show a different behavior according to the address that has been read: * Standard read view RESRx (x = 0-7): The data reduction filter has to be disabled, the channel number is included to identify which channel has been converted, and a read action clears the corresponding valid bit. This representation is compatible to the ADC result register in XC16x devices. Read view RESRAx (x = 0-7): The data reduction filter can be enabled, the channel number is not included, and a read action clears the corresponding valid bit. Read view RESRVx (x = 0-7) for debugger: The data reduction filter has to be disabled, the channel number is included, but a read action does not clear the corresponding valid bit. Read view RESRAVx (x = 0-7) for debugger: The data reduction filter can be enabled, the channel number is not included, but a read action does not clear the corresponding valid bit. * * * User's Manual ADC, UM_V0.1D6 16-79 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2.14.2 Wait-for-Read Mode The wait-for-read mode is a feature of a result register allowing the CPU (or PEC) to treat each conversion result independently without the risk of data loss. Data loss could occur if the CPU does not read a conversion result from a result register before a new result overwrites the previous one. Especially for auto-scan conversion sequences (or other sequences with "relaxed" timing requirements), the wait-for-read offers the possibility to request a conversion sequence according to an event (HW or SW), but to start a new conversion according to the CPU capability to read the formerly converted result. If wait-for-read mode is enabled for a result register by setting bit WFR in register RCRx (x = 0 - 7), a request source does not generate a conversion request while the targeted result register contains valid data (indicated by the valid flag VFx = 1) or if a currently running conversion targets the same result register. A new conversion request is generated only after the targeted result register has been read out. If two request sources target the same result register with wait-for-read selected, a lower priority request started before the higher priority source has requested its conversion can not be interrupted by the higher priority request. If a higher priority request targets a different result register, the lower priority conversion can be cancelled and repeated afterwards. User's Manual ADC, UM_V0.1D6 16-80 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2.14.3 Result Event Interrupts A result event interrupt can be generated based on a result event according to the structure shown in Figure 16-18. If a result event is detected, it sets the corresponding indication flag in register EVINFR. These flags can also be set by writing a 1 to the corresponding bit position, whereas writing 0 has no effect. The indication flags can be cleared by SW by writing a 1 to the corresponding bit position in register EVINCR. result event indication flag EVINFR. EVINFx set result event result event interrupt interrupt enable node pointer RCRx. IEN EVINPRy. EVINPx to SR0 new data available to SR1 result event to SR2 to SR3 ADC_result_event_int Figure 16-18 Result Event Interrupt Generation The service request output line SRx that is selected by the result event interrupt node pointer bit fields in registers EVINPR8 or EVINPR12 issues an interrupt each time the related result event is detected or the related bit position in register EVINFR is written with a 1. The result events and the request source events share the same registers. The result events are located at the following bit positions in register EVINFR: * * * * Event 8: Result event of result register 0. Event 9: Result event of result register 1. ... Event 15: Result event of result register 7. User's Manual ADC, UM_V0.1D6 16-81 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2.14.4 Result FIFO Buffer If a result register is not used as direct target for a conversion result, it can be concatenated with other result registers of the same ADC kernel to form a result FIFO buffer (first-in-first-out buffer mechanism). This allows to store measurement results and to read them out later with a "relaxed" CPU access timing. It is possible to set up more than one FIFO buffer structure with the available result registers. A FIFO structure can be built by at least two "neighbor" result registers with the indices x and z = x+1, where result register z represents the input and result register x represents the output of the FIFO buffer. The conversion result has to be delivered by the converter stage to the FIFO input, whereas the buffered data has to be read out from the FIFO output. The FIFO buffer function can be enabled by setting bit FEN in registers RCRx (x = 0 - 7). In the example shown in Figure 16-19, the result registers have been configured to form two FIFO buffers with two buffer stages (result registers 0/1 and 6/7, respectively), one FIFO buffer with three buffer stages (result registers 2/3/4), whereas result register 5 is used as "normal" result register without additional FIFO buffer functionality. conversion results CH2, 7, 10 result register 7 result register 6 result register 5 result register 4 result register 3 result register 2 CPU read out CPU read out conversion results CH8 AD conversion stage conversion results all other channels (e.g. for scan) CPU read out conversion results CH3 result register 1 result register 0 CPU read out ADC_result_FIFO Figure 16-19 Result FIFO Buffers If more than two result neighbor registers are concatenated to a FIFO buffer (from result register z to result register x, with z > x), the one with the highest index (z) is always the input and the one with the lowest index (x) is always the output. All intermediate result registers y (x < y < z) are used as intermediate FIFO stages without data input or data output functionality. Result register features for each FIFO buffer: * Result register z (FIFO buffer input): This result register can be enabled for data reduction. The wait-for-read mode is 16-82 V1.0, 2007-06 User's Manual ADC, UM_V0.1D6 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter * * supported to avoid data loss if the FIFO is full. Result event interrupt generation is not supported. Must not be read at a read view modifying the valid bit. Result register y (intermediate buffer stage): This/these result register(s) must not be enabled neither for wait-for-read mode, nor for data reduction. Result event interrupt generation is not supported. Must not be read at a read view modifying the valid bit, nor be the target of a conversion result. Result register x (FIFO buffer output): This result register can be enabled for result event interrupt generation to inform the CPU that new data can be read out from this register location. Data reduction and wait-for-read are not supported and have to be disabled. Must not be the target of a conversion result. If enabled, a result interrupt is generated for each data word in the FIFO. User's Manual ADC, UM_V0.1D6 16-83 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2.14.5 Data Reduction Filter The data reduction filter can be used as digital filter for anti-aliasing or decimation purposes. It can accumulate a maximum of 4 conversion results to generate a final result. Each result register can be individually enabled for data reduction. The feature is controlled by bit field DRCTR in registers RCRx (x = 0 - 7). The actual status is given by bit field DRC (data reduction counter) in the same register. Conversion delivering results to other result registers do not influence the data reduction filter of result register x. As a consequence, other channels can be converted between two conversions targeting result register x. r0 r1 r2 r3 r4 r5 r6 r7 r8 conversion results for RESRAx RCRx.DRC 0 3 2 1 r0 + r1 + r2 0 r0 + r1 + r2 + r3 3 2 1 r4 + r5 + r6 0 r4 + r5 + r6 + r7 0 r0 r0 + r1 r4 r4 + r5 contents of RESRAx VFR.VFx t1 t2 t3 t4 t5 t6 t7 t8 t9 ADC_DRC Figure 16-20 Data Reduction Filter In the example given in Figure 16-20, a data reduction sequence of 4 accumulated conversion results is shown. The data reduction is based on three rules: * Each time bit field DRC is 0 and a conversion targeting result register x is completed (t1, t5, t9), the contents of bit field RCRx.DRCTR is loaded into bit field DRC and the conversion result is stored in result register x. Each time bit field DRC is not 0 and a conversion targeting result register x is completed (t2, t3, t4 for the first final result and t6, t7, t8 for the next one), bit field DRC is decremented by 1 and the conversion result is added to the value already stored in result register x. Each time bit field DRC is 0 after decrementing or after loading it with RCRx.DRCTR = 0 (t4 for the first final result and t8 for the next one), the valid bit for the result register x becomes set and a result register event occurs. * * User's Manual ADC, UM_V0.1D6 16-84 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter The final result of a data reduction sequence has to be read out from result register x before the next data reduction sequence starts (interval between t4 and t5, or t8 and t9 respectively). With the read out of the final result from this register, the valid flag is automatically cleared. If this interval is too short, it is recommended to associate a second result register z to result register x by enabling the result FIFO mechanism for result register x, see Figure 16-21 (z = x + 1). In this case, result register x is loaded with the final result elaborated by result register z when a data reduction sequence is finished. The final result has to be read out from result register x before the next data reduction sequence is finished (interval between t4 and t8). 0 r0 r0 + r1 r0 + r1 + r2 r0 + r1 + r2 + r3 r4 r4 + r5 r4 + r5 + r6 r4 + r5 + r6 + r7 contents of RESRAx VFR.VFx 0 r0 + r1 + r2 + r3 r4 + r5 + r6 + r7 contents of RESRAx-1 VFR.VFx-1 t1 t2 t3 t4 t5 t6 t7 t8 t9 ADC_DRC_FIFO Figure 16-21 Data Reduction Filter with Result FIFO User's Manual ADC, UM_V0.1D6 16-85 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2.15 Conversion Result-Related Registers 16.2.15.1 Standard Views RESRx and RESRVx These result registers deliver the conversion result and the related channel number. The corresponding valid flag is cleared when register RESRx is read, whereas it is left unchanged when reading RESRVx. RESRx (x = 0-7) Result Register x RESRVx (x = 0-7) Result Register x, View V 15 14 13 12 11 10 XSFR(40H + 2 * x) XSFR(60H + 2 * x) 9 8 7 6 5 4 Reset Value: 0000H Reset Value: 0000H 3 2 1 0 r 0 CHNR rh RESULT rh Field RESULT CHNR Bits [11:2] [15:12] Type Description rh rh Conversion Result This bit field contains the conversion result. Channel Number This bit field contains the channel number of the latest register update. In case that the external multiplexer control is enabled, bits CHNR[3:1] are replaced by the multiplexer setting EMUX[2:0]. Reserved returns 0 if read; should be written with 0; 0 [1:0] r User's Manual ADC, UM_V0.1D6 16-86 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2.15.2 Data Reduction Read Views RESRAx and RESRAVx These result registers deliver the accumulated conversion result and no channel number. The corresponding valid flag is cleared when register RESRAx is read, whereas it is left unchanged when reading RESRAVx. RESRAx (x = 0-7) Result Register x, View A RESRAVx (x = 0-7) Result Register x, View AV 15 0 r 14 13 12 11 10 XSFR(50H + 2 * x) XSFR(70H + 2 * x) 9 8 7 6 5 4 Reset Value: 0000H Reset Value: 0000H 3 2 1 0 r 0 RESULT rh Field RESULT Bits [13:0] Type Description rh Conversion Result This bit field contains the result of the data reduction filter. Reserved returns 0 if read; should be written with 0; 0 [1:0], [15:14] rh User's Manual ADC, UM_V0.1D6 16-87 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2.15.3 Result Status Shadow Register The result status shadow register contains the status information related to the latest result register (view without extension "V") that has been read out. The update of the bit fields is done when a result register is read out. RSSR Result Status Shadow Register 15 0 r 14 13 RRNR rh 12 11 10 9 XSFR(82H) 8 0 r 7 6 5 4 Reset Value: 0000H 3 2 1 0 CHNR rh Field CHNR Bits [3:0] Type Description rh Channel Number This bit field indicates the channel number related to the latest result that has been read out. Result Register Number This bit field indicates to which result register the information stored in CHNR belongs. Reserved returns 0 if read; should be written with 0; RRNR [14:12] rh 0 [11:4], 15 r User's Manual ADC, UM_V0.1D6 16-88 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2.15.4 Valid Flag Register The valid flag register contains the flags indicating that the corresponding result register contents are valid (valid = "new" = not read out). VFR Valid Flag Register 15 14 13 12 0 r 11 10 9 XSFR(80H) 8 7 VF 7 rwh 6 VF 6 rwh 5 VF 5 rwh 4 VF 4 rwh Reset Value: 0000H 3 VF 3 rwh 2 VF 2 rwh 1 VF 1 rwh 0 VF 0 rwh Field VFx (x = 0 - 7) Bits x Type Description rwh Valid Flag for Result Register x This bit indicates that the contents of the result register x is valid. Writing a 0 has no effect, whereas writing a 1 clears the written bit position. If a hardware event triggers the setting of a bit VFx and SW writes a 1 to the same bit position, the bit VFx is cleared (software overrules hardware). 0B The result register x does not contain valid data. Either this register has been read out or no data has been moved to it. 1B The result register x contains valid data that has not yet been read out. Reserved returns 0 if read; should be written with 0; 0 [15:8] r User's Manual ADC, UM_V0.1D6 16-89 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2.15.5 Result Control Registers The result control registers contain bits to control the behavior of the result registers and to monitor their status. RCRx (x = 0 - 7) Result Control Register x 15 14 0 r 13 12 VF rh 11 0 r 10 XSFR(B0H + x * 2) 9 8 7 0 r 6 5 4 Reset Value: 0000H 3 0 r 2 1 0 DRC rh WFR FEN IEN rw rw rw DRCTR rw Field DRCTR Bits [1:0] Type Description rw Data Reduction Control This bit field defines how many conversion results are accumulated for data reduction (see Section 16.2.14.5). It defines the reload value for bit field DRC. 00B The data reduction filter is disabled. The reload value for DRC is 0, so no accumulation is done. 01B The data reduction filter is enabled. The reload value for DRC is 1, so the accumulation is done over 2 conversions. 10B The data reduction filter is enabled. The reload value for DRC is 2, so the accumulation is done over 3 conversions. 11B The data reduction filter is enabled. The reload value for DRC is 3, so the accumulation is done over 4 conversions. Interrupt Enable This bit enables the result event interrupt if a result event is detected for result register x. 0B The result event interrupt is disabled. The result event interrupt is enabled. 1B FIFO Enable This bit enables the FIFO functionality for result register x, see Section 16.2.14.4. 0B The FIFO functionality is disabled. 1B The FIFO functionality is enabled. 16-90 V1.0, 2007-06 IEN 4 rw FEN 5 rw User's Manual ADC, UM_V0.1D6 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field WFR Bits 6 Type Description rw Wait-for-Read Mode This bit enables the wait-for-read mode for result register x. 0B The wait-for-read mode is disabled. 1B The wait-for-read mode is enabled. Data Reduction Counter This bit field indicates how many conversion results have still to be accumulated to generate the final result for data reduction. The valid flag is automatically set and a result event is generated when this bit field becomes 0 (by decrementing or by reload). 00B The final result is available in the result register. 01B 1 more conversion result has to be added to obtain the final result in the result register. 10B 2 more conversion results have to be added to obtain the final result in the result register. 11B 3 more conversion results have to be added to obtain the final result in the result register. Valid Flag This flag indicates that the contents of the result register x is valid. It is another view of the corresponding bit in register VFR. 0B The result register x does not contain valid data. 1B The result register x contains valid data. Reserved returns 0 if read; should be written with 0; Analog to Digital Converter DRC [9:8] rh VF 12 rh 0 [3:2], 7, [11:10], [15:13] r User's Manual ADC, UM_V0.1D6 16-91 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2.15.6 Event Indication Flag Register The event indication flag register EVINFR monitors the detected request source events (flags EVINF0 - EVINF2) and result events (flags EVINF8 - EVINF15). EVINFR Event Indication Flag Register 15 14 13 12 11 10 9 XSFR(A0H) 8 7 6 5 0 r 4 Reset Value: 0000H 3 2 1 0 EVIN EVIN EVIN EVIN EVIN EVIN EVIN EVIN F15 F14 F13 F12 F11 F10 F9 F8 rwh rwh rwh rwh rwh rwh rwh rwh EVIN EVIN EVIN F2 F1 F0 rwh rwh rwh Field EVINFx (x = 0 - 2) Bits x Type Description rwh Event Indication Flag for Request Source x Flag EVINFx indicates that a request source event of request source x has been detected. Writing a 0 has no effect, whereas writing a 1 sets the written bit position and generates the corresponding interrupt request. 0B An event of request source x has not yet been detected. 1B An event of request source x has been detected. Event Indication Flag for Result Register x - 8 Flag EVINFx indicates that a result event of result register x-8 has been detected. Writing a 0 has no effect, whereas writing a 1 sets the written bit position and generates the corresponding interrupt request. 0B An event of result register x-8 has not yet been detected. 1B An event of result register x-8 has been detected. Reserved returns 0 if read; should be written with 0; EVINFx (x = 8 - 15) x rwh 0 [7:3] r User's Manual ADC, UM_V0.1D6 16-92 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2.15.7 Clear Event Indication Register Writing a 1 to a bit position in the event indication clear register EVINCR clears the corresponding event indication flag EVINFx in register EVINFR. If a request source or result event is detected when the corresponding bit position is written with a 1, flag EVINFx is cleared. EVINCR Event Indication Clear Register 15 14 13 12 11 10 9 XSFR(A2H) 8 7 6 5 0 r 4 Reset Value: 0000H 3 2 1 0 EVIN EVIN EVIN EVIN EVIN EVIN EVIN EVIN C15 C14 C13 C12 C11 C10 C9 C8 w w w w w w w w EVIN EVIN EVIN C2 C1 C0 w w w Field EVINCx (x = 0 - 2) EVINCx (x = 8 - 15) 0 Bits x Type Description w Clear Event Indication Flag for Request Source x 0 No action. 1 Bit EVINFR.x is cleared. Clear Event Indication Flag for Result Reg. x-8 0 No action. 1 Bit EVINFR.x is cleared. Reserved returns 0 if read; should be written with 0; x w [7:3] r User's Manual ADC, UM_V0.1D6 16-93 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2.15.8 Event Interrupt Node Pointer Registers The bit fields in these registers define the service request output SR[3:0] is used to signal a request source or result event interrupt. EVINPR0 Event Interrupt Node Pointer Register 0 XSFR(A8H) 15 14 13 0 r 12 11 10 9 8 7 0 r 6 5 4 Reset Value: 0000H 3 0 r 2 1 0 EVINP2 rw EVINP1 rw EVINP0 rw Field EVINP0, EVINP1, EVINP2 Bits [1:0], [5:4], [9:8] Type Description rw Interrupt Node Pointer for Request Source x This bit field selects which service request output indicates an event interrupt of request source x. 00B Service request output SR0 is selected. 01B Service request output SR1 is selected. 10B Service request output SR2 is selected. 11B Service request output SR3 is selected. Reserved returns 0 if read; should be written with 0; 0 [3:2], [7:6], [15:10] r EVINPR8 Event Interrupt Node Pointer Register 8 XSFR(ACH) 15 0 r 14 13 12 11 0 r 10 9 8 7 0 r 6 5 4 Reset Value: 0000H 3 0 r 2 1 0 EVINP11 rw EVINP10 rw EVINP9 rw EVINP8 rw User's Manual ADC, UM_V0.1D6 16-94 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter Field EVINP8, EVINP9, EVINP10, EVINP11 Bits [1:0], [5:4], [9:8], [13:12] Type Description rw Interrupt Node Pointer for Result Event x-8 This bit field selects which service request output indicates an event interrupt of result register x-8. 00B Service request output SR0 is selected. 01B Service request output SR1 is selected. 10B Service request output SR2 is selected. 11B Service request output SR3 is selected. Reserved returns 0 if read; should be written with 0; 0 [3:2], [7:6], [11:10], [15:14] r EVINPR12 Event Interrupt Node Pointer Register 12 XSFR(AEH) 15 0 r 14 13 12 11 0 r 10 9 8 7 0 r 6 5 4 Reset Value: 0000H 3 0 r 2 1 0 EVINP15 rw EVINP14 rw EVINP13 rw EVINP12 rw Field EVINP12, EVINP13, EVINP14, EVINP15 Bits [1:0], [5:4], [9:8], [13:12] Type Description rw Interrupt Node Pointer for Result Event x-8 This bit field selects which service request output indicates an event interrupt of result register x-8. 00B Service request output SR0 is selected. 01B Service request output SR1 is selected. 10B Service request output SR2 is selected. 11B Service request output SR3 is selected. Reserved returns 0 if read; should be written with 0; 0 [3:2], [7:6], [11:10], [15:14] r User's Manual ADC, UM_V0.1D6 16-95 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2.16 External Multiplexer Control If an application requires more analog inputs channels than available on the XC2000, the ADC kernel supports an extension of analog channels by adding an external analog multiplexer. Three output signals EMUX[2:0] are delivered by each ADC kernel to control the settings of an external analog multiplexer. They can be used to extend the number of analog input channels by adding an external 1-out-of-8 multiplexer. The external multiplexer control behavior is defined by the bits in register EMCTR. The current setting of EMUX[2:0] is given by bit field LASTEMUX. If another extended input channel should be converted, bit field SETEMUX has to be programmed to the desired value. This value is automatically applied with the start of the next conversion of the related analog ADC input channel. In the example shown in Figure 16-22 and in the description below, the analog input CH7 has been extended, leading to additional analog inputs named CH70 to CH77. In general, the external multiplexer support can be enabled for each of the input channels CH0 to CH7. direct input signals CH0 R EXT R EXT external analog 8-to-1 multiplexer CH70 C EXT CH6 internal analog multiplexer . .. C EXT CH7 ADC R EXT1 C EXT1 channel control extended input signals R EXT2 R EXT2 R EXT2 C EXT2 CH71 EMUX[2:0] EMUX control ADC kernel ADC_ext_mux C EXT2 CH77 . .. C EXT2 Figure 16-22 External Analog Multiplexer If the external multiplexer is located far from the ADC analog input, it is recommended to introduce an RC filter REXT1-CEXT1 directly at the analog input CH7 of the ADC. If needed for signal filtering, local RC filters REXT2-CEXT2 can be optionally added at the inputs of the external analog multiplexer. If the external multiplexer is located close to the analog ADC input, the components REXT1 and CEXT1 are not necessarily needed. In this case it is strongly recommended to User's Manual ADC, UM_V0.1D6 16-96 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter introduce RC filters (REXT2, CEXT2) at the multiplexer inputs. Please note that each RC filter limits the bandwidth of the analog input signal. The RC filters used with an external multiplexer may lead to another impedance "seen" by the ADC analog input CH7 than for the other (direct) analog inputs. The adaptation of the sample phase length can be done by using a different input class with a different value for the sample phase extension. This value can be adapted to execute conversions with an EMUX[2:0] setting that has changed a sufficiently long time before the conversion of CH7 starts. "A sufficiently long time before" signifies that signal transitions at the analog ADC input due to changing multiplexer setting are finished and the input signal is stable enough. After changing the EMUX[2:0] setting of the external multiplexer, an additional settling time has to elapse before the switched analog signal is stable and can be measured. To compensate for this settling time, an alternative sample phase length (instead of the one given by the input class) is automatically applied for the first conversion of CH7 after EMUX[2:0] has changed. The alternative sample phase length can be programmed by bit field EMCTR.EMSAMPLE. If the first conversion of CH7 after the EMUX[2:0] setting has changed is aborted due to a higher priority request, the repeated conversion of CH7 also uses the value of EMSAMPLE. The settling time is considered to be finished after the complete conversion of CH7. The automatic control of an external analog multiplexer related to conversions of an ADC input channel can be enabled by bits EMSELx in register EMENR. If bit EMSELx = 0, channel CHx does not influence any EMUX setting and the selected input class is always taken into account. If bit EMSELx = 1, the automatic multiplexer control is enabled for channel CHx. With each conversion start of CHx, the value of EMCTR.SETEMUX is copied to EMCTR.LASTEMUX that is output at EMUX[2:0]. In addition, the control logic checks if the value of LASTEMUX has changed to adapt the sample phase length accordingly. User's Manual ADC, UM_V0.1D6 16-97 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2.17 Synchronized Conversions for Parallel Sampling The independent ADC kernels implemented in the XC2000 can be synchronized for simultaneous measurements of analog input channels. While no parallel conversion is requested, the kernels can work independently. The synchronization mechanism for parallel conversions ensures that the sample phases of the related channel(s) start simultaneously. Different values for the resolution and the sample phase length of each kernel for a parallel conversion are supported. A parallel conversion can be requested individually for each input channel (also several channels can be enabled for parallel conversions). In the example shown in the figure below, input channels CH3 of the ADC kernels ADC0 and ADC1 are converted synchronously, whereas other input channels do not lead to parallel conversions. This leads to the following structure: * A synchronization master ADC kernel can request a conversion of an analog channel. If this channel is selected for a synchronized conversion, it is also requested in the connected slave ADC kernel(s). A synchronization slave ADC kernel reacts to incoming synchronized conversion requests from its master. While no incoming master requests are active, the slave kernel can convert its own requests. All ADC kernels in an ADC module being similar, each kernel can be set up to be a synchronization master or a synchronization slave (depending on the application needs, such as trigger capability of request sources). A synchronization master can synchronize several slave kernels, whereas a slave kernel can only be synchronized to one master kernel. * * * parallel conversions requested by ADC0 conversions kernel ADC0 CH0 CH2 CH3 CH7 CH8 CH3 parallel conversions triggering ADC1 conversions kernel ADC1 CH2 CH5 CH3 CH4 CH3 CH1 running conversion is aborted and repeated afterwards ADC_parallel_conv Figure 16-23 Parallel Conversions User's Manual ADC, UM_V0.1D6 16-98 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter The term "conversion group" has been introduced to define the kernel behavior allowing parallel sampling: * * * Kernels in the same conversion group can execute parallel conversions. A conversion group contains at least 1 ADC kernel and can contain a maximum of all ADC kernels of the ADC module. Each conversion group contains exactly one synchronization master kernel that issues a parallel conversion request and defines the internal frequencies fADCI and fADCD and the channel number for a parallel conversion of the conversion group. All other kernels in a conversion group are synchronization slaves and have to be programmed with the same values of GLOBCTR.DIVA, DIVD and ARBRND as the synchronization master. If there is no need for parallel conversions, each kernel can be considered to form an own conversion group with only an ADC kernel as synchronization master, but without any synchronization slave. The channel number and the synchronization request are issued by the synchronization master to the kernels in the same synchronization group if a conversion is requested with CHCTRx (x = 0 - 15).SYNC = 1 in the synchronization master kernel. Synchronization slaves can not issue synchronization requests. Once started, a parallel conversion can not be aborted. A parallel conversion request is always handled with highest priority and cancelinject-repeat mode in a synchronization slave (see Section 16.2.6.2). Bit GLOBCTR.ARBM has to be 0 for synchronization slaves. The wait-for-read mode is supported for the master kernel, whereas the setting is ignored in the slave kernels (previous results may be overwritten). * * * * * * * The synchronization request issuing mechanism of the master to the slave kernels is based on bit field GLOBSTR.ANON. The information given by GLOBCTR.ANON is distributed by the synchronization master to all kernels in the conversion group (the bit fields SYNCTR.STSEL of all kernels must be programmed in a way that all kernels refer to the same information). In addition to the ANON information, the master delivers the requested channel number to the slave (not explicitly shown in Figure 16-24). The start of the converters of all kernels of a conversion group is based on signals indicating when a kernel is ready and can start the sample phase of a parallel conversion. Bit SYNCTR.EVALR1 defines if a kernel has to wait for the other kernel(s) (to allow parallel conversions) or can start without waiting (no parallel conversions possible). To support parallel conversions, all ready signals of the kernels of a conversion group have to be considered. The alias feature is independent of synchronized conversions. All kernels of a conversion group request the same channel number (defined by the master), but can convert analog signals from different inputs. The requested channel number can be redirected by its alias setting. E.g., if the channel number requested in a conversion group is channel CH0, but for a kernel, an alternative reference is connected to this input, User's Manual ADC, UM_V0.1D6 16-99 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter the actually converted analog input can be changed to any value. This can be done by programming bit field ALIAS0 accordingly. Note: A parallel conversion in a slave ADC should not target a result register that is already used for data reduction of other channels. ADC1_ANON ADC0_ANON C I1 C I2 C I3 C I1 C I2 10 GLOBCTR. ANON SYNCTR. STSEL 00 GLOBCTR. ANON SYNCTR. STSEL 00 01 10 11 01 kernel control GLOBSTR. ANON SYNCTR. EVALR1 R3 kernel control GLOBSTR. ANON SYNCTR. EVALR1 R3 R1 R2 R1 ADC0 kernel R2 ADC1 kernel ADC0_READY ADC1_READY ADC_ANON_sync Figure 16-24 Synchronization via ANON and Ready Signals Table 16-4 SYNCTR Setting for Kernel Synchronization SYNCTR.EVALR1 SYNCTR.STSEL Operating Mode ADC0 Kernel (values to be programmed to ADC0_SYNCTR) no sync master of ADC1 slave of ADC1 0B 1B 1B 00B 00B 01B ADC1 Kernel (values to be programmed to ADC1_SYNCTR) no sync User's Manual ADC, UM_V0.1D6 0B 16-100 00B V1.0, 2007-06 11 C I3 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Table 16-4 Analog to Digital Converter SYNCTR Setting for Kernel Synchronization (cont'd) SYNCTR.EVALR1 1B 1B SYNCTR.STSEL 00B 01B Operating Mode master of ADC0 slave of ADC0 User's Manual ADC, UM_V0.1D6 16-101 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2.18 Additional Feature Registers 16.2.18.1 External Multiplexer Control Register The external multiplexer control register defines the settings of an external analog multiplexer. EMCTR External Multiplexer Control Register XSFR(D0H) 15 14 13 12 11 10 9 8 7 0 r 6 5 LAST EMUX rh 4 Reset Value: 0000H 3 0 r 2 1 SET EMUX rw 0 EMSAMPLE rw Field SETEMUX Bits [2:0] Type Description rw New Setting for External Multiplexer This bit field defines the EMUX[2:0] setting for the external multiplexer that will be selected for the next conversion of the enabled channel. Last Setting of External Multiplexer This bit field indicates the current EMUX[2:0] setting of the external multiplexer. This value has been selected for (at least) the last conversion of the enabled channel. External Multiplexer Sampling Time This bit field defines the alternative sample phase length in the case the external multiplexer setting has changed with the start of a conversion with enabled external multiplexer (the value given by the selected input class is not taken into account). A minimum sample phase of 2 analog clock cycles is extended by the programmed value. sample phase length = (2 + EMSAMPLE) / fADCI Reserved returns 0 if read; should be written with 0; LASTEMUX [6:4] rh EMSAMPLE [15:8] rw 0 3, 7 r User's Manual ADC, UM_V0.1D6 16-102 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.2.18.2 External Multiplexer Enable Register The external multiplexer enable register defines if a channel is enabled to control the settings of an external analog multiplexer. It is not allowed to enable the external multiplexer control for more than one analog input channel. EMENR External Multiplexer Enable Register XSFR(D6H) 15 0 r 14 EMS EL7 rw 13 0 r 12 EMS EL6 rw 11 0 r 10 EMS EL5 rw 9 0 r 8 EMS EL4 rw 7 0 r 6 EMS EL3 rw 5 0 r 4 EMS EL2 rw Reset Value: 0000H 3 0 r 2 EMS EL1 rw 1 0 r 0 EMS EL0 rw Field EMSELx (x = 0 - 7) Bits 2*x Type Description rw External Multiplexer Selection for Channel CHx This bit defines if an external multiplexer will be controlled by channel CHx. 0B The external multiplexer control is disabled. 1B The external multiplexer control is enabled for CHx. Reserved returns 0 if read; should be written with 0; 0 1, 3, 5, r 7, 9, 11, 13, 15 16.2.18.3 Synchronization Control Register The synchronization control register contains bits controlling the synchronization between several kernels for parallel conversions. The programming of register SYNCTR in the kernels of a conversion group has to be done while the bit fields GLOBSTR.ANON = 00B in all ADC kernels of the conversion group. Bit field ANON of the synchronization master can be set to 11B afterwards. It is recommended to avoid power saving modes (ANON = 01B or 10B) for parallel conversions. The bits EVALRx are only taken into account if a synchronized, parallel conversion is requested by a master. This ensures that the conversions of the ADC kernels of the same synchronization group are started at the same time for parallel sampling (although a kernel might be idle, the master and all its connected slaves have to wait for all of them being ready). User's Manual ADC, UM_V0.1D6 16-103 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary SYNCTR Synchronization Control Register XSFR(1AH) 15 14 13 12 11 0 r 10 9 8 7 6 0 rw 5 4 EVA LR1 rw Analog to Digital Converter Reset Value: 0000H 3 0 r 2 1 0 STSEL rw Field STSEL Bits [1:0] Type Description rw Start Selection This bit field controls the synchronization mechanism of the ADC kernel. 00B The kernel is a synchronization master. The kernel's own bit field GLOBCTR.ANON is taken into account. 01B The kernel is a synchronization slave. The control information at input CI1 is taken into account instead. 10B reserved, do not use (kernel is switched off) 11B reserved, do not use (kernel is switched off) Evaluate Ready Input R1 This bit defines if a kernel is considered to be part of a synchronization group. Parallel conversions can only be started if the synchronization master and all slaves of the conversion group indicate that they are ready to start a parallel conversion. 0B The ready input R1 is not considered for the start of a parallel conversion of this conversion group. 1B The ready input R1 is considered for the start of a parallel conversion of this conversion group. Reserved for Future Use returns 0 if read; must be written with 0; Reserved returns 0 if read; should be written with 0; EVALR1 4 rw 0 0 [6:5] [3:2], [15:7] r r User's Manual ADC, UM_V0.1D6 16-104 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.3 * * * * * * Implementation This section describes the implementation of the ADC kernels in the XC2000 device. Address map (see Section 16.3.1) Interrupt control registers (see Section 16.3.2) Analog connections of ADC0 (see Section 16.3.3.1) Analog connections of ADC1 (see Section 16.3.3.2) Digital connections of ADC0 (see Section 16.3.4.1) Digital connections of ADC1 (see Section 16.3.4.2) 16.3.1 Address Map The ADC kernels ADC0 and ADC1 are available at the following base addresses. The exact register address is given by the relative address of the register (given in Table 16-2) plus the kernel base address (given in Table 16-5) of the module. Table 16-5 Module ADC0 ADC1 Registers Address Space Base Address E000H E100H End Address E0FFH E1FFH Note 16.3.2 Interrupt Control Registers The interrupt control registers are located in the SFR area. They are described in the general interrupt chapter. Table 16-6 Short Name ADC_0IC ADC_1IC ADC_2IC ADC_3IC ADC_4IC ADC_5IC ADC_6IC ADC_7IC ADC Interrupt Control Registers Description Interrupt Control Register for SR0 of ADC0 Interrupt Control Register for SR1 of ADC0 Interrupt Control Register for SR2 of ADC0 Interrupt Control Register for SR3 of ADC0 Interrupt Control Register for SR0 of ADC1 Interrupt Control Register for SR1 of ADC1 Interrupt Control Register for SR2 of ADC1 Interrupt Control Register for SR3 of ADC1 User's Manual ADC, UM_V0.1D6 16-105 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.3.3 * * * Analog Connections The input channels of both ADC kernels are distributed as follows: 16 channels of ADC0 connected to P5 8 channels of ADC1 connected to P15 4 channels of ADC1 connected to P5 and overlaid to ADC0 inputs Each ADC kernel has its own reference input lines VAGND and VAREFx, with x = 0, 1. Depending on the package, these lines can be available as independent pins for high pin count packages or can be combined for low pin count packages. The respective voltage supply lines of both converters are connected together. 16.3.3.1 Analog Connections of ADC0 The table below lists the analog connections of ADC0. Table 16-7 Signal ADC0 Analog Connections in XC2000 from/to Module see pinning chapter I/O to ADC0 I I I I P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.6 P5.7 P5.8 P5.9 I I I I I I I I I I Can be used to/as Power supply and standard reference VDDPA VSS VAREF(0) VAGND Analog input channels CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 analog input channel 0 analog input channel 1 analog input channel 2 analog input channel 3 analog input channel 4 analog input channel 5 analog input channel 6 analog input channel 7 analog input channel 8 overlaid with ADC1 channel 8 analog input channel 9 overlaid with ADC1 channel 9 analog power supply analog power supply positive analog reference negative analog reference User's Manual ADC, UM_V0.1D6 16-106 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Table 16-7 Signal CH10 CH11 CH12 CH13 CH14 CH15 Analog to Digital Converter ADC0 Analog Connections in XC2000 (cont'd) from/to Module P5.10 P5.11 P5.12 P5.13 P5.14 P5.15 I/O to ADC0 I I I I I I Can be used to/as analog input channel 10 overlaid with ADC1 channel 10 analog input channel 11 overlaid with ADC1 channel 11 analog input channel 12 analog input channel 13 analog input channel 14 analog input channel 15 16.3.3.2 Analog Connections of ADC1 The table below lists the analog connections of ADC1. Table 16-8 Signal ADC1 Analog Connections in XC2000 from/to Module I/O to ADC1 analog I I I I P15.0 P15.1 P15.2 P15.3 P15.4 P15.5 P15.6 P15.7 I I I I I I I I positive analog reference negative analog reference analog input channel 0 analog input channel 1 analog input channel 2 analog input channel 3 analog input channel 4 analog input channel 5 analog input channel 6 analog input channel 7 Can be used to/as Power supply and standard reference VDDPA VSS VAREF(1) VAGND Analog input channels CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 see pinning chapter analog power supply User's Manual ADC, UM_V0.1D6 16-107 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Table 16-8 Signal Analog to Digital Converter ADC1 Analog Connections in XC2000 (cont'd) from/to Module P5.8 P5.9 P5.10 P5.11 n.c. I/O to ADC1 analog I I I I I Can be used to/as CH8 CH9 CH10 CH11 CH12..15 analog input channel 8 overlaid with ADC0 channel 8 analog input channel 9 overlaid with ADC0 channel 9 analog input channel 10 overlaid with ADC0 channel 10 analog input channel 11 overlaid with ADC0 channel 11 not available, do not request User's Manual ADC, UM_V0.1D6 16-108 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.3.4 Digital Connections The following table shows the digital connections of the ADC kernels with other modules or pins in the XC2000 device. The following sections refer to the inter-module connections, whereas the connections of the service request outputs SR[3:0] of each kernel to the interrupt control registers is given in Section 16.3.2. Note: The functional inputs of the ADC that are marked I(s) are additionally synchronized to fSYS before they can affect the module internal logic. The resulting delay of 2/fSYS and an uncertainty of 1/fSYS have to be taken into account for precise timing calculation. An edge of an input signal can only be correctly detected if the high phase and the low phase of the input signal are both longer than 1/fSYS. The functional inputs of the ADC that are marked I are already considered as synchronous to fSYS. 16.3.4.1 Digital Connections of ADC0 The table below lists the digital connections of ADC0. Table 16-9 Signal ADC0 Digital Connections in XC2000 from/to Module P6.0 P6.1 P6.2 ERU_GOUT0 ERU_GOUT1 P6.0 0 ERU_TOUT1 CCU60_T13_PM P6.1 P6.3 ERU_GOUT0 I/O to ADC0 O O O I I I (s) I (s) I I I (s) I (s) I Can be used to/as External multiplexer control EMUX[0] EMUX[1] EMUX[2] REQGT0A REQGT0B REQGT0C REQGT0D REQTR0A REQTR0B REQTR0C REQTR0D REQGT1A control of external analog multiplexer(s) control of external analog multiplexer(s) control of external analog multiplexer(s) source gate input A source gate input B source gate input C source gate input D source trigger input A source trigger input B source trigger input C source trigger input D source gate input A 16-109 V1.0, 2007-06 Request source 0 Request source 1 User's Manual ADC, UM_V0.1D6 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Table 16-9 Signal REQGT1B REQGT1C REQGT1D REQTR1A REQTR1B REQTR1C REQTR1D REQGT2A REQGT2B REQGT2C REQGT2D REQTR2A REQTR2B REQTR2C REQTR2D Analog to Digital Converter ADC0 Digital Connections in XC2000 (cont'd) from/to Module ERU_GOUT1 P6.0 0 ERU_TOUT1 CCU60_T13_PM P6.1 P6.3 ERU_GOUT0 ERU_GOUT1 P6.0 0 ERU_TOUT1 CCU62_T13_PM P6.1 P6.3 I/O to ADC0 I I (s) I (s) I I I (s) I (s) I I I (s) I (s) I I I (s) I (s) Can be used to/as source gate input B source gate input C source gate input D source trigger input A source trigger input B source trigger input C source trigger input D source gate input A source gate input B source gate input C source gate input D source trigger input A source trigger input B source trigger input C source trigger input D Request source 2 User's Manual ADC, UM_V0.1D6 16-110 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter 16.3.4.2 Digital Connections of ADC1 The table below lists the digital connections of ADC1. Table 16-10 ADC1 Digital Connections in XC2000 Signal from/to Module P7.2 P7.3 P7.4 ERU_GOUT0 ERU_GOUT1 P6.0 0 ERU_TOUT1 CCU61_T13_PM P6.1 P6.3 ERU_GOUT0 ERU_GOUT1 P6.0 0 ERU_TOUT1 CCU61_T13_PM P6.1 P6.3 ERU_GOUT0 ERU_GOUT1 P6.0 0 I/O to ADC1 O O O I I I (s) I (s) I I I (s) I (s) I I I (s) I (s) I I I (s) I (s) I I I (s) I (s) Can be used to/as External multiplexer control EMUX[0] EMUX[1] EMUX[2] REQGT0A REQGT0B REQGT0C REQGT0D REQTR0A REQTR0B REQTR0C REQTR0D REQGT1A REQGT1B REQGT1C REQGT1D REQTR1A REQTR1B REQTR1C REQTR1D REQGT2A REQGT2B REQGT2C REQGT2D control of external analog multiplexer(s) control of external analog multiplexer(s) control of external analog multiplexer(s) source gate input A source gate input B source gate input C source gate input D source trigger input A source trigger input B source trigger input C source trigger input D source gate input A source gate input B source gate input C source gate input D source trigger input A source trigger input B source trigger input C source trigger input D source gate input A source gate input B source gate input C source gate input D 16-111 V1.0, 2007-06 Request source 0 Request source 1 Request source 2 User's Manual ADC, UM_V0.1D6 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Analog to Digital Converter Table 16-10 ADC1 Digital Connections in XC2000 (cont'd) Signal REQTR2A REQTR2B REQTR2C REQTR2D from/to Module ERU_TOUT1 CCU63_T13_PM P6.1 P6.3 I/O to ADC1 I I I (s) I (s) Can be used to/as source trigger input A source trigger input B source trigger input C source trigger input D User's Manual ADC, UM_V0.1D6 16-112 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 2 17 Capture/Compare Unit 2 The XC2000 provides a Capture/Compare (CAPCOM2) unit which provides 16 capture/compare channels, which interact with 2 timers. A CAPCOM2 channel can capture the contents of a timer on specific internal or external events, or it can compare a timer's contents with given values, and modify output signals in case of a match. Data Registers Control Registers Interrupt Control T7, T7REL T8, T8REL E E T78CON T7IC T8IC CC16-CC19 CC20-CC23 CC24-CC27 CC28-CC31 CC2_M4 CC2_M5 CC2_M6 CC2_M7 CC2_SEE CC16IC-CC19IC CC20IC-CC23IC CC24IC-CC27IC CC28IC-CC31IC E E E E CC2_OUT CC2_SEM CC2_DRM CC2_IOC KSCFG CC16...31 CC16...31IC CCM4...7 T78CON T7, T8 T7/8REL T7IC, T8IC CAPCOM2 Register 16...31 CAPCOM2 Intr. Ctrl. Reg. 16...31 CAPCOM2 Mode Ctrl. Reg. 4...7 CAPCOM2 Timer Control Reg. CAPCOM2 Timer Register CAPCOM2 Timer Reload Register CAPCOM2 Timer x Intr. Ctrl. Reg. CC2_SEE CC2_SEM CC2_DRM CC2_OUT CC2_IOC CAPCOM Single Event En. Reg. CAPCOM Single Event Mode Reg. CAPCOM Double Reg. Mode Reg. CAPCOM Output Register CAPCOM Input/Outp. Control Reg. KSCFG Kernel State Configuration Register mc_capcom2_registers_p11.vsd Figure 17-1 SFRs Associated with the CAPCOM Units User's Manual CC12_X8, V2.1 17-1 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 2 With this mechanism, the CAPCOM2 unit supports generation and control of timing sequences on up to 16 channels with a minimum of software intervention. From the programmer's point of view, the term `CAPCOM2 unit' refers to a set of registers which are associated with this peripheral, including the port pins which may be used for alternate input/output functions, and their direction control bits (see also Figure 17-1). A CAPCOM2 unit is typically used to handle high speed IO tasks such as pulse and waveform generation, pulse width modulation, or recording of the time when a specific event occurs. It also supports the implementation of up to 16 software-controlled interrupt events. The CAPCOM2 Unit consists of two 16-bit timers (T7, T8), each with its own reload register (TxREL), and a bank of sixteen dual-purpose 16-bit capture/compare registers (CCy). The input clock for the CAPCOM2 timers is programmable to several prescaled values of the module input clock (fCC), or it can be derived from the overflow/underflow of timer T6. T7 may also operate in counter mode (from an external input), clocked by external events. Each capture/compare register may be programmed individually for capture or compare operation, and each register may be allocated to either of the two timers. Each capture/compare register has one signal associated with it, which serves as an input signal for the capture operation or as an output signal for the compare operation. The capture operation causes the current timer contents to be latched into the respective capture/compare register, triggered by an event (transition) on the associated input signal. This event also activates the associated interrupt request line. The compare operation may cause an output signal transition on the associated output signal, when the allocated timer increments to the value stored in a capture/compare register. The compare match event also activates the associated interrupt request line. In Double-register compare mode a pair of registers controls one common output signal. The compare output signals are available via a dedicated output register, and may also control the output latches of the connected port pins. The output path can be selected. For the switching of the output signals two timing schemes (see Section 17.8) can be selected: In Staggered Mode1) the output signals are switched consecutively in 8 steps, which distributes the switching steps over a certain time. In staggered mode, the maximum resolution is 8 tCC. In Non-Staggered Mode the output signals are switched immediately at the same time. In non-staggered mode, the maximum resolution is 1 tCC. 1) Staggered mode is compatible with the CAPCOM units of previous 16-bit controllers. User's Manual CC12_X8, V2.1 17-2 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Figure 17-2 shows the basic structure of a CAPCOM unit. Capture/Compare Unit 2 T78CON.T7RS EL Reload Reg. T7REL External Sync. S tart fCC T7IN T6OUF CCxIO CCxIO T7 Input Control Timer T7 T7IRQ CCxIRQ CCxIRQ Mode Control (Capture or Compare) S ixteen 16-bit Capture/ Compare Registers CCxIO CCxIRQ fCC T6OUF External Sync. S tart T8 Input Control Timer T8 T8IRQ T78CON.T8RS EL S YSCON1.GLCCS T Reload Reg. T8REL CAPCOM2 provides channels x = 16 ... 31. (see signals CCxIO and CCxIRQ) MCB05418_P11_CC2 Figure 17-2 CAPCOM Unit Block Diagram There is a possibility to start both timers T7 and T8 synchronously with the CAPCOM6 timers, by seting the bit in the SYSCON1.GLCCST module. User's Manual CC12_X8, V2.1 17-3 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 2 17.1 The CAPCOM2 Timers The primary use of the timers T7 and T8 is to provide two independent time bases for the capture/compare channels of each unit. The maximum resolution is 8 tCC in staggered mode, and 1 tCC in non-staggered mode. The basic structure of the two timers, illustrated in Figure 17-3, is identical, except for the input pin (see mark). Reload Reg. TxREL fCC Prescaler f Tx TxM TxI T6OUF MUX Count Timer Tx TxIRQ Edge TxI TxR TxIN Select to Capure/Compare Register Array TxI x = 7, 8 MCB05419_4CM_CC2 Figure 17-3 Block Diagram of a CAPCOM Timer The functions of the CAPCOM timers are controlled via the bit-addressable control register T78CON. The high-byte of T78CON controls T8, the low-byte of T78CON controls T7. The control options are identical for all four timers (except for external input). In all modes, the timers are always counting upward. The current timer values are accessible for the CPU in the timer registers Tx, which are non bit-addressable registers. When the CPU writes to a register Tx in the state immediately before the respective timer increment or reload is to be performed, the CPU write operation has priority and the increment or reload is disabled to guarantee correct timer operation. User's Manual CC12_X8, V2.1 17-4 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary CC2_T78CON Timer 7/8 Control Register 15 14 T8R rw 13 12 11 T8M rw 10 Capture/Compare Unit 2 SFR (FF20H/90H) 9 T8I rw 8 7 6 T7R rw 5 4 Reset Value: 0000H 3 T7M rw 2 1 T7I rw 0 T8RSEL - T7RSEL - Field TxR Bits 14, 6 Type rw Description Timer/Counter Tx Run Control 0 Timer/Counter Tx is disabled 1 Timer/Counter Tx is enabled Timer/Counter Tx Mode Selection 0 Timer Mode 1 Counter Mode Timer/Counter Tx Input Selection Timer Mode (TxM = 0): Input frequency fTx = fCC/2( TxM 11, 3 rw TxI [10:8], [2:0] rw T7RSEL [5:4] rw Timer T7 External Run Selection Bit field T7RSEL defines the event of signal T7HR that can set the run bit T7R by HW. 00 The external setting of T7R is disabled. 01 Bit T7R is set if a rising edge of signal T7HR is detected. 10 Bit T7R is set if a falling edge of signal T7HR is detected. 11 Bit T7R is set if an edge of signal T7HR is detected. User's Manual CC12_X8, V2.1 17-5 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field T8RSEL Bits Type Description Timer T8 External Run Selection Bit field T8RSEL defines the event of signal T8HR that can set the run bit T8R by HW. 00 The external setting of T8R is disabled. 01 Bit T8R is set if a rising edge of signal T8HR is detected. 10 Bit T8R is set if a falling edge of signal T8HR is detected. 11 Bit T8R is set if an edge of signal T8HR is detected. Capture/Compare Unit 2 [13:12] rw The timer run flags TxR allow the starting and stopping of the timers. The following description of the timer modes and operation always applies to the enabled state of the timers, i.e. the respective run flag is assumed to be set. Timer Mode In Timer Mode (TxM = 0), the input clock for a CAPCOM2 timer is derived from fCC, divided by a programmable prescaler. Each timer has its own individual prescaler, controlled through the individual bitfields TxI in the timer control registers T01CON and T78CON. The input frequency fTx for a timer Tx and its resolution rTx are determined by the following formulas: Staggered Mode: f CC [ MHz ] f Tx [ MHz ] = ------------------------( 2 Non-Staggered Mode: r Tx [ s ] = ------------------------f CC [ MHz ] 2 ( (17.1) When a timer overflows from FFFFH to 0000H, it is reloaded with the value stored in its respective reload register TxREL. The reload value determines the period PTx between two consecutive overflows of Tx as follows: f CC [ MHz ] f Tx [ MHz ] = ------------------------ 2 Staggered Mode: r Tx [ s ] = ------------------------f CC [ MHz ] 2 (17.2) ( 2 - User's Manual CC12_X8, V2.1 16 ( (17.3) 17-6 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Non-Staggered Mode: ( 2 - 16 Capture/Compare Unit 2 (17.4) After a timer has been started by setting its run flag (TxR), the first increment will occur within the time interval which is defined by the selected timer resolution. All further increments occur exactly after the time defined by the timer resolution. Examples for timer input frequencies, resolution and periods, which result from the selected prescaler option in TxI when using a 40 MHz clock, are listed in Table 17-1 below. The numbers for the timer periods are based on a reload value of 0000H. Note that some numbers may be rounded. User's Manual CC12_X8, V2.1 17-7 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Table 17-1 TxI Capture/Compare Unit 2 Timer Tx Input Clock Selection for Timer Mode, fCC = 40 MHz Prescaler Input Frequency 5 MHz 2.5 MHz 1.25 MHz 625 kHz 312.5 kHz 156.25 kHz 78.125 kHz 39.0625 kHz 40 MHz 20 MHz 10 MHz 5 MHz 2.5 MHz 1.25 MHz 625 kHz 312.5 kHz Resolution Period Non-Staggered Mode 000B 001B 010B 011B 100B 101B 110B 111B 000B 001B 010B 011B 100B 101B 110B 111B 8 16 32 64 128 256 512 1024 1 2 4 8 16 32 64 128 200 ns 400 ns 800 ns 1.6 s 3.2 s 6.4 s 12.8 s 25.6 s 25 ns 50 ns 100 ns 200 ns 400 ns 800 ns 1.6 s 3.2 s 13.11 ms 26.21 ms 52.43 ms 104.86 ms 209.72 ms 419.43 ms 838.86 ms 1677.72 ms 1.6384 ms 3.2768 ms 6.5536 ms 13.11 ms 26.21 ms 52.43 ms 104.86 ms 209.72 ms Non-Staggered Mode User's Manual CC12_X8, V2.1 17-8 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Counter Mode In Counter Mode (TxM = 1), the input clock of a CAPCOM2 timer is either derived from an associated external input pin, T7IN, or from the over-/underflows of GPT timer T6. Using an external signal connected to pin TxIN as a counting signal is only possible for timer T7. The only counter option for timer T8 is using the over-/underflows of the GPT timer T6 (selected by TxI = 000B). Bitfields T7I are used to select either a positive, a negative, or both a positive and a negative transition of the external signal at pin T7IN to trigger an increment of timer T7. Please note that certain criteria must be met for the external signal and the port pin programming for this mode in order to operate properly. These conditions are detailed in Chapter 17.10. Timer Overflow and Reload When a CAPCOM2 timer contains the value FFFFH at the time a new count trigger occurs, a timer interrupt request is generated, and the timer is loaded with the contents of its associated reload register TxREL. The timer then resumes incrementing with the next count trigger starting from the reloaded value. The reload registers TxREL are not bitaddressable. After reset, they contain the value 0000H. Capture/Compare Unit 2 User's Manual CC12_X8, V2.1 17-9 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 2 17.2 CAPCOM2 Timer Interrupts Upon a timer overflow the corresponding timer interrupt request flag TxIR for the respective timer will be set. This flag can be used to generate an interrupt or trigger a PEC service request, when enabled by the respective interrupt enable bit TxIE. Each timer has its own bitaddressable interrupt control register and its own interrupt vector. The organization of the interrupt control registers TxIC is identical with the other interrupt control registers. CC2_T7IC CAPCOM T7 Intr. Ctrl. Reg. 15 14 13 12 11 10 ESFR (FF6CH/BDH) 9 8 7 6 5 4 Reset Value: - - 00H 3 2 1 0 GPX T7IR T7IE rw rwh rw ILVL rw GLVL rw CC2_T8IC CAPCOM T8 Intr. Ctrl. Reg. 15 14 13 12 11 10 ESFR (FF6EH/BEH) 9 8 7 6 5 4 Reset Value: - - 00H 3 2 1 0 GPX T8IR T8IE rw rwh rw ILVL rw GLVL rw Note: Please refer to the general Interrupt Control Register description for an explanation of the control fields. User's Manual CC12_X8, V2.1 17-10 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 2 17.3 Capture/Compare Channels The 16-bit capture/compare registers CC0 through CC15 (CC16 through CC31) are used as data registers for capture or compare operations with respect to timers T0/T7 and T1/T8. The capture/compare registers are not bit-addressable. The functions of the 16 capture/compare registers of a unit are controlled by 4 bitaddressable 16-bit mode control registers, named CC1_M0 ... CC1_M3 (CC2_M4 ... CC2_M7), which are all organized identically (see description below). Each register contains the bits for mode selection and timer allocation for four capture/comp. registers. TBD RegisterAdressSpace 17.3.1 Capture/Compare Registers for the CAPCOM2 (CC31 ... CC16) CC2_M4 CAPCOM Mode Ctrl. Reg. 4 15 ACC 19 rw 14 13 MOD19 rw 12 11 ACC 18 rw 10 SFR (FF22H/91H) 9 MOD18 rw 8 7 ACC 17 rw 6 5 MOD17 rw 4 Reset Value: 0000H 3 ACC 16 rw 2 1 MOD16 rw 0 CC2_M5 CAPCOM Mode Ctrl. Reg. 5 15 ACC 23 rw 14 13 MOD23 rw 12 11 ACC 22 rw 10 SFR (FF24H/92H) 9 MOD22 rw 8 7 ACC 21 rw 6 5 MOD21 rw 4 Reset Value: 0000H 3 ACC 20 rw 2 1 MOD20 rw 0 CC2_M6 CAPCOM Mode Ctrl. Reg. 6 15 ACC 27 rw 14 13 MOD27 rw 12 11 ACC 26 rw 10 SFR (FF26H/93H) 9 MOD26 rw 8 7 ACC 25 rw 6 5 MOD25 rw 4 Reset Value: 0000H 3 ACC 24 rw 2 1 MOD24 rw 0 User's Manual CC12_X8, V2.1 17-11 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary CC2_M7 CAPCOM Mode Ctrl. Reg. 7 15 ACC 31 rw 14 13 MOD31 rw 12 11 ACC 30 rw 10 Capture/Compare Unit 2 SFR (FF28H/94H) 9 MOD30 rw 8 7 ACC 29 rw 6 5 MOD29 rw 4 Reset Value: 0000H 3 ACC 28 rw 2 1 MOD28 rw 0 Field ACCy Bits 15, 11, 7, 3 [14:12], [10:8], [6:4], [2:0] Type rw Description Allocation Bit for CAPCOM Register CCy 0 CCy allocated to Timer T0 or T7, respectively 1 CCy allocated to Timer T1 or T8, respectively Mode Selection for CAPCOM Register CCy See Table 17-2. MODy rw Each of the registers CCy may be individually programmed for capture mode or for one of 4 different compare modes, and may be allocated individually to one of the two timers of the respective CAPCOM unit. A special double-register compare mode combines two registers to act on one common output signal. When capture or compare operations are disabled for one of the CCy registers, it may be used for general purpose variable storage. Table 17-2 Mode Disabled Selection of Capture Modes and Compare Modes MODy 000 Selected Operating Mode Disable Capture and Compare Modes The respective CAPCOM register may be used for general variable storage. Capture on Positive Transition (Rising Edge) at Pin CCyIO Capture on Negative Transition (Falling Edge) at Pin CCyIO Capture on Positive and Negative Transition (Both Edges) at Pin CCyIO Capture 001 010 011 User's Manual CC12_X8, V2.1 17-12 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Table 17-2 Mode Compare Capture/Compare Unit 2 Selection of Capture Modes and Compare Modes (cont'd) MODy 100 Selected Operating Mode Compare Mode 0: Interrupt Only Several interrupts per timer period. Can enable double-register compare mode for Bank2 registers. Compare Mode 1: Toggle Output Pin on each Match Several compare events per timer period. Can enable double-register compare mode for Bank1 registers. Compare Mode 2: Interrupt Only Only one interrupt per timer period. Compare Mode 3: Set Output Pin on each Match Reset output pin on each timer overflow; only one interrupt per timer period. 101 110 111 The detailed discussion of the capture and compare modes is valid for all the capture/compare channels, so registers, bits and pins are only referenced by a placeholder. Note: A capture or compare event on channel 31 may be used to trigger a channel injection on the XC2000's A/D converter if enabled. User's Manual CC12_X8, V2.1 17-13 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 2 17.4 Capture Mode Operation In Capture Mode, the current contents of a CAPCOM timer are latched (captured) into the respective capture/compare register in response to an external event. This is used, for example, to record the time at which an external event has occurred, or to measure the distance between two external events in timer increments. The event to cause a capture of a timer's contents can be programmed to be either the positive, the negative, or both the positive and the negative transition of the external signal connected to the input pin. This triggering transition is selected by bitfield MODy in the respective mode control register. When the selected external signal transition occurs, the selected timer's contents is latched into the capture/compare register and the respective interrupt request line CCyIRQ is activated. This can cause an interrupt or PEC service request, when enabled. Note: A capture input can be used as an additional external interrupt input. The capture operation can be disregarded in this case. Either the contents of timer T0/T7 or T1/T8 can be captured, selected by the timer allocation control bit ACCy in the respective mode control register. Input Clock Interrupt Requests Timer T7 Timer T8 ACCy Edge CCyIO Select M UX CCyIRQ Capture Register CCy MODy MCB05420_4CM_CC2 Figure 17-4 Capture Mode Block Diagram For capture operation, the respective pin must be programmed for input. To ensure that a transition of the input signal is recognized correctly, its level must be held high or low for a minimum number of module clock cycles before it changes. This information can be found in Section 17.10. User's Manual CC12_X8, V2.1 17-14 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 2 17.5 Compare Mode Operation The compare modes allow triggering of events (interrupts and/or output signal transitions) or generation of pulse trains with minimum software overhead. In all compare modes, the 16-bit value stored in a capture/compare register CCy (in the following also referred to as `compare value') is continuously compared with the contents of the allocated timer (T7 or T8). If the current timer contents match the compare value, the interrupt request line associated with register CCy is activated and, depending on the compare mode, an output signal can be generated at the corresponding output pin CCyIO. Four different compare modes are available, which can be selected individually for each of the capture/compare registers by bitfield MODy in the respective mode control register. Modes 0 and 2 do not influence the output signals. In the following, each mode is described in detail. In addition to these `single-register' modes, a `double-register' compare mode enables two registers to operate on the same pin. This feature can further reduce software overhead, as two different compare values can be programmed to control a sequence of transitions for a signal. See Section 17.5.5 for details for this operation. In all Compare Modes, the comparator performs an `equal to' comparison. This means, a match is only detected when the timer contents are equal to the contents of a compare register. In addition, the comparator is only enabled in the clock cycle directly after the timer was incremented by hardware. This is done to prevent repeated matches if the timer does not operate with the highest possible input clock (either in timer or counter mode). In this case, the timer contents would remain at the same value for several or up to thousands of cycles. This operation has the side-effect, that software modifications of the timer contents will have no effect regarding the comparator. If a timer is set by software to the same value stored in one of the compare registers, no match will be detected. If a compare register is set to a value smaller than the current timer contents, no action will take place. For the exact operation of the port output function, please see Section 17.6. When two or more compare registers are programmed to the same compare value1), their corresponding interrupt request flags will be set and the selected output signals will be generated after the allocated timer is incremented to this compare value. Further compare events on the same compare value are disabled2) until the timer is incremented again or written to by software. After a reset, compare events for register CCy will only become enabled, if the allocated timer has been incremented or written to by software and one of the compare modes described in the following has been selected for this register. 1) In staggered mode these interrupts and output signals are generated sequentially (see Section 17.8). 2) Even if more compare cycles are executed before the timer increments (lower timer frequency) a given compare value only results in one single compare event. User's Manual CC12_X8, V2.1 17-15 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 2 17.5.1 Compare Mode 0 This is an interrupt-only mode which can be used for software timing purposes. In this mode, the interrupt request line CCyIRQ is activated each time a match is detected between the contents of the compare register CCy and the allocated timer. A match means, the contents of the timer are equal to (`=') the contents of the compare register. Several of these compare events are possible within a single timer period, if the compare value in register CCy is updated during the timer period. The corresponding port signal CCyIO is not affected by compare events in this mode and can be used as general purpose IO. Note: If compare mode 0 is programmed for one of the bank2 registers the doubleregister compare mode may be enabled for this register (see Chapter 17.5.5). 17.5.2 Compare Mode 1 This is a compare mode which influences the associated output signal. Besides this, the basic operation is as in compare mode 0. Each time a match is detected between the contents of the compare register CCy and the allocated timer, the interrupt request line CCyIRQ is activated. In addition, the associated output signal is toggled. Several of these compare events are possible within a single timer period, if the compare value in register CCy is updated during the timer period. Note: If compare mode 1 is programmed for one of the bank1 registers the doubleregister compare mode may be enabled for this register (see Section 17.5.5). For the exact operation of the port output signal, please see Section 17.6. User's Manual CC12_X8, V2.1 17-16 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 2 Timer T7 Timer T8 T8IRQ T7IRQ ACCy M UX Mode 1 only! Mode & Output Ctrl. MODy Mode Control Comparator =? to Port Logic CCyIRQ SEEy SEMy Compare Register CCy MCB05421_4CM Figure 17-5 Compare Mode 0 and 1 Block Diagram Note: The signal remains unaffected in compare mode 0. Figure 17-6 illustrates a few example cases for compare modes 0 and 1. In all examples, the reload value of the used timer is set to FFF9H. When the timer overflows, it starts counting from this value upwards. In Case 1, register CCy contains the value FFFCH. When the timer reaches this value, a match is detected, and the interrupt request line CCyIRQ is activated. In compare mode 0, this is all that will happen. In compare mode 1, additionally the associated port output is toggled, causing an inversion of the output signal. If the contents of register CCy are not changed, this operation will take place each time the timer reaches the programmed compare value. In Case 2, software reloads the compare register CCy with FFFFH after the first match with FFFCH has occurred. As the timer continues to count up, it finally reaches this new compare value, and a new match is detected, activating the interrupt request line (both modes) and toggling the output signal (compare mode 1). If then the compare value is left unchanged, the next match will occur when the timer reaches FFFFH again. This example illustrates, that further compare matches are possible within the current timer period (this is in contrast to compare modes 2 and 3). User's Manual CC12_X8, V2.1 17-17 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 2 Timer Contents FFFF FFFE FFFD FFFC FFFB FFFA FFF9 Reload Value = FFF9 FFF9 FFFA FFFC FFFB FFFD FFFE FFFF CCxIO Case 1 CC16 = FFFF CCxIO Case 2 CC16 = FFFA CCxIO Case 3 CC16 = FFF9 CCxIO Case 4 Symbolizes activation of the interrupt request line CCyIRQ MCT05422_4CM CC16 = FFFD CC16 = FFFC CC16 = FFFA CC16 = FFFC CC16 = FFFF CC16 = FFFB Figure 17-6 Examples for Compare Modes 0 and 1 In Case 3, a new compare value, higher than the current timer contents, causes a new match within the current timer period. The compare register is reloaded with FFFAH after the first match (at FFFCH). However, the timer has already passed this value. Thus, it will take until the timer reaches FFFAH in the following timer period to cause the desired compare match. Reloading register CCy now with a value higher than the current timer contents will cause the next match within this period. In Case 4, the compare values are equal to the timer reload value or to the maximum count value, FFFFH. User's Manual CC12_X8, V2.1 17-18 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 2 17.5.3 Compare Mode 2 Compare mode 2 is an interrupt-only mode similar to compare mode 0. The main difference is that only one compare match, corresponding to one interrupt request, is possible within a given timer period. When a match is detected in compare mode 2 for the first time within a count period of the allocated timer, the interrupt request line CCyIRQ is activated. In addition, all further compare matches within the current timer period are disabled, even if a new compare value, higher than the current timer contents, would be written to the register. This blocking is only released when the allocated timer overflows. A new compare value written to the compare register after the first match will only go into effect within the following timer period. 17.5.4 Compare Mode 3 Compare mode 3 is based on compare mode 2, but additionally influences the associated port pin. Only one compare event is possible within one timer period. When a match is detected in compare mode 3 for the first time within a count period of the allocated timer, the interrupt request line CCyIRQ is activated, and the associated output signal is set to 1. In addition, all further compare matches within the current timer period are disabled, even if a new compare value, higher than the current timer contents, would be written to the register. This blocking is only released when the allocated timer overflows. A new compare value written to the compare register after the first match will only go into effect within the following timer period. The overflow signal is also used to reset the associated output signal to 0. Special attention has to be paid when the compare value is set equal to the timer reload value. In this case, the compare match signal would try to set the output signal, while the timer overflow tries to reset the output signal. This conflict is avoided such that the state of the output signal is left unchanged in this case. Note: When the compare value is changed from a value above the current timer contents to a value below the current timer contents, the new value is not recognized before the next timer period. For the exact operation of the port output signal, please see Section 17.6. User's Manual CC12_X8, V2.1 17-19 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 2 Timer T7 Timer T8 T8IRQ T7IRQ M UX ACCy M UX ACCy Mode 3 only! Mode & Output Ctrl. MODy Mode Control Comparator =? to Port Logic CCyIRQ SEEy SEMy Compare Register CCy MCB05423_4CM Figure 17-7 Compare Mode 2 and 3 Block Diagram Note: The port latch and signal remain unaffected in compare mode 2. Figure 17-8 illustrates a few timing examples for compare modes 2 and 3. In all examples, the reload value of the used timer is set to FFF9H. When the timer overflows, it starts counting from this value upwards. In Case 1, register CCy contains the value FFFCH. When the timer reaches this value, a match is detected, and the interrupt request line CCyIRQ is activated. In compare mode 2, this is all that will happen. In compare mode 3, additionally the associated port output is set to 1. The timer continues to count, and finally reaches its overflow. At this point, the port output is reset to 0 again. Note that, although not shown in the diagrams, the overflow signal of the timer also activates the associated interrupt request line TxIRQ. If the contents of register CCy are not changed, the port output will be set again during the following timer period, and reset again when the timer overflows. This operation is ideal for the generation of a pulse width modulated (PWM) signal with a minimum of software overhead. The pulse width is varied by changing the compare value accordingly. In Case 2, the compare operation is blocked after the first match within a timer period. After the first match at FFFCH, the interrupt request is generated and the port output is set. In addition, further compare matches are disabled. If now a new compare value is written to register CCy, no interrupt request and no port output influence will take place, although the new compare value is higher than the current timer contents. Only after the overflow of the timer, the compare logic is enabled again, and the next match will be User's Manual CC12_X8, V2.1 17-20 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 2 detected at FFFFH. One can see, that this operation is ideal for PWM generation, as software can write a new compare value regardless of whether this value is higher or lower than the current timer contents. It is assured that the new value (usually written to the compare register in the appropriate interrupt service routine) will only go into effect during the following timer period. Timer Contents FFFF FFFE FFFD FFFC FFFB FFFA FFF9 Reload Value = FFF9 FFF9 FFFA FFFC FFFB FFFD FFFE FFFF CCxIO Case 1 CC16 = FFFF CCxIO Case 2 CC16 = FFFA CCxIO Case 3 CC16 = FFFA CCxIO Case 4 MCT05424_4CM CC16 = FFFC CC16 = FFFC Figure 17-8 Timing Example for Compare Modes 2 and 3 Note: In compare mode 2, only interrupt requests are generated, in mode 3, also the output signals are generated. In Case 3, further examples for the operation of the compare match blocking are illustrated. In Case 4, a new compare value is written to a compare register before the first match within the timer period. One can see that, of course, the originally programmed compare match (at FFFAH) will not take place. The first match will be detected at FFFCH. However, it is important to note that the reprogramming of the compare register took place asynchronously - this means, the register was written to without any regard to the current contents of the timer. This is dangerous in the sense that the effect of such an asynchronous reprogramming is not easily predictable. If the timer would have already reached the originally programmed compare value of FFFAH by the time the software User's Manual CC12_X8, V2.1 17-21 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 2 wrote to the register, a match would have been detected and the reprogramming would go into effect during the next timer period. The examples in Figure 17-9 show special cases for compare modes 2 and 3. Case 1 illustrates the effect when the compare value is equal to the reload value of the timer. An interrupt is generated in both modes. In mode 3, the output signal is not affected - it remains at the high level. Setting the compare value equal to the reload value easily enables a 100% duty cycle signal for PWM generation. The important advantage here is that the compare interrupt is still generated and can be used to reload the next compare value. Thus, no special treatment is required for this case (see Case 3). Cases 2, 4, and 5 show different options for the generation of a 0% duty cycle signal. Case 2 shows an asynchronous reprogramming of the compare value equal to the reload value. At the end of the current timer period, a compare interrupt will be generated, which enables software to set the next compare value. The disadvantage of this method is that at least two timer periods will pass until a new regular compare value can go into effect. The compare match with the reload value FFF9H will block further compare matches during that timer period. This is additionally illustrated by Case 4. Timer Contents FFFF FFFE FFFD FFFC FFFB FFFA FFF9 Reload Value = FFF9 Int. CCxIO Case 1 Int. CC16 = FFF9 CCxIO Case 2 Int. CCxIO Case 3 Int. CC16 = FFF9 CCxIO Case 4 Int. CCxIO Case 5 MCT05425_4CM FFFF FFFE FFFD FFFC FFFB FFFA FFF9 CC16 = FFF9 Int. Int. Int. CC16 = FFF9 Int. CC16 = FFFB Int. No CC16 = Comp. FFFC CC16 = FFF8 CC16 = FFFC Int. Figure 17-9 Special Cases in Compare Modes 2 and 3 User's Manual CC12_X8, V2.1 17-22 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 2 Case 5 shows an option to get around this problem. Here, the compare register is reloaded with FFF8H, a value which is lower than the timer reload value. Thus, the timer will never reach this value, and no compare match will be detected. The output signal will be set to 0 after the first timer overflow. However, after the second overflow, software now reloads the compare register with a regular compare value. As no compare blocking has taken place (since there was no compare match), the newly written compare value will go into effect during the current timer period. User's Manual CC12_X8, V2.1 17-23 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 2 17.5.5 Double-Register Compare Mode The Double-Register Compare Mode makes it possible to further reduce software overhead for a number of applications. In this mode, two compare registers work together to control one output. This mode is selected via the DRM register, or by a special combination of compare modes for the two registers. For double-register compare mode, the 16 capture/compare registers of a CAPCOM2 unit are regarded as two banks of 8 registers each. The lower eight registers form bank1, while the upper eight registers form bank2. For double-register mode, a bank1 register and a bank2 register form a register pair. Both registers of this register pair operate on the pin associated with the bank1 register. The relationship between the bank1 and bank2 register of a pair and the effected output pins for double-register compare mode is listed in Table 17-3. Table 17-3 Register Pairs for Double-Register Compare Mode CAPCOM2 Unit Register Pair Bank 1 CC16 CC17 CC18 CC19 CC20 CC21 CC22 CC23 Bank 2 CC24 CC25 CC26 CC27 CC28 CC29 CC30 CC31 CC16IO CC17IO CC18IO CC19IO CC20IO CC21IO CC22IO CC23IO Used Output Pin Control Bitfield in CC2DRM DR0M DR1M DR2M DR3M DR4M DR5M DR6M DR7M The double-register compare mode can be programmed individually for each register pair. Double-register compare mode can be selected via a certain combination of compare modes for the two registers of a pair. The bank1 register must be programmed for mode 1 (with port influence), while the bank2 register must be programmed for mode 0 (interrupt-only). User's Manual CC12_X8, V2.1 17-24 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 2 Double-register compare mode can be controlled (this means, enabled or disabled) for each register pair via the associated control bitfield DRxM in register CC2_DRM. CC2_DRM Double-Reg. Cmp. Mode Reg. 15 14 13 12 11 10 SFR (FF2AH/95H) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 DR7M rw DR6M rw DR5M rw DR4M rw DR3M rw DR2M rw DR1M rw DR0M rw Field DRxM Bits [1:0], [3:2], [5:4], [7:6], [9:8], [11:10], [13:12], [15:14] Type rw Description Double Register x Compare Mode Selection 00 DRM is controlled via the combination of compare modes 1 and 0 (compatibility mode) 01 DRM disabled regardless of compare modes 10 DRM enabled regardless of compare modes 11 Reserved Note: "x" indicates the register pair index in a bank. Double-register compare mode can be controlled individually for each of the register pairs. In the block diagram of the double-register compare mode (Figure 17-10), a bank2 register will be referred to as CCz, while the corresponding bank1 register will be referred to as CCy. User's Manual CC12_X8, V2.1 17-25 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 2 Timer T7 Timer T8 M UX ACCy M UX ACCz DRyM MODy Mode Control Comp. =? Mode & Output Ctrl. Comparator =? CCyIRQ SEEy SEMy to Port Logic DRyM MODz Mode Control CCzIRQ SEEz SEMz Compare Register CCy Compare Register CCz z=y+8 MCB05426_4CM Figure 17-10 Double-Register Compare Mode Block Diagram When a match is detected for one of the two registers in a register pair (CCy or CCz), the associated interrupt request line (CCyIRQ or CCzIRQ) is activated, and pin CCyIO, corresponding to the bank1 register CCy, is toggled. The generated interrupt always corresponds to the register that caused the match. Note: If a match occurs simultaneously for both register CCy and register CCz of the register pair, pin CCyIO will be toggled only once, but two separate compare interrupt requests will be generated. Each of the two registers of a pair can be individually allocated to one of the two timers in the CAPCOM2 unit. This offers a wide variety of applications, as the two timers can run in different modes with different resolution and frequency. However, this might require sophisticated software algorithms to handle the different timer periods. Note: The signals CCzIO (which do not serve for double-register compare mode) may be used for general purpose IO. User's Manual CC12_X8, V2.1 17-26 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 2 17.6 Compare Output Signal Generation This section discusses the interaction between the CAPCOM Unit and the Port Logic. The block diagram illustrated in Figure 17-11 details the logic of the block "Mode & Output Control", shown in Figure 17-5, Figure 17-7, and Figure 17-10. Each output signal is latched in its associated bit of the respective output latch register CCx_OUT. The individual bits are updated each time an associated compare event occurs. The bits of these registers are connected to the respective port pins as an alternate output function of a port line. Compare signals can also directly affect the associated port output latch Px. In this case, the port latch must be selected for the respective pin. The direct port latch option is disabled in non-staggered mode or it can be disabled by setting bit PL in register CCx_IOC. Register CCx_OUT is always updated in parallel to the update of the port output latch. CC2_OUT Compare Output Reg. 15 CC 15 IO rwh 14 CC 14 IO rwh 13 CC 13 IO rwh 12 CC 12 IO rwh 11 CC 11 IO rwh 10 SFR (FF2CH/96H) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 CC CC9 CC8 CC7 CC6 CC5 CC4 CC3 CC2 CC1 CC0 10 IO IO IO IO IO IO IO IO IO IO IO rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh Field CCyIO Bits Type Description Compare Output for Channel y Alternative port output for the associated port pin. 15 ... 0 rwh User's Manual CC12_X8, V2.1 17-27 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 2 STAG PL Compare Match TxOV Output Value Control _ >1 & Port Latch 0 OUT Latch 1 MUX Driver Port Pin Pm.n MODy ALTSEL0Pn Direction CAPCOM Logic Port Logic MCB05427 Figure 17-11 Port Output Block Diagram for Compare Modes Note: A compare output signal is visible at the pin only in compare modes 1 or 3. The output signal of a compare event can either be a 1, a 0, the complement of the current level, or the previous level. The block `Output Value Control' determines the correct new level based on the compare event, the timer overflow signal, and the current states of the Port and OUT latches. For the output toggle function (e.g. in compare mode 1), the state of the output latch is read, inverted, and then written back. The associated output pins either drives the port latch signal or the OUT signal, selected by register ALTSEL (see Figure 17-11). Note: If the port output latch is written to by software at the same time it would be altered by a compare event, the software write will have priority. In this case the hardwaretriggered change will not become effective. User's Manual CC12_X8, V2.1 17-28 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 2 17.7 Single Event Operation If an application requires that one and only one compare event needs to take place (within a certain time frame), single event operation helps to reduce software overhead and to eliminate the need for fast reaction upon events. In order to achieve a single event operation without this feature, software would have to either disable the compare mode or write a new value, which is outside of the count range of the timer, into the compare register, after the programmed compare match has taken place. Thus, usually an interrupt service routine is required to perform this operation. Interrupt response time may be critical if the timer period is very short - the disable operation needs to be completed before the timer would reach the same value again. The single event operation eliminates the need for software to react after the first compare match. The complete operation can be set up before the event, and no action is required after the event. The hardware takes care of generating only one event, and then disabling all further compare matches. This option is programmed via the Single Event Mode register CC2_SEM and the Single Event Enable register CC2_SEE. Each register provides one bit for each CCy register of a unit. CC2_SEM Single Event Mode Ctrl. Reg. 15 14 13 12 11 10 SFR (FE28H/14H) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 SEM SEM SEM SEM SEM SEM SEM SEM SEM SEM SEM SEM SEM SEM SEM SEM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Field SEMy Bits 15 ... 0 Type rw Description Single Event Mode Control 0 Single Event Mode disabled for channel y 1 Single Event Mode enabled for channel y CC2_SEE Single Event Enable Reg. 15 14 13 12 11 10 SFR (FE2AH/15H) 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 SEE SEE SEE SEE SEE SEE SEE SEE SEE SEE SEE SEE SEE SEE SEE SEE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh User's Manual CC12_X8, V2.1 17-29 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 2 Field SEEy Bits 15 ... 0 Type rw Description Single Event Enable Control 0 Single Event disabled for channel y 1 Single Event enabled for channel y Note: This bit is cleared by hardware after the event. To setup a single event operation for a CCy register, software first programs the desired compare operation and compare value, and then sets the respective bit in register CC2_SEM to enable the single event mode. At last, the respective event enable bit in register CC2_SEE is set. When the programmed compare match occurs, all operations of the selected compare mode take place. In addition, hardware automatically disables all further compare matches and reset the event enable bit in register CC2_SEE to 0. As long as this bit is cleared, any compare operation is disabled. To setup a new event, this bit must first be set again. User's Manual CC12_X8, V2.1 17-30 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 2 17.8 Staggered and Non-Staggered Operation The CAPCOM2 units can run in one of two basic operation modes: Staggered Mode and Non-Staggered Mode. The selection between these modes is performed via register IOC. CC2_IOC I/O Control Register 15 14 13 12 11 10 - ESFR (F066H/33H) 9 8 7 6 5 4 Reset Value: 0000H 3 2 ST AG rw 1 PL rw 0 - Field STAG Bits 2 Type rw Description Staggered Mode Control 0 CAPCOM operates in Staggered Mode 1 CAPCOM operates in Non-Staggered Mode Port Lock Control 0 Compare output signals affect the associated port output latch 1 Direct influence of the port output latch by the compare output signals is disabled PL 1 rw Note: Whenever Non-Staggered Mode is enabled (STAG = 1) or Port Lock is activated (PL = 1), the port output registers are not changed by the CAPCOM unit. In staggered mode, a CAPCOM2 operation cycle consists of 8 module clock cycles, and the outputs of the compare events of the different registers are staggered, that is, the outputs for compare matches with the same compare value are not switched at the same time, but with a fixed time delay. This operation helps to reduce noise and peak power consumption caused by simultaneous switching outputs. In non-staggered Mode, a CAPCOM2 operation cycle is equal to one module clock cycle, and all compare outputs for compare events with the same compare value are switched in the same clock cycle. This mode offers a faster operation and increased resolution of the CAPCOM2 unit, 8 times higher than in staggered mode. User's Manual CC12_X8, V2.1 17-31 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Staggered Mode Figure 17-12 illustrates the staggered mode operation. In this example, all CCy registers are programmed for compare mode 3. Registers CC16, CC17, and CC18 are all programmed for a compare value of FFFEH. When the timer increments to FFFEH, the comparator detects a match for all of the three registers. The output CC16IO of register CC16 is switched to 1 one cycle after the comparator match. However, the outputs CC17IO and CC18IO are not switched at the same time, but one, respectively two cycles later. This staggering of the outputs continues for all registers including register CC23. The number of the register indicates the delay of the output signal in clock cycles - the output of register CC23 is switched 7 cycles later than the one of register CC16. In the example, the compare value for register CC13 is set to FFFDH. Thus, the output is switched in the last clock cycle of the CAPCOM2 cycle in which the timer reached FFFDH. When the timer overflows, all compare outputs are reset to 0 (compare mode 3). Again, the staggering of the output signals can be seen from Figure 17-12. Looking at registers CC24 through CC31 shows that their outputs are switched in parallel to the respective outputs of registers CC16 through CC23. In fact, the staggering is performed in parallel for the upper and the lower register bank. In this way, it is assured, that both compare signals of a register pair in double-register compare mode operate simultaneously. In staggered mode direct port latch switching (see Section 17.6) is possible. However, it is possible to use the alternate output function option of the associated port pins to output the compare signals. Note: This is a general description and only refers to channels connected to pins. Capture/Compare Unit 2 User's Manual CC12_X8, V2.1 17-32 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 2 Timer contents = FFFD Timer increments to FFFE Timer increments to FFFF Timer overflow Timer is reloaded with FFFC 1 CAPCOM Cycle = 8 fCC Clock Cycles CC16 = FFFE CC17 = FFFE CC18 = FFFE CC19 = FFFF CC20 = FFFE CC21 = FFFF CC22 = FFFF CC23 = FFFD CC24 = FFFE CC25 = FFFE CC26 = FFFE CC27 = FFFF CC28 = FFFE CC29 = FFFF CC30 = FFFF CC31 = FFFD 1 CAPCOM Cycle = 8 f CC Clock Cycles MCT05428_4CM Figure 17-12 Staggered Mode Operation User's Manual CC12_X8, V2.1 17-33 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Non-Staggered Mode To gain maximum speed and resolution with the CAPCOM2 unit, it can be switched to non-staggered mode. In this mode, one CAPCOM2 operation cycle is equal to one module clock cycle. Timer increment and the comparison of its new contents with the contents of the compare register takes place within one clock cycle. The appropriate output signals are switched in the following clock cycle (in parallel to the next possible timer increment and comparison). Figure 17-13 illustrates the non-staggered mode. Note that when the timer overflows, it also takes one additional clock cycle to switch the output signals. Note: In non-staggered mode, direct port latch switching is disabled. This is a general description and only refers to channels connected to pins. Capture/Compare Unit 2 User's Manual CC12_X8, V2.1 17-34 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 2 Timer contents = FFFD Timer increments to FFFE Timer increments to FFFF Timer overflow Timer is reloaded with FFFC 1 CAPCOM Cycle = 1 fCC Clock Cycle CC16 = FFFE CC17 = FFFE CC18 = FFFE CC19 = FFFF CC20 = FFFE CC21 = FFFF CC22 = FFFF CC23 = FFFD CC24 = FFFE CC25 = FFFE CC26 = FFFE CC27 = FFFF CC28 = FFFE CC29 = FFFF CC30 = FFFF CC31 = FFFD 1 CAPCOM Cycle = 1 f CC Clock Cycle MCT05429_4CM_CC2 Figure 17-13 Non-Staggered Mode Operation User's Manual CC12_X8, V2.1 17-35 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 2 17.9 CAPCOM2 Interrupts Upon a capture or compare event, the interrupt request flag CCyIR for the respective capture/compare register CCy is automatically set. This flag can be used to generate an interrupt or trigger a PEC service request when enabled by the interrupt enable bit CCyIE. Capture interrupts can be regarded as external interrupt requests with the additional feature of recording the time at which the triggering event occurred. Each of the capture/compare registers has its own bitaddressable interrupt control register and its own interrupt vector allocated. These registers are organized in the same way as all other interrupt control registers. The basic register layout is shown below, Table 17-4 lists the associated addresses. CC2_CCyIC CAPCOM Intr. Ctrl. Reg. 15 14 13 12 11 10 (E)SFR (Table 17-4) 9 8 GPX rw 7 6 5 4 Reset Value: - - 00H 3 2 1 0 CCy CCy IR IE rwh rw ILVL rw GLVL rw Note: Please refer to the general Interrupt Control Register description for an explanation of the control fields. User's Manual CC12_X8, V2.1 17-36 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Table 17-4 Capture/Compare Unit 2 CAPCOM Unit Interrupt Control Register Addresses CAPCOM2 Unit Register Name CC2_CC16IC CC2_CC17IC CC2_CC18IC CC2_CC19IC CC2_CC20IC CC2_CC21IC CC2_CC22IC CC2_CC23IC CC2_CC24IC CC2_CC25IC CC2_CC26IC CC2_CC27IC CC2_CC28IC CC2_CC29IC CC2_CC30IC CC2_CC31IC Address FE60H/30H FE62H/31H FE64H/32H FE66H/33H FE68H/34H FE6AH/35H FE6CH/36H FE6EH/37H FE70H/38H FE72H/39H FE74H/3AH FE76H/3BH FE78H/3CH FE7AH/3DH FE7CH/3EH FE7EH/3FH Reg. Space ESFR ESFR ESFR ESFR ESFR ESFR ESFR ESFR ESFR ESFR ESFR ESFR ESFR ESFR ESFR ESFR User's Manual CC12_X8, V2.1 17-37 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 2 17.10 External Input Signal Requirements The external input signals of a CAPCOM2 unit are sampled by the CAPCOM2 logic based on the module clock and the basic operation mode (staggered or non-staggered mode). To assure that a signal level is recognized correctly, its high or low level must be held active for at least one complete sampling period. The duration of a sampling period is one module clock cycle in non-staggered mode, and 8 module clock cycles in staggered mode. To recognize a signal transition, the signal needs to be sampled twice. If the level of the first sampling is different to the level detected during the second sampling, a transition is recognized. Therefore, a minimum of two sampling periods are required for the sampling of an external input signal. Thus, the maximum frequency of an input signal must not be higher than half the module clock frequency in non-staggered mode, and a 1/16th of the module clock frequency in staggered mode. Table 17-5 summarizes the requirements and limits for external input signals. Table 17-5 CAPCOM2 External Input Signal Limits Non-Staggered Mode Maximum Input Frequency Staggered Mode fCC/2 fCC/16 8/fCC Minimum Input Signal Level 1/fCC Duration In order to use an external signal as a count or capture input, the port pin to which it is connected must be configured as input. Note: For example for test purposes a pin used as a count or capture input may be configured as output. Software or an other peripheral may control the respective signal and thus trigger count or capture events. In order to cause a compare output signal to be seen by the external world, the associated port pin must be configured as output. Compare output signals can either directly switch the port latch, or the output of the CC2_OUT latch is used as an alternate output function of a port. User's Manual CC12_X8, V2.1 17-38 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 2 17.10.1 KSCCFG Register KSCCFG Kernel State Configuration Register SFR(FE24H) 15 BP COM w 14 0 r 13 12 11 BP SUM w 10 0 r 9 8 7 BP NOM w 6 0 r 5 4 Reset Value: 0000H 3 0 r 2 1 0 BP MOD MOD EN EN w rw COMCFG rw SUMCFG rw NOMCFG rw Field MODEN Bits 0 Type Description rw Module Enable This bit enables the module kernel clock and the module functionality. 0B The module is switched off. It does not react on mode control actions and the module clock is switched off immediately (without stop condition). The module does not react on read accesses and ignores write accesses. 1B The module is switched on. Note: This bit is reset by a class 3 reset. Bit Protection for MODEN This bit enables the write access to the bit MODEN. It always reads 0. It is only active during the write access cycle. 0B MODEN is not changed. 1B MODEN is updated with the written value. Note: This bit is reset by a class 3 reset. Normal Operation Mode Configuration This bit field defines the kernel mode applied in normal operation mode. 0XB The module is switched on. 1XB The module is switched off. This field is taken into account for CR = 00 or 11. Note: This bit is reset by a class 3 reset. BPMODE 1 w NOMCFG [5:4] rw User's Manual CC12_X8, V2.1 17-39 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field BPNOM Bits 7 Type Description w Bit Protection for NOMCFG This bit enables the write access to the bit field NOMCFG. It always reads 0. It is only active during the write access cycle. 0B NOMCFG is not changed. 1B NOMCFG is updated with the written value. Note: This bit is reset by a class 3 reset. SUMCFG [9:8] rw Suspend Mode Configuration This bit field defines the kernel mode applied in suspend mode. 0XB The module is switched on. 1XB The module is switched off. This field is taken into account for CR = 01. Note: This bit is reset by a class 1 reset. BPSUM 11 w Bit Protection for SUMCFG This bit enables the write access to the bit field SUMCFG. It always reads 0. It is only active during the write access cycle. SUMCFG is not changed. 0B 1B SUMCFG is updated with the written value. Note: This bit is reset by a class 1 reset. COMCFG [13:12] rw Clock Off Mode Configuration This bit field defines the kernel mode applied in clock off mode. 0XB The module is switched on. 1XB The module is switched off. This field is taken into account for CR = 10. Note: This bit is reset by a class 3 reset. BPCOM 15 w Bit Protection for COMCFG This bit enables the write access to the bit field COMCFG. It always reads 0. It is only active during the write access cycle. 0B COMCFG is not changed. 1B COMCFG is updated with the written value. Note: This bit is reset by a class 3 reset. 0 [3:2], 6, 10, 14 r Reserved; returns 0 if read; should be written with 0; Capture/Compare Unit 2 User's Manual CC12_X8, V2.1 17-40 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 2 17.11 Interfaces of the CAPCOM Units The CAPCOM2 unit (see Figure 17-14) are connected to their environment in different ways. Internal Connections The overflow/underflow signal T6OUF of GPT2 timer T6 is connected to the CAPCOM units, providing an optional clock source for the CAPCOM timers. The 18 interrupt request lines of the CAPCOM2 unit are connected to the interrupt control block. Note: The upper 6 input lines from PORT1, connected with the CAPCOM2 unit, can also be used as individual external interrupt inputs. The upper four channels are connected to the External Request Unit (ERU). The CAPCOM2 module is clocked with the XC2000 system clock, so fCC = fSYS. External Connections Twelve capture/compare signals of the CAPCOM2 unit are connected with input/output ports of the XC2000. Depending on the selected direction, these ports may provide capture trigger signals from the external system or issue compare output signals to external circuitry.. Note: Capture trigger signals may also be derived from output pins. In this case, software can generate the trigger edges, for example. Timer T7 can be clocked by an external signal. User's Manual CC12_X8, V2.1 17-41 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 2 fSYS = f CC S ystem Control Unit (SCU) CC2DIS GLCCS T T6OUF CC16IO CC17IO CC18IO CC19IO CC20IO P ort P 2 Control P 2.3/CC16IO P 2.4/CC17IO P 2.5/CC18IO P 2.6/CC19IO P 2.7/CC20IO P 2.8/CC21IO P 2.9/CC22IO GPT12 Unit T7IRQ T8IRQ CC16IRQ CC17IRQ CC18IRQ CC19IRQ CC20IRQ CC21IRQ CC22IRQ Interrupt Control CC23IRQ CC24IRQ CC25IRQ CC26IRQ CC27IRQ CC28IRQ CC29IRQ CC30IRQ CC31IRQ CAP COM2 Module CC21IO CC22IO CC23IO CC24IO CC25IO CC26IO CC27IO CC28IO CC29IO CC30IO CC31IO P ort P 4 Control P2.10/CC23IO P 4.0/CC24IO P 4.1/CC25IO P 4.2/CC26IO P 4.3/CC27IO P 4.4/CC28IO P 4.5/CC29IO P 4.6/CC30IO P 4.7/CC31IO T7IN P ort P 1 Control P5.9/T7IN ERU MCA05431_P11_CC2 Figure 17-14 CAPCOM2 Unit Interfaces User's Manual CC12_X8, V2.1 17-42 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18 Capture/Compare Unit 6 (CCU6) The CCU6 is a high-resolution 16-bit capture and compare unit with application specific modes, mainly for AC drive control. Special operating modes support the control of Brushless DC-motors using Hall sensors or Back-EMF detection. Furthermore, block commutation and control mechanisms for multi-phase machines are supported. It also supports inputs to start several timers synchronously, an important feature in devices with several CCU6 modules. This chapter is structured as follows: * * Introduction (see Section 18.1) including the register overview (see Section 18.1.3) Operating T12 (see Section 18.2) including T12 related registers (see Section 18.2.8) and capture/compare control registers (see Section 18.2.9) Operating T13 (see Section 18.3) including T13 related registers (see Section 18.3.6) Trap handling (see Section 18.4) Multi-Channel mode (see Section 18.5) Hall sensor mode (see Section 18.6) Modulation control registers (see Section 18.7) Interrupt handling (see Section 18.8) including interrupt registers (see Section 18.8.2) General module operation (see Section 18.9) including general registers (see Section 18.9.3) Module implementation (see Section 18.10) * * * * * * * * 18.1 Introduction The CCU6 unit is made up of a Timer T12 Block with three capture/compare channels and a Timer T13 Block with one compare channel. The T12 channels can independently generate PWM signals or accept capture triggers, or they can jointly generate control signal patterns to drive AC-motors or inverters. A rich set of status bits, synchronized updating of parameter values via shadow registers, and flexible generation of interrupt request signals provide means for efficient software-control. Note: The capture/compare module itself is named CCU6 (capture/compare unit 6). A capture/compare channel inside this module is named CC6x. User's Manual CCU6, UM_V0.5D3 18-1 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.1.1 Feature Set Overview This section gives an overview over the different building blocks and their main features. Timer 12 Block Features * * * * * * * * * * * Three capture/compare channels, each channel can be used either as capture or as compare channel Generation of a three-phase PWM supported (six outputs, individual signals for highside and low-side switches) 16-bit resolution, maximum count frequency = peripheral clock Dead-time control for each channel to avoid short-circuits in the power stage Concurrent update of T12 registers Center-aligned and edge-aligned PWM can be generated Single-shot mode supported Start can be controlled by external events Capability of counting external events Many interrupt request sources Hysteresis-like control mode Timer 13 Block Features * * * * * * * * One independent compare channel with one output 16-bit resolution, maximum count frequency = peripheral clock Concurrent update of T13 registers Can be synchronized to T12 Interrupt generation at period-match and compare-match Single-shot mode supported Start can be controlled by external events Capability of counting external events Additional Specific Functions * * * * * * * * Block commutation for Brushless DC-drives implemented Position detection via Hall-sensor pattern Noise filter supported for position input signals Automatic rotational speed measurement and commutation control for block commutation Integrated error handling Fast emergency stop without CPU load via external signal (CTRAP) Control modes for multi-channel AC-drives Output levels can be selected and adapted to the power stage User's Manual CCU6, UM_V0.5D3 18-2 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.1.2 Block Diagram The Timer T12 can work in capture and/or compare mode for its three channels. The modes can also be combined (e.g. a channel works in compare mode, whereas another channel works in capture mode). The Timer T13 can work in compare mode only. The multi-channel control unit generates output patterns which can be modulated by T12 and/or T13. The modulation sources can be selected and combined for the signal modulation. CCU6 Module Kernel Compare CC60 T12 CC61 CC62 Clock Control Start T13 Interrupt Control CC63 Compare SR[3:0] 1 3+3 22 2 1 1 1 Output Selec t Output Selec t Trap Input Hall Input Compare Compare Compare DeadTime Control Multichannel Control Trap Control fCC6 Capture 3 1 Input / Output Control CC POS0[D :A] CC POS1[D :A] CC POS2[D :A] C C61I N[D:A] C C60I N[D:A] C C62I N[D:A] C TR AP[D :A] T 12HR [D :A] T 13HR [D :A] COU T61 COU T60 COU T62 CC 60 CC 61 Port Control CC 62 CCU6_MCB05506 Figure 18-1 CCU6 Block Diagram User's Manual CCU6, UM_V0.5D3 18-3 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.1.3 Register Overview For the generation of the overall register table, the prefix "CCU6x_" has to be added to the register names in this table to identify the registers of different CCU6 modules that are implemented. In this naming convention, x indicates the module number. Table 18-1 shows all registers required for programming of a CCU6 module. It summarizes the CCU6 kernel registers and defines their relative addresses and the reset values. 8-bit short addresses are not available for this module. T12 related Registers T12 T12PR T12DTC CC60R CC60SR CC61R CC61SR CC62R CC62SR T13 related Registers T13 T13PR CC63R CC63SR Cap/Com Control Registers CMPSTAT CMPMODIF T12MSEL TCTR0 TCTR2 TCTR4 Interrupt Status/ Control Registers IS ISS ISR INP IEN 0IC 1IC 2IC 3IC General Registers KSCFG KSCSR MCFG PISELH PISELL Modulation Control Registers MODCTR TRPCTR PSLR MCMCTR MCMOUTS MCMOUT CCU6_regs Figure 18-2 CCU6 Registers User's Manual CCU6, UM_V0.5D3 18-4 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Table 18-1 CCU6 Module Register Summary Rel. Reset Addr. Value See Page Capture/Compare Unit 6 (CCU6) Short Name Description General Registers PISELL PISELH KSCFG KSCSR MCFG Module Port Input Select Register Module Port Input Select Register Kernel State Configuration Register 04H 06H 00H 0000H 0000H 0000H 0000H 8007H Page 18-107 Page 18-109 Page 18-111 Page 18-113 Page 18-114 Kernel State Control Sensitivity Register 0EH Module Configuration Register 0CH Timer T12 related Registers T12 T12PR T12DTC CC60R CC61R CC62R CC60SR CC61SR CC62SR Timer 12 Counter Register Timer 12 Period Register Dead-Time Control Register for Timer T12 Capture/Compare Register Channel CC60 Capture/Compare Register Channel CC61 Capture/Compare Register Channel CC62 Capture/Compare Shadow Register Channel CC60 Capture/Compare Shadow Register Channel CC61 Capture/Compare Shadow Register Channel CC62 10H 12H 14H 18H 1AH 1CH 20H 22H 24H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H Page 18-33 Page 18-33 Page 18-36 Page 18-34 Page 18-34 Page 18-34 Page 18-35 Page 18-35 Page 18-35 User's Manual CCU6, UM_V0.5D3 18-5 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Table 18-1 Capture/Compare Unit 6 (CCU6) CCU6 Module Register Summary (cont'd) Rel. Reset Addr. Value See Page Short Name Description Capture/Compare Control Registers CMPSTAT CMPMODIF T12MSEL TCTR0 TCTR2 TCTR4 Compare State Register Compare State Modification Register T12 Capture/Compare Mode Select Register Timer Control Register 0 Timer Control Register 2 Timer Control Register 4 28H 2AH 46H 2CH 2EH 26H 0000H 0000H 0000H 0000H 0000H 0000H Page 18-38 Page 18-40 Page 18-41 Page 18-42 Page 18-45 Page 18-48 Timer T13 related Registers T13 T13PR CC63R CC63SR Timer 13 Counter Register Timer 13 Period Register Compare Register for Timer 13 30H 32H 34H 0000H 0000H 0000H 0000H Page 18-63 Page 18-64 Page 18-65 Page 18-65 Compare Shadow Register for Timer 13 36H Modulation Control Registers MODCTR TRPCTR PSLR MCMOUTS Modulation Control Register Trap Control Register Passive State Level Register Multi-Channel Mode Output Shadow Register 18-6 40H 42H 44H 4AH 0000H 0000H 0000H 0000H Page 18-78 Page 18-80 Page 18-83 Page 18-86 User's Manual CCU6, UM_V0.5D3 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Table 18-1 Capture/Compare Unit 6 (CCU6) CCU6 Module Register Summary (cont'd) Rel. Reset Addr. Value 4CH 4EH 0000H 0000H See Page Page 18-87 Page HIDDEN Short Name Description MCMOUT MCMCTR Multi-Channel Mode Output Register Multi-Channel Mode Control Register Interrupt Status and Node Registers IS ISS ISR INP IEN Interrupt Status Register Interrupt Status Set Register Interrupt Status Reset Register Interrupt Node Pointer Register Interrupt Node Pointer Register 50H 52H 54H 56H 58H 0000H 0000H 0000H 3940H 0000H Page 18-91 Page 18-94 Page 18-96 Page 18-101 Page 18-98 Note: In the case of a write access to addresses inside the address range (that is covered by the same chip select signal), but that are not the addresses explicitly mentioned for the module, the write access is not taken into account for the module. The same principle is valid for read accesses. In case of a read access to another address, the module does not react. User's Manual CCU6, UM_V0.5D3 18-7 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.2 Operating Timer T12 The timer T12 block is the main unit to generate the 3-phase PWM signals. A 16-bit counter is connected to 3 channel registers via comparators, that generate a signal when the counter contents match one of the channel register contents. A variety of control functions facilitate the adaptation of the T12 structure to different application needs. Besides the 3-phase PWM generation, the T12 block offers options for individual compare and capture functions, as well as dead-time control and hysteresis-like compare mode. This section provides information about: * * * * * * * * T12 overview (see Section 18.2.1) Counting scheme (see Section 18.2.2) Compare modes (see Section 18.2.3) Compare mode output path (see Section 18.2.4) Capture modes (see Section 18.2.5) Shadow transfer (see Section 18.2.6) T12 operating mode selection (see Section 18.2.7) T12 counter register description (see Section 18.2.8) State Bits Capture/Compare Channel CC60 Timer T12 Logic Capture/Compare Channel CC61 Capture/Compare Channel CC62 Input and Control/Status Logic T12HR CC6xIN CCPOSx CC60ST To Dead-Time Control and Output Modulation CC61ST CC62ST CCU6_MCA05507 Figure 18-3 Overview Diagram of the Timer T12 Block User's Manual CCU6, UM_V0.5D3 18-8 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.2.1 T12 Overview Figure 18-4 shows a detailed block diagram of Timer T12. The functions of the timer T12 block are controlled by bits in registers TCTR0, TCTR2, and PISELL. Timer T12 receives its input clock (fT12) from the module clock fCC6 via a programmable prescaler and an optional 1/256 divider or from an input signal T12HR. These options are controlled via bit fields T12CLK and T12PRE (see Table 18-2). T12 can count up or down, depending on the selected operation mode. A direction flag, CDIR, indicates the current counting direction. T12RSEL T12RS T12RR edge detection ISCNT12 T12HR edge detection T12CNT 256 T12R CDIR CTM T12 Control & Status T12STR T12STD STE12 T12SSC Clock Selection n fT12 Counter Register T12 T12RES = 0000 H = 0001 H Comp. =? fCC6 T12_ZM T12_OM T12_PM T12CLK T12PRE Read from T12PR Period Register T12_ST Write to T12PR Period Shadow Register CCU6_MCA05508 Figure 18-4 Timer T12 Logic and Period Comparators Via a comparator, the T12 counter register T12 is connected to a Period Register T12PR. This register determines the maximum count value for T12. In Edge-Aligned mode, T12 is cleared to 0000H after it has reached the period value defined by T12PR. In Center-Aligned mode, the count direction of T12 is set from `up' to User's Manual CCU6, UM_V0.5D3 18-9 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) `down' after it has reached the period value (please note that in this mode, T12 exceeds the period value by one before counting down). In both cases, signal T12_PM (T12 Period Match) is generated. The Period Register receives a new period value from its Shadow Period Register. A read access to T12PR delivers the current period value at the comparator, whereas a write access targets the Shadow Period Register to prepare another period value. The transfer of a new period value from the Shadow Period Register into the Period Register (see Section 18.2.6) is controlled via the `T12 Shadow Transfer' control signal, T12_ST. The generation of this signal depends on the operating mode and on the shadow transfer enable bit STE12. Providing a shadow register for the period value as well as for other values related to the generation of the PWM signal allows a concurrent update by software for all relevant parameters. Two further signals indicate whether the counter contents are equal to 0000H (T12_ZM = zero match) or 0001H (T12_OM = one match). These signals control the counting and switching behavior of T12. The basic operating mode of T12, either Edge-Aligned mode (Figure 18-5) or CenterAligned mode (Figure 18-6), is selected via bit CTM. A Single-Shot control bit, T12SSC, enables an automatic stop of the timer when the current counting period is finished (see Figure 18-7 and Figure 18-8). The start or stop of T12 is controlled by the Run bit T12R that can be modified by bits in register TCTR4. The run bit can be set/cleared by software via the associated set/clear bits T12RS or T12RR, it can be set by a selectable edge of the input signal T12HR (TCTR2.T12RSEL), or it is cleared by hardware according to preselected conditions. Timer T12 can be cleared via control bit T12RES. Setting this write-only bit does only clear the timer contents, but has no further effects, for example, it does not stop the timer. The timer T12 run bit T12R must not be set while the applied T12 period value is zero. The generation of the T12 shadow transfer control signal, T12_ST, is enabled via bit STE12. This bit can be set or reset by software indirectly through its associated set/clear control bits T12STR and T12STD. While Timer T12 is running, write accesses to the count register T12 are not taken into account. If T12 is stopped and the Dead-Time counters are 0, write actions to register T12 are immediately taken into account. User's Manual CCU6, UM_V0.5D3 18-10 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.2.2 T12 Counting Scheme This section describes the clocking and counting capabilities of T12. 18.2.2.1 Clock Selection In Timer Mode (PISELH.ISCNT12 = 00B), the input clock fT12 of Timer T12 is derived from the internal module clock fCC6 through a programmable prescaler and an optional 1/256 divider. The resulting prescaler factors are listed in Table 18-2. The prescaler of T12 is cleared while T12 is not running (TCTR0.T12R = 0) to ensure reproducible timings and delays. Table 18-2 T12CLK 000B 001B 010B 011B 100B 101B 110B 111B Timer T12 Input Frequency Options Resulting Input Clock fT12 Prescaler Off (T12PRE = 0) Resulting Input Clock fT12 Prescaler On (T12PRE = 1) fCC6 fCC6 / 2 fCC6 / 4 fCC6 / 8 fCC6 / 16 fCC6 / 32 fCC6 / 64 fCC6 / 128 fCC6 / 256 fCC6 / 512 fCC6 / 1024 fCC6 / 2048 fCC6 / 4096 fCC6 / 8192 fCC6 / 16384 fCC6 / 32768 In Counter Mode, timer T12 counts one step: * * * If a 1 is written to TCTR4.T12CNT and PISELH.ISCNT12 = 01B If a rising edge of input signal T12HR is detected and PISELH.ISCNT12 = 10B If a falling edge of input signal T12HR is detected and PISELH.ISCNT12 = 11B User's Manual CCU6, UM_V0.5D3 18-11 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.2.2.2 Edge-Aligned / Center-Aligned Mode In Edge-Aligned Mode (CTM = 0), timer T12 is always counting upwards (CDIR = 0). When reaching the value given by the period register (period-match T12_PM), the value of T12 is cleared with the next counting step (saw tooth shape). fT12 Period Value T12 Count Period Zero Match Match Zero Up CDIR CC6x Value n+1 Value n+2 Up Shadow Transfer CCU6_MCT05509 Figure 18-5 T12 Operation in Edge-Aligned Mode As a result, in Edge-Aligned mode, the timer period is given by: T12PER = In Center-Aligned Mode (CTM = 1), timer T12 is counting upwards or downwards (triangular shape). When reaching the value given by the period register (period-match T12_PM) while counting upwards (CDIR = 0), the counting direction control bit CDIR is changed to downwards (CDIR = 1) with the next counting step. When reaching the value 0001H (one-match T12_OM) while counting downwards, the counting direction control bit CDIR is changed to upwards with the next counting step. As a result, in Center.Aligned mode, the timer period is given by: T12PER = ( With the next clock event of fT12 the count direction is set to counting up (CDIR = 0) when the counter reaches 0001H while counting down. With the next clock event of fT12 the count direction is set to counting down (CDIR = 1) when the Period-Match is detected while counting up. With the next clock event of fT12 the counter counts up while CDIR = 0 and it counts down while CDIR = 1. User's Manual CCU6, UM_V0.5D3 18-12 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) fT12 Period Value T12 Count Zero Match Period Match Period Match Zero Down CDIR CC6x Value n Value n+1 Value n+1 Value n+2 Up Up Down Shadow Transfer Shadow Transfer CCU6_MCT05510 Figure 18-6 T12 Operation in Center-Aligned Mode Note: Bit CDIR changes with the next timer clock event after the one-match or the period-match. Therefore, the timer continues counting in the previous direction for one cycle before actually changing its direction (see Figure 18-6). User's Manual CCU6, UM_V0.5D3 18-13 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.2.2.3 Single-Shot Mode In Single-Shot Mode, the timer run bit T12R is cleared by hardware. If bit T12SSC = 1, the timer T12 will stop when the current timer period is finished. In Edge-Aligned mode, T12R is cleared when the timer becomes zero after having reached the period value (see Figure 18-7). fT12 Period Value T12 Count Compare Value 0 T12R CC6xST T12SSC CCU6_MCT05511 Figure 18-7 Single-Shot Operation in Edge-Aligned Mode In Center-Aligned mode, the period is finished when the timer has counted down to zero (one clock cycle after the one-match while counting down, see Figure 18-8). fT12 Period Value Compare Value 1 0 T12R CC6xST T12SSC CCU6_MCT05512 T12 Count Figure 18-8 Single-Shot Operation in Center-Aligned Mode User's Manual CCU6, UM_V0.5D3 18-14 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.2.3 T12 Compare Mode Associated with Timer T12 are three individual capture/compare channels, that can perform compare or capture operations with regard to the contents of the T12 counter. The capture functions are explained in Section 18.2.5. 18.2.3.1 Compare Channels In Compare Mode (see Figure 18-9), the three individual compare channels CC60 CC61, and CC62 can generate a three-phase PWM pattern. Counter Register T12 fT12 Compare Match CM_60 Compare Match CM_61 Compare Match CM_62 Comp. =? Comp. =? Comp. =? Compare Register CC60R Compare Register CC61R Compare Register CC62R T12_ST Compare Shadow Register CC60SR Compare Shadow Register CC61SR Compare Shadow Register CC62SR CCU6_MCA05513 Figure 18-9 T12 Channel Comparators Each compare channel is connected to the T12 counter register via its individual equalto comparator, generating a match signal when the contents of the counter matches the contents of the associated compare register. Each channel consists of the comparator and a double register structure - the actual compare register CC6xR, feeding the comparator, and an associated shadow register CC6xSR, that is preloaded by software and transferred into the compare register when signal T12 shadow transfer, T12_ST, gets active. Providing a shadow register for the compare value as well as for other values related to the generation of the PWM signal facilitates a concurrent update by software for all relevant parameters of a three-phase PWM. User's Manual CCU6, UM_V0.5D3 18-15 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.2.3.2 Channel State Bits Associated with each (compare) channel is a State Bit, CMPSTAT.CC6xST, holding the status of the compare (or capture) operation (see Figure 18-10). In compare mode, the State Bits are modified according to a set of switching rules, depending on the current status of timer T12. CC60_R CCPOS0 Compare Channel CC60 CM_60 Switching Rule Logic To Interrupt CC60_F Control State Bit CC60ST To Dead_Time Counter 0 MSEL60 MCC60S/R CC61_R CCPOS1 Compare Channel CC61 CM_61 Switching Rule Logic To Interrupt CC61_F Control State Bit CC61ST To Dead_Time Counter 1 MSEL61 MCC61S/R CC62_R CCPOS2 Compare Channel CC62 CM_62 Switching Rule Logic To Interrupt CC62_F Control State Bit CC62ST To Dead_Time Counter 2 MSEL62 T12 Counter T12_ZM CDIR MCC62S/R T12R CCU6_MCB05514 Figure 18-10 Compare State Bits for Compare Mode The inputs to the switching rule logic for the CC6xST bits are the timer direction (CDIR), the timer run bit (T12R), the timer T12 zero-match signal (T12_ZM), and the actual individual compare-match signals CM_6x as well as the mode control bits, T12MSEL.MSEL6x. User's Manual CCU6, UM_V0.5D3 18-16 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) In addition, each state bit can be set or cleared by software via the appropriate set and reset bits in register CMPMODIF, MCC6xS and MCC6xR. The input signals CCPOSx are used in hysteresis-like compare mode, whereas in normal compare mode, these inputs are ignored. Note: In Hall Sensor, single shot or capture modes, additional/different rules are taken into account (see related sections). A compare interrupt event CC6x_R is signaled when a compare match is detected while counting upwards, whereas the compare interrupt event CC6x_F is signaled when a compare match is detected while counting down. The actual setting of a State Bit has no influence on the interrupt generation in compare mode. A modification of a State Bit CC6xST by the switching rule logic due to a compare action is only possible while Timer T12 is running (T12R = 1). If this is the case, the following switching rules apply for setting and clearing the State Bits in Compare Mode (illustrated in Figure 18-11 and Figure 18-12): A State Bit CC6xST is set to 1: * * with the next T12 clock (fT12) after a compare-match when T12 is counting up (i.e., when the counter is incremented above the compare value); with the next T12 clock (fT12) after a zero-match AND a parallel compare-match when T12 is counting up. with the next T12 clock (fT12) after a compare-match when T12 is counting down (i.e., when the counter is decremented below the compare value in center-aligned mode); with the next T12 clock (fT12) after a zero-match AND NO parallel compare-match when T12 is counting up. fT12 Period Value T12 Count Compare Value Zero A State Bit CC6xST is cleared to 0: * * CC6xST CCU6_MCT05515 Figure 18-11 Compare Operation, Edge-Aligned Mode Figure 18-13 illustrates some more examples for compare waveforms. It is important to note that in these examples, it is assumed that some of the compare values are changed User's Manual CCU6, UM_V0.5D3 18-17 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) while the timer is running. This change is performed via a software preload of the Shadow Register, CC6xSR. The value is transferred to the actual Compare Register CC6xR with the T12 Shadow Transfer signal, T12_ST, that is assumed to be enabled. fT12 Compare-Match T12 Count Compare-Match Period Value Compare Value Zero CC6xST CCU6_MCT05516 Figure 18-12 Compare Operation, Center-Aligned Mode User's Manual CCU6, UM_V0.5D3 18-18 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) fT12 Period Value = 5 T12 Count Zero Down CDIR CC6x Value n CC6x = 2 a) CC6x = 1 b) CC6x = 3 c) CC6x = 4 d) CC6x = 5 e) CC6x = 3 f) CCU6_MCT05517 Up Down Up Value n+1 CC6x = 2 CC6x = 0 CC6x = 3 CC6x = 4 CC6x = 5 CC6x = 6 Value n+2 CC6x = 1 CC6x = 0 CC6x = 3 CC6x = 4 CC6x = 5 CC6x = 6 Value n+3 CC6x = 1 CC6x = 0 CC6x = 3 CC6x = 4 CC6x = 5 CC6x = 6 Figure 18-13 Compare Waveform Examples Example b) illustrates the transition to a duty cycle of 100%. First, a compare value of 0001H is used, then changed to 0000H. Please note that a low pulse with the length of one T12 clock is still produced in the cycle where the new value 0000H is in effect; this pulse originates from the previous value 0001H. In the following timer cycles, the State Bit CC6xST remains at 1, producing a 100% duty cycle signal. In this case, the compare rule `zero-match AND compare-match' is in effect. Example f) shows the transition to a duty cycle of 0%. The new compare value is set to User's Manual CCU6, UM_V0.5D3 18-19 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) Period Value CC61R CC62R T12 Count CC60R Zero Down Down CDIR Shadow Transfer CC60ST CC61ST CC62ST Up Down Up CCU6_MCT05518 Figure 18-14 Three-Channel Compare Waveforms User's Manual CCU6, UM_V0.5D3 18-20 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.2.3.3 Hysteresis-Like Control Mode The hysteresis-like control mode (T12MSEL.MSEL6x = 1001B) offers the possibility to switch off the PWM output if the input CCPOSx becomes 0 by clearing the State Bit CC6xST. This can be used as a simple motor control feature by using a comparator indicating, e.g., overcurrent. While CCPOSx = 0, the PWM outputs of the corresponding channel are driving their passive levels, because the setting of bit CC6xST is only possible while CCPOSx = 1. As long as input CCPOSx is 0, the corresponding State Bit is held 0. When CCPOSx is at high level, the outputs can be in active state and are determined by bit CC6xST (see Figure 18-10 for the state bit logic and Figure 18-15 for the output paths). The CCPOSx inputs are evaluated with fCC6. This mode can be used to introduce a timing-related behavior to a hysteresis controller. A standard hysteresis controller detects if a value exceeds a limit and switches its output according to the compare result. Depending on the operating conditions, the switching frequency and the duty cycle are not fixed, but change permanently. If (outer) time-related control loops based on a hysteresis controller in an inner loop should be implemented, the outer loops show a better behavior if they are synchronized to the inner loops. Therefore, the hysteresis-like mode can be used, that combines timerrelated switching with a hysteresis controller behavior. For example, in this mode, an output can be switched on according to a fixed time base, but it is switched off as soon as a falling edge is detected at input CCPOSx. This mode can also be used for standard PWM with overcurrent protection. As long as there is no low level signal at pin CCPOSx, the output signals are generated in the normal manner as described in the previous sections. Only if input CCPOSx shows a low level, e.g. due to the detection of overcurrent, the outputs are shut off to avoid harmful stress to the system. User's Manual CCU6, UM_V0.5D3 18-21 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.2.4 Compare Mode Output Path Figure 18-15 gives an overview on the signal path from a channel State Bit to its output pin in its simplest form. As illustrated, a user has a variety of controls to determine the desired output signal switching behavior in relation to the current state of the State Bit, CC6xST. Please refer to Section 18.2.4.3 for details on the output modulation. T12 State Bits Dead-Time Generation T12 State Selection CC6xPS Output Level Selection PSLy CC6x T12 Output Modulation Level Select Level Select COUT6x PSLy+1 CCU6_MCA05519 CC60ST CC61ST CC62ST Dead-Time Counters CC6xST CC6x_O CC6xST COUT6x_O COUT6xPS Figure 18-15 Compare Mode Simplified Output Path Diagram The output path is based on signals that are defined as active or passive. The terms active and passive are not related to output levels, but to internal actions. This mainly applies for the modulation, where T12 and T13 signals are combined with the multichannel signals and the trap function. The Output level Selection allows the user to define the output level at the output pin for the passive state (inverted level for the active state). It is recommended to configure this block in a way that an external power switch is switched off while the CCU6 delivers an output signal in the passive state. 18.2.4.1 Dead-Time Generation The generation of (complementary) signals for the high-side and the low-side switches of one power inverter phase is based on the same compare channel. For example, if the high-side switch should be active while the T12 counter value is above the compare value (State Bit = 1), then the low-side switch should be active while the counter value is below the compare value (State Bit = 0). In most cases, the switching behavior of the connected power switches is not symmetrical concerning the switch-on and switch-off times. A general problem arises if the time for switch-on is smaller than the time for switch-off of the power device. In this case, a short-circuit can occur in the inverter bridge leg, which may damage the complete system. In order to solve this problem by HW, this capture/compare unit User's Manual CCU6, UM_V0.5D3 18-22 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) contains a programmable Dead-Time Generation Block, that delays the passive to active edge of the switching signals by a programmable time (the active to passive edge is not delayed). The Dead-Time Generation Block, illustrated in Figure 18-16, is built in a similar way for all three channels of T12. It is controlled by bits in register T12DTC. Any change of a CC6xST State Bit activates the corresponding Dead-Time Counter, that is clocked with the same input clock as T12 (fT12). The length of the dead-time can be programmed by bit field DTM. This value is identical for all three channels. Writing TCTR4.DTRES = 1 sets all dead-times to passive. Dead-Time Value DTM fT12 DTRES Dead-Time Counter 0 Dead-Time Counter 1 Dead-Time Counter 2 DTE0 CC60ST DTE1 CC61ST DTE2 CC62ST Dead-Time 0 active / passive Dead-Time 1 active / passive Dead-Time 2 active / passive CC60ST CC60ST CC61ST CC61ST CC62ST CC62ST CCU6_MCB05520 Figure 18-16 Dead-Time Generation Block Diagram Each of the three dead-time counters has its individual dead-time enable bit, DTEx. An enabled dead-time counter generates a dead-time delaying the passive-to-active edge of the channel output signal. The change in a State Bit CC6xST is not taken into account while the dead-time generation of this channel is currently in progress (active). This avoids an unintentional additional dead-time if a State Bit CC6xST changes too early. A disabled dead-time counter is always considered as passive and does not delay any edge of CC6xST. Based on the State Bits CC6xST, the Dead-Time Generation Block outputs a direct signal CC6xST and an inverted signal CC6xST for each compare channel, each masked with the effect of the related Dead-Time Counters (waveforms illustrated in Figure 18-17). User's Manual CCU6, UM_V0.5D3 18-23 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) T12 Counter Value Compare Value State Bit CC6xST active active passive DeadTime CC6xST with DeadTime CC6xST with DeadTime active passive passive active passive active passive CCU6_MCT05521 Figure 18-17 Dead-Time Generation Waveforms 18.2.4.2 State Selection To support a wide range of power switches and drivers, the state selection offers the flexibility to define when a an output can be active and can be modulated, especially useful for complementary or multi-phase PWM signals. The state selection is based on the signals CC6xST and CC6xST delivered by the deadtime generator (see Figure 18-15). Both signals are never active at the same time, but can be passive at the same time. This happens during the dead-time of each compare channel after a change of the corresponding State Bit CC6xST. The user can select independently for each output signal CC6xO and COUT6xO if it should be active before or after the compare value has been reached (see register CMPSTAT). With this selection, the active (conducting) phases of complementary power switches in a power inverter bridge leg can be positioned with respect to the compare value (e.g. signal CC6xO can be active before, whereas COUT6xO can be active after the compare value is reached). Like this, the output modulation, the trap logic and the output level selection can be programmed independently for each output signal, although two output signals are referring to the same compare channel. User's Manual CCU6, UM_V0.5D3 18-24 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.2.4.3 Output Modulation and Level Selection The last block of the data path is the Output Modulation block. Here, all the modulation sources and the trap functionality are combined and control the actual level of the output pins (controlled by the modulation enable bits T1xMODENy and MCMEN in register MODCTR). The following signal sources can be combined here for each T12 output signal (see Figure 18-18 for compare channel CC60): * A T12 related compare signal CC6x_O (for outputs CC6x) or COUT6x_O (for outputs COUT6x) delivered by the T12 block (state selection with dead-time) with an individual enable bit T12MODENy per output signal (y = 0, 2, 4 for outputs CC6x and y = 1, 3, 5 for outputs COUT6x) The T13 related compare signal CC63_O delivered by the T13 state selection with an individual enable bit T13MODENy per output signal (y = 0, 2, 4 for outputs CC6x and y = 1, 3, 5 for outputs COUT6x) A multi-channel output signal MCMPy (y = 0, 2, 4 for outputs CC6x and y = 1, 3, 5 for outputs COUT6x) with a common enable bit MCMEN The trap state TRPS with an individual enable bit TRPENy per output signal (y = 0, 2, 4 for outputs CC6x and y = 1, 3, 5 for outputs COUT6x) * * * If one of the modulation input signals CC6x_O/COUT6x_O, CC63_O, or MCMPy of an output modulation block is enabled and is at passive state, the modulated is also in passive state, regardless of the state of the other signals that are enabled. Only if all enabled signals are in active state the modulated output shows an active state. If no modulation input is enabled, the output is in passive state. If the Trap State is active (TRPS = 1), then the outputs that are enabled for the trap signal (by TRPENy = 1) are set to the passive state. The output of each of the modulation control blocks is connected to a level select block that is configured by register PSLR. It offers the option to determine the actual output level of a pin, depending on the state of the output line (decoupling of active/passive state and output polarity) as specified by the Passive State Select bit PSLy. If the modulated output signal is in the passive state, the level specified directly by PSLy is output. If it is in the active state, the inverted level of PSLy is output. This allows the user to adapt the polarity of an active output signal to the connected circuitry. The PSLy bits have shadow registers to allow for updates without undesired pulses on the output lines. The bits related to CC6x and COUT6x (x = 0, 1, 2) are updated with the T12 shadow transfer signal (T12_ST). A read action returns the actually used values, whereas a write action targets the shadow bits. Providing a shadow register for the PSL value as well as for other values related to the generation of the PWM signal facilitates a concurrent update by software for all relevant parameters. Figure 18-18 shows the output modulation structure for compare channel CC60 (output signals CC60 and COUT60). A similar structure is implemented for the other two compare channels CC61 and CC62. User's Manual CCU6, UM_V0.5D3 18-25 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) Trap Handling Block TRPS TRPEN0 CC63_O Output Modulation CC60 active passive Level Selection CC60 PSL0 T12MODEN0 MCMP0 Multi-Channel Mode MCMP1 T13 Block T13MODEN0 CC60_O T12 Block + Dead-Time COUT60_O MCMEN TRPEN1 T13MODEN1 Output Modulation COUT60 active passive Level Selection COUT60 PSL1 T12MODEN1 CCU6_MCA05543 Figure 18-18 Output Modulation for Compare Channel CC60 User's Manual CCU6, UM_V0.5D3 18-26 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.2.5 T12 Capture Modes Each of the three channels of the T12 Block can also be used to capture T12 time information in response to an external signal CC6xIN. In capture mode, the interrupt event CC6x_R is detected when a rising edge is detected at the input CC6xIN, whereas the interrupt event CC6x_F is detected when a falling edge is detected. There are a number of different modes for capture operation. In all modes, both of the registers of a channel are used. The selection of the capture modes is done via the T12MSEL.MSEL6x bit fields and can be selected individually for each of the channels. Table 18-3 MSEL6x 0100B 0101B 0110B 0111B 1 2 3 4 Capture Modes Overview Mode Signal Active Edge CC6nSR Stored in T12 Stored in - - CC6xR CC6xR CC6xR CC6xR CC6xSR CC6xSR CC6xSR CC6xSR CC6xIN Rising CC6xIN Falling CC6xIN Rising CC6xIN Falling CC6xIN Any Figure 18-19 illustrates Capture Mode 1. When a rising edge (0-to-1 transition) is detected at the corresponding input signal CC6xIN, the current contents of Timer T12 are captured into register CC6xR. When a falling edge (1-to-0 transition) is detected at the input signal CC6xIN, the contents of Timer T12 are captured into register CC6xSR. Counter Register T12 fT12 MSEL6x CC6xIN Edge Detect Capture Mode Selection Set Rising Falling fCC6 State Bit CC6xST Register CC6xR CC6x_R CC6x_F Shadow Register CC6xSR To Interrupt Logic CCU6_MCB05522 Figure 18-19 Capture Mode 1 Block Diagram User's Manual CCU6, UM_V0.5D3 18-27 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) Capture Modes 2, 3 and 4 are shown in Figure 18-20. They differ only in the active edge causing the capture operation. In each of the three modes, when the selected edge is detected at the corresponding input signal CC6xIN, the current contents of the shadow register CC6xSR are transferred into register CC6xR, and the current Timer T12 contents are captured in register CC6xSR (simultaneous transfer). The active edge is a rising edge of CC6xIN for Capture Mode 2, a falling edge for Mode 3, and both, a rising or a falling edge for Capture Mode 4, as shown in Table 18-3. These capture modes are very useful in cases where there is little time between two consecutive edges of the input signal. fT12 Counter Register T12 MSEL6x CC6xIN Edge Detect Capture Mode Selection Set Shadow Register CC6xSR fCC6 State Bit CC6xST Register CC6xR CC6x_R CC6x_F To Interrupt Logic CCU6_MCB05523 Figure 18-20 Capture Modes 2, 3 and 4 Block Diagram User's Manual CCU6, UM_V0.5D3 18-28 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) Five further capture modes are called Multi-Input Capture Modes, as they use two different external inputs, signal CC6xIN and signal CCPOSx. fT12 MSEL6x Counter Register T12 CC6xIN Edge Detect Capture Mode Selection Set State Bit CC6xST Set Register CC6xR CC6x_R CC6x_F fCC6 Shadow Register CC6xSR To Interrupt Logic CCPOSx Edge Detect Capture Mode Selection MSEL6x CCU6_MCB05524 Figure 18-21 Multi-Input Capture Modes Block Diagram In each of these modes, the current T12 contents are captured in register CC6xR in response to a selected event at signal CC6xIN, and in register CC6xSR in response to a selected event at signal CCPOSx. The possible events can be opposite input transitions, or the same transitions, or any transition at the two inputs. The different options are detailed in Table 18-4. In each of the various capture modes, the Channel State Bit, CC6xST, is set to 1 when the selected capture trigger event at signal CC6xIN or CCPOSx has occurred. The State Bit is not cleared by hardware, but can be cleared by software. In addition, appropriate signal lines to the interrupt logic are activated, that can generate an interrupt request to the CPU. Regardless of the selected active edge, all edges detected at signal CC6xIN can lead to the activation of the appropriate interrupt request line (see also Section 18.8). User's Manual CCU6, UM_V0.5D3 18-29 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Table 18-4 MSEL6x 1010B 1011B 1100B 1101B 1110B 1111B Capture/Compare Unit 6 (CCU6) Multi-Input Capture Modes Overview Mode 5 6 7 8 9 - Signal CC6xIN CCPOSx CC6xIN CCPOSx CC6xIN CCPOSx CC6xIN CCPOSx CC6xIN CCPOSx Active Edge Rising Falling Falling Rising Rising Rising Falling Falling Any Any T12 Stored in CC6xR CC6xSR CC6xR CC6xSR CC6xR CC6xSR CC6xR CC6xSR CC6xR CC6xSR reserved (no capture or compare action) User's Manual CCU6, UM_V0.5D3 18-30 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.2.6 T12 Shadow Register Transfer A special shadow transfer signal (T12_ST) can be generated to facilitate updating the period and compare values of the compare channels CC60, CC61, and CC62 synchronously to the operation of T12. Providing a shadow register for values defining one PWM period facilitates a concurrent update by software for all relevant parameters. The next PWM period can run with a new set of parameters. The generation of this signal is requested by software via bit TCTR0.STE12 (set by writing 1 to the write-only bit TCTR4.T12STR, cleared by writing 1 to the write-only bit TCTR4.T12STD). Figure 18-22 shows the shadow register structure and the shadow transfer signals, as well as on the read/write accessibility of the various registers. Read Period Register T12PR Read (T12) PSLy Read Read CC6xPS COUT6xPS Period Shadow Register T12PR Write Read Compare Register CC6xR _ >1 (T12) PSLy Shadow Write CC6xPS Shadow Write COUT6xPS Shadow Write T12_ST Other Modes (Hall, Capture, etc.) Compare Shadow Register CC6xSR Write Read CCU6_MCA05546 Figure 18-22 T12 Shadow Register Overview User's Manual CCU6, UM_V0.5D3 18-31 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) A T12 shadow register transfer takes place (T12_ST active): * * * while timer T12 is not running (T12R = 0), or STE12 = 1 and a Period-Match is detected while counting up, or STE12 = 1 and a One-Match is detected while counting down When signal T12_ST is active, a shadow register transfer is triggered with the next cycle of the T12 clock. Bit STE12 is automatically cleared with the shadow register transfer. 18.2.7 Timer T12 Operating Mode Selection The operating mode for the T12 channels are defined by the bit fields T12MSEL.MSEL6x. Table 18-5 MSEL6x 0000B, 1111B 0001B, 0010B, 0011B 01XXB 1000B T12 Capture/Compare Modes Overview Selected Operating Mode Capture/Compare modes switched off Compare mode, see Section 18.2.3 same behavior for all three codings Double-Register Capture modes, see Section 18.2.5 Hall Sensor Mode, see Section 18.6 In order to properly enable this mode, all three MSEL6x fields have to be programmed to Hall Sensor mode. Hysteresis-like compare mode, see Section 18.2.3.3 Multi-Input Capture modes, see Section 18.2.5 1001B 1010B 1011B, 1100B, 1101B 1110B The clocking and counting scheme of the timers are controlled by the timer control registers TCTR0 and TCTR2. Specific actions are triggered by write operations to register TCTR4. User's Manual CCU6, UM_V0.5D3 18-32 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.2.8 T12 related Registers 18.2.8.1 T12 Counter Register Register T12 represents the counting value of timer T12. It can only be written while the timer T12 is stopped. Write actions while T12 is running are not taken into account. Register T12 can always be read by SW. In edge-aligned mode, T12 only counts up, whereas in center-aligned mode, T12 can count up and down. T12 Timer T12 Counter Register 15 14 13 12 11 10 9 XSFR(10H) 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 T12CV rwh Field T12CV Bits [15:0] Type Description rwh Timer 12 Counter Value This register represents the 16-bit counter value of Timer12. Note: While timer T12 is stopped, the internal clock divider is reset in order to ensure reproducible timings and delays. 18.2.8.2 Period Register Register T12PR contains the period value for timer T12. The period value is compared to the actual counter value of T12 and the resulting counter actions depend on the defined counting rules. This register has a shadow register and the shadow transfer is controlled by bit STE12. A read action by SW delivers the value that is currently used for the compare action, whereas the write action targets a shadow register. The shadow register structure allows a concurrent update of all T12-related values. T12PR Timer 12 Period Register 15 14 13 12 11 10 9 XSFR(12H) 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 T12PV rwh User's Manual CCU6, UM_V0.5D3 18-33 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) Field T12PV Bits [15:0] Type Description rwh T12 Period Value The value T12PV defines the counter value for T12 leading to a period-match. When reaching this value, the timerT12 is set to zero (edge-aligned mode) or changes its count direction to down counting (centeraligned mode). 18.2.8.3 Capture/Compare Registers In compare mode, the registers CC6xR (x = 0 - 2) are the actual compare registers for T12. The values stored in CC6xR are compared (all three channels in parallel) to the counter value of T12. In capture mode, the current value of the T12 counter register is captured by registers CC6xR if the corresponding capture event is detected. CC6xR (x = 0-2) Capture/Compare Register for Channel CC6x XSFR(18H + 2*x) 15 14 13 12 11 10 9 8 CCV rh 7 6 5 4 Reset Value: 0000H 3 2 1 0 Field CCV Bits [15:0] Type Description rh Capture/Compare Value In compare mode, the bit fields CCV contain the values, that are compared to the T12 counter value. In capture mode, the captured value of T12 can be read from these registers. User's Manual CCU6, UM_V0.5D3 18-34 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.2.8.4 Capture/Compare Shadow Registers The registers CC6xR can only be read by SW, the modification of the value is done by a shadow register transfer from register CC6xSR. The corresponding shadow registers CC6xSR can be read and written by SW. In capture mode, the value of the T12 counter register can also be captured by registers CC6xSR if the selected capture event is detected (depending on the selected capture mode). CC6xSR (x=0-2) Capture/Compare Shadow Reg. for Channel CC6x XSFR(20H+2*x) 15 14 13 12 11 10 9 8 CCS rwh 7 6 5 4 Reset Value: 0000H 3 2 1 0 Field CCS Bits [15:0] Type Description rwh Shadow Register for Channel x Capture/ Compare Value In compare mode, the bit fields contents of CCS are transferred to the bit fields CCV for the corresponding channel during a shadow transfer. In capture mode, the captured value of T12 can be read from these registers. Note: The shadow registers can also be written by SW in capture mode. In this case, the HW capture event wins over the SW write if both happen in the same cycle (the SW write is discarded). User's Manual CCU6, UM_V0.5D3 18-35 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.2.8.5 Dead-time Control Register Register T12DTC controls the dead-time generation for the timer T12 compare channels. Each channel can be independently enabled/disabled for dead-time generation. If enabled, the transition from passive state to active state is delayed by the value defined by bit field DTM. The dead time counters are clocked with the same frequency as T12. This structure allows symmetrical dead-time generation in center-aligned and in edgealigned PWM mode. A duty cycle of 50% leads to CC6x, COUT6x switched on for: 0.5 * period - dead time. Note: The dead-time counters are not reset by bit T12RES, but by bit DTRES. T12DTC Dead-Time Control Register for Timer12 XSFR(14H) 15 0 r 14 13 12 11 0 r 10 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 DTR DTR DTR 2 1 0 rh rh rh DTE DTE DTE 2 1 0 rw rw rw DTM rw Field DTM Bits [7:0] Type Description rw Dead-Time Bit field DTM determines the programmable delay between switching from the passive state to the active state of the selected outputs. The switching from the active state to the passive state is not delayed. Dead Time Enable Bits Bits DTE0..DTE2 enable and disable the dead time generation for each compare channel (0, 1, 2) of timer T12. 0B Dead-Time Counter x is disabled. The corresponding outputs switch from the passive state to the active state (according to the actual compare status) without any delay. 1B Dead-Time Counter x is enabled. The corresponding outputs switch from the passive state to the active state (according to the compare status) with the delay programmed in bit field DTM. 18-36 V1.0, 2007-06 DTE2, DTE1, DTE0 10, 9, 8 rw User's Manual CCU6, UM_V0.5D3 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field DTR2, DTR1, DTR0 Bits 14, 13, 12 Type Description rh Dead Time Run Indication Bits Bits DTR0..DTR2 indicate the status of the dead time generation for each compare channel (0, 1, 2) of timer T12. 0B Dead-Time Counter x is currently in the passive state. 1B Dead-Time Counter x is currently in the active state. reserved; returns 0 if read; should be written with 0; Capture/Compare Unit 6 (CCU6) 0 [15:11] r User's Manual CCU6, UM_V0.5D3 18-37 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.2.9 Capture/Compare Control Registers 18.2.9.1 Channel State Bits The Compare State Register CMPSTAT contains status bits monitoring the current capture and compare state and control bits defining the active/passive state of the compare channels. CMPSTAT Compare State Register 15 14 13 12 11 10 9 XSFR(28H) 8 7 0 r 6 5 4 Reset Value: 0000H 3 2 1 0 CC CC CC CC CC CC CC POS POS POS 62ST 61ST 60ST 63ST 60 61 62 rh rh rh rh rh rh rh C C C C CC CC CC T13 OUT OUT OUT OUT 62PS 61PS 60PS IM 61PS 60PS 63PS 62PS rwh rwh rwh rwh rwh rwh rwh rwh Field CC60ST, CC61ST, CC62ST, CC63ST 1) Bits 0, 1, 2, 6 Type Description rh Capture/Compare State Bits Bits CC6xST monitor the state of the capture/ compare channels. Bits CC6xST (x = 0, 1, 2) are related to T12, bit CC63ST is related to T13. In compare mode, the timer count is less than 0B the compare value. In capture mode, the selected edge has not yet been detected since the bit has been cleared by SW the last time. 1B In compare mode, the counter value is greater than or equal to the compare value. In capture mode, the selected edge has been detected. Sampled Hall Pattern Bits Bits CCPOSx (x = 0, 1, 2) are indicating the value of the input Hall pattern that has been compared to the current and expected value. The value is sampled when the event HCRDY (Hall Compare Ready) occurs. 0B The input CCPOSx has been sampled as 0. 1B The input CCPOSx has been sampled as 1. CCPOS0, CCPOS1, CCPOS2 3, 4, 5 rh User's Manual CCU6, UM_V0.5D3 18-38 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field CC60PS, CC61PS, CC62PS, COUT60PS, COUT61PS, COUT62PS, COUT63PS 2) Capture/Compare Unit 6 (CCU6) Bits 8, 10, 12, 9, 11, 13, 14 Type Description rwh Passive State Select for Compare Outputs Bits CC6xPS, COUT6xPS select the state of the corresponding compare channel, that is considered to be the passive state. During the passive state, the passive level (defined in register PSLR) is driven by the output pin. Bits CC6xPS, COUT6xPS (x = 0, 1, 2) are related to T12, bit CC63PS is related to T13. 0B The corresponding compare signal is in passive state while CC6xST is 0. 1B The corresponding compare signal is in passive state while CC6xST is 1. In capture mode, these bits are not used. T13 Inverted Modulation Bit T13IM inverts the T13 signal for the modulation of the CC6x and COUT6x (x = 0, 1, 2) signals. T13 output CC63_O is equal to CC63ST. 0B 1B T13 output CC63_O is equal to CC63ST. reserved; returns 0 if read; should be written with 0; T13IM3) 15 rwh 0 1) 2) 7 r These bits are set and cleared according to the T12, T13 switching rules These bits have shadow bits and are updated in parallel to the capture/compare registers of T12, T13 respectively. A read action targets the actually used values, whereas a write action targets the shadow bits. This bit has a shadow bit and is updated in parallel to the compare and period registers of T13. A read action targets the actually used values, whereas a write action targets the shadow bit. 3) User's Manual CCU6, UM_V0.5D3 18-39 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) The Compare Status Modification Register CMPMODIF provides software-control (independent set and clear conditions) for the channel state bits CC6xST. This feature enables the user to individually change the status of the output lines by software, for example when the corresponding compare timer is stopped. CMPMODIF Compare State Modification Register XSFR(2AH) 15 0 r 14 MCC 63R w 13 12 0 r 11 10 9 8 7 0 r 6 MCC 63S w 5 4 0 r Reset Value: 0000H 3 2 1 0 MCC MCC MCC 62R 61R 60R w w w MCC MCC MCC 62S 61S 60S w w w Field MCC60S, MCC61S, MCC62S, MCC63S, MCC60R, MCC61R, MCC62R, MCC63R Bits 0, 1, 2, 7, 8, 9, 10, 14 Type Description w Capture/Compare Status Modification Bits These bits are used to bits to set (MCC6xS) or to clear (MCC6xR) the corresponding bits CC6xST by SW. This feature allows the user to individually change the status of the output lines by SW, e.g. when the corresponding compare timer is stopped. This allows a bit manipulation of CC6xST-bits by a single data write action. The following functionality of a write access to bits concerning the same capture/compare state bit is provided: [MCC6xR, MCC6xS] = 00B Bit CC6xST is not changed. 01B Bit CC6xST is set. 10B Bit CC6xST is cleared. 11B reserved reserved; returns 0 if read; should be written with 0; 0 [5:3], 7, [13:11], 15 r User's Manual CCU6, UM_V0.5D3 18-40 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.2.9.2 T12 Mode Control Register Register T12MSEL contains control bits to select the capture/compare functionality of the three channels of Timer T12. T12MSEL T12 Mode Select Register 15 D BYP rw 14 13 HSYNC rw 12 11 10 9 XSFR (46H) 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 MSEL62 rw MSEL61 rw MSEL60 rw Field MSEL60, MSEL61, MSEL62 Bits [3:0], [7:4], [11:8] Type rw Description Capture/Compare Mode Selection These bit fields select the operating mode of the three T12 capture/compare channels. Each channel (x = 0, 1, 2) can be programmed individually for one of these modes (except for Hall Sensor Mode). Coding see Table 18-5. Hall Synchronization Bit field HSYNC defines the source for the sampling of the Hall input pattern and the comparison to the current and the expected Hall pattern bit fields. Coding see Table 18-11. Delay Bypass DBYP controls whether the source signal for the sampling of the Hall input pattern (selected by HSYNC) is delayed by the Dead-Time Counter 0. 0 The bypass is not active. Dead-Time Counter 0 is generating a delay after the source signal becomes active. 1 The bypass is active. Dead-Time Counter 0 is not used for a delay. HSYNC [14:12] rw DBYP 15 rw User's Manual CCU6, UM_V0.5D3 18-41 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.2.9.3 Timer Control Registers Register TCTR0 controls the basic functionality of both timers, T12 and T13. Note: A write action to the bit fields T12CLK or T12PRE is only taken into account while the timer T12 is not running (T12R=0). A write action to the bit fields T13CLK or T13PRE is only taken into account while the timer T13 is not running (T13R=0). TCTR0 Timer Control Register 0 15 0 r 14 13 12 11 10 9 T13CLK rw XSFR(2CH) 8 7 6 5 4 Reset Value: 0000H 3 2 1 T12CLK rw 0 STE T13 T13R 13 PRE rh rh rw CTM CDIR rw rh STE T12 T12R 12 PRE rh rh rw Field T12CLK Bits [2:0] Type Description rw Timer T12 Input Clock Select Selects the input clock for timer T12 that is derived from the peripheral clock according to the equation fT12 = fCC6 / 2 18-42 V1.0, 2007-06 T12PRE 3 rw T12R 4 rh User's Manual CCU6, UM_V0.5D3 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field STE12 Bits 5 Type Description rh Timer T12 Shadow Transfer Enable Bit STE12 enables or disables the shadow transfer of the T12 period value, the compare values and passive state select bits and levels from their shadow registers to the actual registers if a T12 shadow transfer event is detected. Bit STE12 is cleared by hardware after the shadow transfer. A T12 shadow transfer event is a period-match while counting up or a one-match while counting down. 0B The shadow register transfer is disabled. The shadow register transfer is enabled. 1B Count Direction of Timer T12 This bit is set/cleared according to the counting rules of T12. 0B T12 counts up. T12 counts down. 1B T12 Operating Mode 0B Edge-aligned Mode: T12 always counts up and continues counting from zero after reaching the period value. 1B Center-aligned Mode: T12 counts down after detecting a period-match and counts up after detecting a one-match. Timer T13 Input Clock Select Selects the input clock for timer T13 that is derived from the peripheral clock according to the equation fT13 = fCC6 / 2 CDIR 6 rh CTM 7 rw T13CLK [10:8] rw User's Manual CCU6, UM_V0.5D3 18-43 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field T13PRE Bits 11 Type Description rw Timer T13 Prescaler Bit In order to support higher clock frequencies, an additional prescaler factor of 1/256 can be enabled for the prescaler for T13. 0B The additional prescaler for T13 is disabled. 1B The additional prescaler for T13 is enabled. Timer T13 Run Bit2) T13R starts and stops timer T13. It is set/cleared by SW by setting bits T13RR orT13RS or it is set/cleared by HW according to the function defined by bit fields T13SSC, T13TEC and T13TED. 0B Timer T13 is stopped. 1B Timer T13 is running. Timer T13 Shadow Transfer Enable Bit STE13 enables or disables the shadow transfer of the T13 period value, the compare value and passive state select bit and level from their shadow registers to the actual registers if a T13 shadow transfer event is detected. Bit STE13 is cleared by hardware after the shadow transfer. A T13 shadow transfer event is a period-match. 0B The shadow register transfer is disabled. 1B The shadow register transfer is enabled. reserved; returns 0 if read; should be written with 0; Capture/Compare Unit 6 (CCU6) T13R 12 rh STE13 13 rh 0 1) [15: 14] r A concurrent set/clear action on T12R (from T12SSC, T12RR or T12RS) will have no effect. The bit T12R will remain unchanged. A concurrent set/cleared action on T13R (from T13SSC, T13TEC, T13RR or T13RS) will have no effect. The bit T12R will remain unchanged. 2) User's Manual CCU6, UM_V0.5D3 18-44 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) Register TCTR2 controls the single-shot and the synchronization functionality of both timers T12 and T13. Both timers can run in single-shot mode. In this mode they stop their counting sequence automatically after one counting period with a count value of zero. The single-shot mode and the synchronization feature of T13 to T12 allow the generation of events with a programmable delay after well-defined PWM actions of T12. TCTR2 Timer Control Register 2 15 14 0 r 13 12 11 10 9 XSFR(2EH) 8 7 0 r 6 T13 TED rw 5 4 Reset Value: 0000H 3 T13 TEC rw 2 1 0 T13 RSEL rw T12 RSEL rw T13 T12 SSC SSC rw rw Field T12SSC Bits 0 Type Description rw Timer T12 Single Shot Control This bit controls the single shot-mode of T12. 0B The single-shot mode is disabled, no HW action on T12R. 1B The single shot mode is enabled, the bit T12R is cleared by HW if - T12 reaches its period value in edge-aligned mode - T12 reaches the value 1 while down counting in center-aligned mode. In parallel to the clear action of bit T12R, the bits CC6xST (x=0, 1, 2) are cleared. Timer T13 Single Shot Control This bit controls the single shot-mode of T13. 0B No HW action on T13R 1B The single-shot mode is enabled, the bit T13R is cleared by HW if T13 reaches its period value. In parallel to the clear action of bit T13R, the bit CC63ST is cleared. T13SSC 1 rw User's Manual CCU6, UM_V0.5D3 18-45 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field T13TEC Bits [4:2] Type Description rw T13 Trigger Event Control bit field T13TEC selects the trigger event to start T13 (automatic set of T13R for synchronization to T12 compare signals) according to following combinations: 000B no action 001B set T13R on a T12 compare event on channel 0 010B set T13R on a T12 compare event on channel 1 011B set T13R on a T12 compare event on channel 2 100B set T13R on any T12 compare event (ch. 0, 1, 2) 101B set T13R upon a period-match of T12 110B set T13R upon a zero-match of T12 (while counting up) 111B set T13R on any edge of inputs CCPOSx Timer T13 Trigger Event Direction1) Bit field T13TED delivers additional information to control the automatic set of bit T13R in the case that the trigger action defined by T13TEC is detected. 00B reserved, no action 01B while T12 is counting up 10B while T12 is counting down 11B independent on the count direction of T12 Timer T12 External Run Selection Bit field T12RSEL defines the event of signal T12HR that can set the run bit T12R by HW. 00B The external setting of T12R is disabled. 01B Bit T12R is set if a rising edge of signal T12HR is detected. 10B Bit T12R is set if a falling edge of signal T12HR is detected. 11B Bit T12R is set if an edge of signal T12HR is detected. Capture/Compare Unit 6 (CCU6) T13TED [6:5] rw T12RSEL [9:8] rw User's Manual CCU6, UM_V0.5D3 18-46 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field T13RSEL Bits Type Description Timer T13 External Run Selection Bit field T13RSEL defines the event of signal T13HR that can set the run bit T13R by HW. 00B The external setting of T13R is disabled. 01B Bit T13R is set if a rising edge of signal T13HR is detected. 10B Bit T13R is set if a falling edge of signal T13HR is detected. 11B Bit T13R is set if an edge of signal T13HR is detected. reserved; returns 0 if read; should be written with 0; Capture/Compare Unit 6 (CCU6) [11:10] rw 0 1) 7, r [15: 12] Example: If the timer T13 is intended to start at any compare event on T12 (T13TEC=100) the trigger event direction can be programmed to - counting up >> a T12 channel 0, 1, 2 compare match triggers T13R only while T12 is counting up - counting down >> a T12 channel 0, 1, 2 compare match triggers T13R only while T12 is counting down - independent from bit CDIR >> each T12 channel 0, 1, 2 compare match triggers T13R The timer count direction is taken from the value of bit CDIR. As a result, if T12 is running in edge-aligned mode (counting up only), T13 can only be started automatically if bit field T13TED=01 or 11. User's Manual CCU6, UM_V0.5D3 18-47 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) Register TCTR4 provides software-control (independent set and clear conditions) for the run bits T12R and T13R. Furthermore, the timers can be reset (while running) and bits STE12 and STE13 can be controlled by software. Reading these bits always returns 0. TCTR4 Timer Control Register 4 15 14 13 12 0 r 11 10 9 XSFR(26H) 8 7 6 5 4 0 r Reset Value: 0000H 3 2 1 0 T13 T13 T13 STD STR CNT w w w T13 T13 T13 T12 T12 T12 RES RS RR STD STR CNT w w w w w w DT T12 T12 T12 RES RES RS RR w w w w Field T12RR Bits 0 Type Description w Timer T12 Run Reset Setting this bit clears the T12R bit. 0B T12R is not influenced. 1B T12R is cleared, T12 stops counting. Timer T12 Run Set Setting this bit sets the T12R bit. T12R is not influenced. 0B 1B T12R is set, T12 starts counting. Timer T12 Reset 0B No effect on T12. The T12 counter register is cleared to zero. The 1B switching of the output signals is according to the switching rules. Setting of T12RES has no impact on bit T12R. Dead-Time Counter Reset 0B No effect on the dead-time counters. 1B The three dead-time counter channels are cleared to zero. Timer T12 Count Event 0B No action 1B If enabled (PISELH), timer T12 counts one step. Timer T12 Shadow Transfer Request 0B No action 1B STE12 is set, enabling the shadow transfer. T12RS 1 w T12RES 2 w DTRES 3 w T12CNT 5 w T12STR 6 w User's Manual CCU6, UM_V0.5D3 18-48 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field T12STD Bits 7 Type Description w Timer T12 Shadow Transfer Disable 0B No action 1B STE12 is cleared without triggering the shadow transfer. Timer T13 Run Reset Setting this bit clears the T13R bit. T13R is not influenced. 0B T13R is cleared, T13 stops counting. 1B Timer T13 Run Set Setting this bit sets the T13R bit. 0B T13R is not influenced. 1B T13R is set, T13 starts counting. Timer T13 Reset 0B No effect on T13. 1B The T13 counter register is cleared to zero. The switching of the output signals is according to the switching rules. Setting of T13RES has no impact on bit T13R. Timer T13 Count Event 0B No action 1B If enabled (PISELH), timer T13 counts one step. Timer T13 Shadow Transfer Request 0B No action 1B STE13 is set, enabling the shadow transfer. Timer T13 Shadow Transfer Disable 0B No action 1B STE13 is cleared without triggering the shadow transfer. reserved; returns 0 if read; should be written with 0; Capture/Compare Unit 6 (CCU6) T13RR 8 w T13RS 9 w T13RES 10 w T13CNT 13 w T13STR 14 w T13STD 15 w 0 4, r [12:11] Note: A simultaneous write of a 1 to bits that set and clear the same bit will trigger no action. The corresponding bit will remain unchanged. User's Manual CCU6, UM_V0.5D3 18-49 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.3 Operating Timer T13 Timer T13 is implemented similarly to Timer T12, but only with one channel in compare mode. A 16-bit up-counter is connected to a channel register via a comparator, that generates a signal when the counter contents match the contents of the channel register. A variety of control functions facilitate the adaptation of the T13 structure to different application needs. In addition, T13 can be started synchronously to timer T12 events. This section provides information about: * * * * * * T13 overview (see Section 18.3.1) Counting scheme (see Section 18.3.2) Compare mode (see Section 18.3.3) Compare output path (see Section 18.3.4) Shadow register transfer (see Section 18.3.5) T13 counter register description (see Section 18.3.6) State Bit Timer T13 Logic Capture/Compare Channel CC63 Input and Control/Status Logic T13HR Synchronization to T12 CC63ST To Output Modulation CCU6_MCA05526 Figure 18-23 Overview Diagram of the Timer T13 Block 18.3.1 T13 Overview Figure 18-24 shows a detailed block diagram of Timer T13. The functions of the timer T12 block are controlled by bits in registers TCTR0, TCTR2, and PISELH. Timer T13 receives its input clock, fT13, from the module clock fCC6 via a programmable prescaler and an optional 1/256 divider or from an input signal T13HR. T13 can only count up (similar to the Edge-Aligned mode of T12). Via a comparator, the timer T13 Counter Register T13 is connected to the Period Register T13PR. This register determines the maximum count value for T13. When T13 reaches the period value, signal T13_PM (T13 Period Match) is generated and T13 is cleared to 0000H with the next T13 clock edge. The Period Register receives a new period value from its Shadow Period Register, T13PS, that is loaded via software. The transfer of a new period value from the shadow register into T13PR is controlled via the `T13 Shadow Transfer' control signal, T13_ST. The generation of this signal depends on the associated control bit STE13. Providing a shadow register for the period value as User's Manual CCU6, UM_V0.5D3 18-50 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) well as for other values related to the generation of the PWM signal facilitates a concurrent update by software for all relevant parameters (refer to Table 18.3.5). Another signal indicates whether the counter contents are equal to 0000H (T13_ZM). A Single-Shot control bit, T13SSC, enables an automatic stop of the timer when the current counting period is finished (see Figure 18-26). T13RSEL T13RS T13RR edge detection ISCNT13 T13STR T13STD edge detection Clock Selection 256 Sync. to T12 T13R T13HR STE13 T13 Control & Status T13SSC T13CNT fT13 Counter Register T13 T13RES fCC6 n Comp. =? T13CLK T13PRE Read from T13PR = 0000 H T13_ZM T13_PM Period Register T13_ST Write to T13PR Period Shadow Register CCU6_MCA05527 Figure 18-24 T13 Counter Logic and Period Comparators The start or stop of T13 is controlled by the Run bit, T13R. This control bit can be set by software via the associated set/clear bits T13RS or T13RR in register TCTR4, or it is cleared by hardware according to preselected conditions (single-shot mode). The timer T13 run bit T13R must not be set while the applied T13 period value is zero. Bit T13R can be set automatically if an event of T12 is detected to synchronize T13 timings to T12 events, e.g. to generate a programmable delay via T13 after an edge of a T12 compare channel before triggering an AD conversion (T13 can trigger ADC User's Manual CCU6, UM_V0.5D3 18-51 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) conversions). Timer T13 can be cleared to 0000H via control bit T13RES. Setting this write-only bit only clears the timer contents, but has no further effects, e.g., it does not stop the timer. The generation of the T13 shadow transfer control signal, T13_ST, is enabled via bit STE13. This bit can be set or cleared by software indirectly through its associated set/ reset control bits T13STR and T13STD. Two bit fields, T13TEC and T13TED, control the synchronization of T13 to Timer T12 events. T13TEC selects the trigger event, while T13TED determines for which T12 count direction the trigger should be active. While Timer T13 is running, write accesses to the count register T13 are not taken into account. If T13 is stopped, write actions to register T13 are immediately taken into account. Note: The T13 Period Register and its associated shadow register are located at the same physical address. A write access to this address targets the Shadow Register, while a read access reads from the actual period register. User's Manual CCU6, UM_V0.5D3 18-52 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.3.2 T13 Counting Scheme This section describes the clocking and the counting capabilities of T13. 18.3.2.1 Clock Selection In Timer Mode (PISELH. ISCNT13 = 00B), the input clock fT13 of Timer T13 is derived from the internal module clock fCC6 through a programmable prescaler and an optional 1/256 divider. The resulting prescaler factors are listed in Table 18-6. The prescaler of T13 is cleared while T13 is not running (TCTR0.T13R = 0) to ensure reproducible timings and delays. Table 18-6 T13CLK 000B 001B 010B 011B 100B 101B 110B 111B Timer T13 Input Clock Options Resulting Input Clock fT13 Prescaler Off (T13PRE = 0) Resulting Input Clock fT13 Prescaler On (T13PRE = 1) fCC6 fCC6 / 2 fCC6 / 4 fCC6 / 8 fCC6 / 16 fCC6 / 32 fCC6 / 64 fCC6 / 128 fCC6 / 256 fCC6 / 512 fCC6 / 1024 fCC6 / 2048 fCC6 / 4096 fCC6 / 8192 fCC6 / 16384 fCC6 / 32768 In Counter Mode, timer T13 counts one step: * * * If a 1 is written to TCTR4.T13CNT and PISELH.ISCNT13 = 01B If a rising edge of input signal T13HR is detected and PISELH.ISCNT13 = 10B If a falling edge of input signal T13HR is detected and PISELH.ISCNT13 = 11B User's Manual CCU6, UM_V0.5D3 18-53 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.3.2.2 T13 Counting The period of the timer is determined by the value in the period Register T13PR according to the following formula: T13PER = Timer T13 can only count up, comparable to the Edge-Aligned mode of T12. This leads to very simple `counting rule' for the T13 counter: * The counter is cleared with the next T13 clock edge if a Period-Match is detected. The counting direction is always upwards. The behavior of T13 is illustrated in Figure 18-25. fT13 Period Value T13 Count Period Zero Match Match Zero CC63 Value n+1 Value n+2 Shadow Transfer CCU6_MCT05528 Figure 18-25 T13 Counting Sequence User's Manual CCU6, UM_V0.5D3 18-54 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.3.2.3 Single-Shot Mode In Single-Shot Mode, the timer run bit T13R is cleared by hardware. If bit T13SSC = 1, the timer T13 will stop when the current timer period is finished. fT13 Period Value T13 Count Compare Value 0 T13R CC63ST T13SSC CCU6_MCT05529 Figure 18-26 Single-Shot Operation of Timer T13 User's Manual CCU6, UM_V0.5D3 18-55 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.3.2.4 Synchronization to T12 Timer T13 can be synchronized to a T12 event. Bit fields T13TEC and T13TED select the event that is used to start Timer T13. The selected event sets bit T13R via HW, and T13 starts counting. Combined with the Single-Shot mode, this feature can be used to generate a programmable delay after a T12 event. Figure 18-27 shows an example for the synchronization of T13 to a T12 event. Here, the selected event is a compare-match (compare value = 2) while counting up. The clocks of T12 and T13 can be different (other prescaler factor); the figure shows an example in which T13 is clocked with half the frequency of T12. fT12 Compare-Match T12 Count Period Value Compare Value Zero T13R T13 Count fT13 CCU6_MCT05530 Figure 18-27 Synchronization of T13 to T12 Compare Match Bit field T13TEC selects the trigger event to start T13 (automatic set of T13R for synchronization to T12 compare signals) according to the combinations shown in Table 18-7. Bit field T13TED additionally specifies for which count direction of T12 the selected trigger event should be regarded (see Table 18-8). User's Manual CCU6, UM_V0.5D3 18-56 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Table 18-7 T13TEC 000B 001B 010B 011B 100B 101B 110B 111B Table 18-8 T13TED 00B 01B 10B 11B T12 Trigger Event Selection Selected Event None T12 Compare Event on Channel 0 (CM_CC60) T12 Compare Event on Channel 1 (CM_CC61) T12 Compare Event on Channel 2 (CM_CC62) T12 Compare Event on any Channel (0, 1, 2) T12 Period-Match (T12_PM) T12 Zero-Match while counting up (T12_ZM and CDIR = 0) Any Hall State Change Capture/Compare Unit 6 (CCU6) T12 Trigger Event Additional Specifier Selected Event Specifier Reserved, no action Selected event is active while T12 is counting up (CDIR = 0) Selected event is active while T12 is counting down (CDIR = 1) Selected event is active independently of the count direction of T12 User's Manual CCU6, UM_V0.5D3 18-57 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.3.3 T13 Compare Mode Associated with Timer T13 is one compare channel, that can perform compare operations with regard to the contents of the T13 counter. Figure 18-23 gives an overview on the T13 channel in Compare Mode. The channel is connected to the T13 counter register via an equal-to comparator, generating a compare match signal when the contents of the counter matches the contents of the compare register. The channel consists of the comparator and a double register structure - the actual compare register, CC63R, feeding the comparator, and an associated shadow register, CC63SR, that is preloaded by software and transferred into the compare register when signal T13 shadow transfer, T13_ST, gets active. Providing a shadow register for the compare value as well as for other values related to the generation of the PWM signal facilitates a concurrent update by software for all relevant parameters. Associated with the channel is a State Bit, CMPSTAT.CC63ST, holding the status of the compare operation. Figure 18-28 gives an overview on the logic for the State Bit. fT13 Counter Register T13 T13_ZM Comp. =? CM_63 Switching Rule Logic State Bit CC63ST To State Selection and Output Modulation Compare Register CC63R T13R MCC63S/R To Interrupt Control T13_ST Compare Shadow Register CC63SR CCU6_MCB05532 Figure 18-28 T13 State Bit Block Diagram A compare interrupt event CM_63 is signaled when a compare match is detected. The actual setting of a State Bit has no influence on the interrupt generation. The inputs to the switching rule logic for the CC63ST bit are the timer run bit (T13R), the timer zero-match signal (T13_ZM), and the actual individual compare-match signal CM_63. In addition, the state bit can be set or cleared by software via bits MCC63S and User's Manual CCU6, UM_V0.5D3 18-58 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) MCC63R in register CMPMODIF. A modification of the State Bit CC63ST by hardware is only possible while Timer T13 is running (T13R = 1). If this is the case, the following switching rules apply for setting and resetting the State Bit in Compare Mode: State Bit CC63ST is set to 1 * * * with the next T13 clock (fT13) after a compare-match (T13 is always counting up) (i.e., when the counter is incremented above the compare value); with the next T13 clock (fT13) after a zero-match AND a parallel compare-match. with the next T13 clock (fT13) after a zero-match AND NO parallel compare-match. fT13 Compare-Match T13 Count Compare-Match Period Value Compare Value Zero CC63ST CCU6_MCT05533 State Bit CC63ST is cleared to 0 Figure 18-29 T13 Compare Operation User's Manual CCU6, UM_V0.5D3 18-59 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.3.4 Compare Mode Output Path Figure 18-30 gives an overview on the signal path from the channel State Bit CC63ST to its output pin COUT63. As illustrated, a user can determine the desired output behavior in relation to the current state of CC63ST. Please refer to Section 18.2.4.3 for detailed information on the output modulation for T12 signals. T13 State Selection T13IM CC63ST T13 State Bit CC63ST CC63ST COUT63_O ECT13O PSL63 CCU6_MCA05534 Output Modulation Output Level Selection CC63_O T12 Output Modulation T13 Output Modulation Level Select COUT63 COUT63PS Figure 18-30 Channel 63 Output Path The output line COUT63_O can generate a T13 PWM at the output pin COUT63. The signal CC63_O can be used to modulate the T12-related output signals with a T13 PWM. In order to decouple COUT63 from the internal modulation, the compare state leading to an active signal can be selected independently by bits T13IM and COUT63PS. The last block of the data path is the Output Modulation block. Here, the modulation source T13 and the trap functionality are combined and control the actual level of the output pin COUT63 (see Figure 18-31): * * The T13 related compare signal COUT63_O delivered by the T13 state selection with the enable bit MODCTR.ECT13O The trap state TRPS with an individual enable bit TRPCTR.TRPEN13 If the modulation input signal COUT63_O is enabled (ECT13O = 1) and is at passive state, the modulated is also in passive state. If the modulation input is not enabled, the output is in passive state. If the Trap State is active (TRPS = 1), then the output enabled for the trap signal (by TRPEN13 = 1) is set to the passive state. The output of the modulation control block is connected to a level select block. It offers the option to determine the actual output level of a pin, depending on the state of the output line (decoupling of active/passive state and output polarity) as specified by the Passive State Select bit PSLR.PSL63. If the modulated output signal is in the passive User's Manual CCU6, UM_V0.5D3 18-60 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) state, the level specified directly by PSL63 is output. If it is in the active state, the inverted level of PSL63 is output. This allows the user to adapt the polarity of an active output signal to the connected circuitry. The PSL63 bit has a shadow register to allow for updates with the T13 shadow transfer signal (T13_ST) without undesired pulses on the output lines. A read action returns the actually used value, whereas a write action targets the shadow bit. Providing a shadow register for the PSL value as well as for other values related to the generation of the PWM signal facilitates a concurrent update by software for all relevant parameters. TRPS Trap Handling Block TRPEN13 COUT63_O T13 Block Output Modulation COUT63 active passive Level Selection COUT63 PSL63 CCU6_MCA05545 ECT13O Figure 18-31 T13 Output Modulation 18.3.5 T13 Shadow Register Transfer A special shadow transfer signal (T13_ST) can be generated to facilitate updating the period and compare values of the compare channel CC63 synchronously to the operation of T13. Providing a shadow register for values defining one PWM period facilitates a concurrent update by software for all relevant parameters. The next PWM period can run with a new set of parameters. The generation of this signal is requested by software via bit TCTR0.STE13 (set by writing 1 to the write-only bit TCTR4.T13STR, cleared by writing 1 to the write-only bit TCTR4.T13STD). When signal T13_ST is active, a shadow register transfer is triggered with the next cycle of the T13 clock. Bit STE13 is automatically cleared with the shadow register transfer. A T13 shadow register transfer takes place (T13_ST active): * * while timer T13 is not running (T13R = 0), or STE13 = 1 and a Period-Match is detected while T13R = 1 User's Manual CCU6, UM_V0.5D3 18-61 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Read Period Register T13PR Read Capture/Compare Unit 6 (CCU6) Read Read PSL63 CC63PS T13IM Period Shadow Register T13PR Write Read Compare Register CC63R PSL63 Shadow Write CC63PS Shadow Write T13IM Shadow Write T13_ST Compare Shadow Register CC63SR Write Read CCU6_MCA05547 Figure 18-32 T13 Shadow Register Overview User's Manual CCU6, UM_V0.5D3 18-62 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.3.6 T13 related Registers 18.3.6.1 T13 Counter Register The generation of the patterns for a single channel pulse width modulation (PWM) is based on timer T13. The registers related to timer T13 can be concurrently updated (with well-defined conditions) in order to ensure consistency of the PWM signal. T13 can be synchronized to several timer T12 events. Timer T13 only supports compare mode on its compare channel CC63. Register T13 represents the counting value of timer T13. It can only be written while the timer T13 is stopped. Write actions while T13 is running are not taken into account. Register T13 can always be read by SW. Timer T13 only supports edge-aligned mode (counting up). T13 Timer T13 Counter Register 15 14 13 12 11 10 9 XSFR(30H) 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 T13CV rwh Field T13CV Bits [15:0] Type Description rwh Timer 13 Counter Value This register represents the 16-bit counter value of Timer13. Note: While timer T13 is stopped, the internal clock divider is reset in order to ensure reproducible timings and delays. User's Manual CCU6, UM_V0.5D3 18-63 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.3.6.2 Period Register Register T13PR contains the period value for timer T13. The period value is compared to the actual counter value of T13 and the resulting counter actions depend on the defined counting rules. This register has a shadow register and the shadow transfer is controlled by bit STE13. A read action by SW delivers the value currently used for the compare action, whereas the write action targets a shadow register. The shadow register structure allows a concurrent update of all T13-related values. T13PR Timer 13 Period Register 15 14 13 12 11 10 9 XSFR(32H) 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 T13PV rwh Field T13PV Bits [15:0] Type Description rwh T13 Period Value The value T13PV defines the counter value for T13 leading to a period-match. When reaching this value, the timer T13 is set to zero. User's Manual CCU6, UM_V0.5D3 18-64 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.3.6.3 Compare Register Registers CC63R is the actual compare register for T13. The values stored in CC63R is compared to the counter value of T13. The State Bit CC63ST is located in register CMPSTAT. CC63R Compare Register for T13 15 14 13 12 11 10 9 XSFR(34H) 8 CCV rh 7 6 5 4 Reset Value: 0000H 3 2 1 0 Field CCV Bits [15:0] Type Description rh Channel CC63 Compare Value The bit field CCV contains the value, that is compared to the T13 counter value. 18.3.6.4 Compare Shadow Register The register CC63R can only be read by SW, the modification of the value is done by a shadow register transfer from register CC63SR. The corresponding shadow register CC63SR can be read and written by SW. CC63SR Compare Shadow Register for T13 XSFR(36H) 15 14 13 12 11 10 9 8 CCS rw 7 6 5 4 Reset Value: 0000H 3 2 1 0 Field CCS Bits [15:0] Type Description rw Shadow Register for Channel CC63 Compare Value The bit field contents of CCS is transferred to the bit field CCV during a shadow transfer. User's Manual CCU6, UM_V0.5D3 18-65 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.4 Trap Handling The trap functionality permits the PWM outputs to react on the state of the input signal CTRAP. This functionality can be used to switch off the power devices if the trap input becomes active (e.g. to perform an emergency stop). The trap handling and the effect on the output modulation are controlled by the bits in the trap control register TRPCTR. The trap flags TRPF and TRPS are located in register IS and can be set/cleared by SW by writing to registers ISS and ISR. Figure 18-33 gives an overview on the trap function. The Trap Flag TRPF monitors the trap input and initiates the entry into the Trap State. The Trap State Bit TRPS determines the effect on the outputs and controls the exit of the Trap State. When a trap condition is detected (CTRAP = 0) and the input is enabled (TRPPEN = 1), both, the Trap Flag TRPF and the Trap State Bit TRPS, are set to 1 (trap state active). The output of the Trap State Bit TRPS leads to the Output Modulation Blocks (for T12 and for T13) and can there deactivate the outputs (set them to the passive state). Individual enable control bits for each of the six T12-related outputs and the T13-related output facilitate a flexible adaptation to the application needs. There are a number of different ways to exit the Trap State. This offers SW the option to select the best operation for the application. Exiting the Trap State can be done either immediately when the trap condition is removed (CTRAP = 1 or TRPPEN = 0), or under software control, or synchronously to the PWM generated by either Timer T12 or Timer T13. RTRPF CTRAP TRPPEN Trap Entry / Exit Control STRPF TRM2 TRPF T12_ZM T13_ZM Trap Exit Synchronization TRPS To T12, T13 Output Modulation TRM0/1 CCU6_MCB05541 Figure 18-33 Trap Logic Block Diagram User's Manual CCU6, UM_V0.5D3 18-66 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) Clearing of TRPF is controlled by the mode control bit TRPM2. If TRPM2 = 0, TRPF is automatically cleared by HW when CTRAP returns to the inactive level (CTRAP = 1) or if the trap input is disabled (TRPPEN = 0). When TRPM2 = 1, TRPF must be reset by SW after CTRAP has become inactive. Clearing of TRPS is controlled by the mode control bits TRPM1 and TRPM0 (located in the Trap Control Register TRPCTR). A reset of TRPS terminates the Trap State and returns to normal operation. There are three options selected by TRPM1 and TRPM0. One is that the Trap State is left immediately when the Trap Flag TRPF is cleared, without any synchronization to timers T12 or T13. The other two options facilitate the synchronization of the termination of the Trap State to the count periods of either Timer T12 or Timer T13. Figure 18-34 gives an overview on the associated operation. T12 Count T13 Count TRPF TRPS TRPS TRPS CTRAP active Sync. to T12 Sync. to T13 No sync. CCU6_MCT05542 Figure 18-34 Trap State Synchronization (with TRM2 = 0) User's Manual CCU6, UM_V0.5D3 18-67 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.5 Multi-Channel Mode The Multi-Channel mode offers the possibility to modulate all six T12-related output signals with one instruction. The bits in bit field MCMOUT.MCMP are used to specify the outputs that may become active. If Multi-Channel mode is enabled (bit MODCTR.MCMEN = 1), only those outputs may become active, that have a 1 at the corresponding bit position in bit field MCMP. This bit field has its own shadow bit field MCMOUTS.MCMPS, that can be written by software. The transfer of the new value in MCMPS to the bit field MCMP can be triggered by, and synchronized to, T12 or T13 events. This structure permits the software to write the new value, that is then taken into account by the hardware at a well-defined moment and synchronized to a PWM signal. This avoids unintended pulses due to unsynchronized modulation sources. SWSEL SWSYN Shadow Register MCMOUTS.MCMPS Shadow Transfer MCM_ST clear STRMCM T12_ZM CM_CHE T13_PM T12_PM T12_OM CM_61 set Switching Event Detection T13_ZM Switching Synchronization IDLE Register MCMOUT.MCMP R clear T12 Output Modulation CDIR STR To Interrupt Control set Outputs CC6x/COUT6x CCU6_MCB05535 Figure 18-35 Multi-Channel Mode Block Diagram Figure 18-35 shows the functional blocks for the Multi-Channel operation, controlled by bit fields in register MCMCTR. The event that triggers the update of bit field MCMP is chosen by SWSEL. In order to synchronize the update of MCMP to a PWM generated by T12 or T13, bit field SWSYN allows the selection of the synchronization event leading to the transfer from MCMPS to MCMP. Due to this structure, an update takes place with a new PWM period. A reminder flag R is set when the selected switching event occurs (the event is not necessarily synchronous to the modulating PWM), and is cleared when the transfer takes place. This flag can be monitored by software to check for the status of this logic block. User's Manual CCU6, UM_V0.5D3 18-68 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) If the shadow transfer from MCMPS to MCMP takes place, bit IS.STR becomes set and an interrupt can be generated. If it is explicitly desired, the update takes place immediately with the occurrence of the selected event when the direct synchronization mode is selected. The update can also be requested by software by writing to bit field MCMPS with the shadow transfer request bit STRMCM = 1. The option to trigger an update by SW is possible for all settings of SWSEL. By using the direct mode and bit STRMCM = 1, the update takes place completely under software control. The event selection and synchronization options are summarized in Table 18-9 and Table 18-10. Table 18-9 SWSEL 000B 001B 010B 011B 100B Multi-Channel Mode Switching Event Selection Selected Event (see register MCMCTR) No automatic event detection Correct Hall Event (CM_CHE) detected at input signals CCPOSx without additional delay T13 Period-Match (T13_PM) T12 One-Match while counting down (T12_OM and CDIR = 1) T12 Compare Channel 1 Event while counting up (CM_61 and CDIR = 0) to support the phase delay function by CC61 for block commutation mode. T12 Period-Match while counting up (T12_PM and CDIR = 0) Reserved, no action 101B 110B, 111B Table 18-10 Multi-Channel Mode Switching Synchronization SWSYN 00B 01B 10B 11B Synchronization Event (see register MCMCTR) Direct Mode: the trigger event directly causes the shadow transfer T13 Zero-Match (T13_ZM), the MCM shadow transfer is synchronized to a T13 PWM T12 Zero-Match (T12_ZM), the MCM shadow transfer is synchronized to a T12 PWM Reserved, no action User's Manual CCU6, UM_V0.5D3 18-69 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.6 Hall Sensor Mode For Brushless DC-Motors in block commutation mode, the Multi-Channel Mode has been introduced to provide efficient means for switching pattern generation. These patterns need to be output in relation to the angular position of the motor. For this, usually Hall sensors or Back-EMF sensing are used to determine the angular rotor position. The CCU6 provides three inputs, CCPOS0, CCPOS1, and CCPOS2, that can be used as inputs for the Hall sensors or the Back-EMF detection signals. There is a strong correlation between the motor position and the output modulation pattern. When a certain position of the motor has been reached, indicated by the sampled Hall sensor inputs (the Hall pattern), the next, pre-determined Multi-Channel Modulation pattern has to be output. Because of different machine types, the modulation pattern for driving the motor can vary. Therefore, it is wishful to have a wide flexibility in defining the correlation between the Hall pattern and the corresponding Modulation pattern. Furthermore, a hardware mechanism significantly reduces the CPU for blockcommutation. The CCU6 offers the flexibility by having a register containing the currently assumed Hall pattern (CURH), the next expected Hall pattern (EXPH) and the corresponding output pattern (MCMP). A new Modulation pattern is output when the sampled Hall inputs match the expected ones (EXPH). To detect the next rotation phase (segment for block commutation), the CCU6 monitors the Hall inputs for changes. When the next expected Hall pattern is detected, the next corresponding Modulation pattern is output. To increase for noise immunity (to a certain extend), the CCU6 offers the possibility to introduce a sampling delay for the Hall inputs. Some changes of the Hall inputs are not leading to the expected Hall pattern, because they are only short spikes due to noise. The Hall pattern compare logic compares the Hall inputs to the next expected pattern and also to the currently assumed pattern to filter out spikes. For the Hall and Modulation output patterns, a double-register structure is implemented. While register MCMOUT holds the actually used values, its shadow register MCMOUTS can be loaded by software from a pre-defined table, holding the appropriate Hall and Modulation patterns for the given motor control. A transfer from the shadow register into register MCMOUT can take place when a correct Hall pattern change is detected. Software can then load the next values into register MCMOUTS. It is also possible by software to force a transfer from MCMOUTS into MCMOUT. Note: The Hall input signals CCPOSx and the CURH and EXPH bit fields are arranged in the following order: CCPOS0 corresponds to CURH.0 (LSB) and EXPH.0 (LSB) CCPOS1 corresponds to CURH.1 and EXPH.1 CCPOS2 corresponds to CURH.2 (MSB) and EXPH.2 (MSB) User's Manual CCU6, UM_V0.5D3 18-70 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.6.1 Hall Pattern Evaluation The Hall sensor inputs CCPOSx can be permanently monitored via an edge detection block (with the module clock fCC6). In order to suppress spikes on the Hall inputs due to noise in rugged inverter environment, two optional noise filtering methods are supported by the Hall logic (both methods can be combined). * Noise filtering with delay: For this function, the mode control bit fields MSEL6x for all T12 compare channels must be programmed to 1000B and DBYP = 0. The selected event triggers DeadTime Counter 0 to generate a programmable delay (defined by bit field DTM). When the delay has elapsed, the evaluation signal HCRDY becomes activated. Output modulation with T12 PWM signals is not possible in this mode. Noise filtering by synchronization to PWM: The Hall inputs are not permanently monitored by the edge detection block, but samples are taken only at defined points in time during a PWM period. This can be used to sample the Hall inputs when the switching noise (due to PWM) does not disturb the Hall input signals. * If neither the delay function of Dead-Time Counter 0 is not used for the Hall pattern evaluation nor the Hall mode for Brushless DC-Drive control is enabled, the timer T12 block is available for PWM generation and output modulation. CCPOS 0..2 Hall Compare Logic HCRDY Edge Hall Inputs Hall Pattern Evaluation Detect CM_63 T13_PM T12_PM T12_OM CM_61 Event Selection CDIR Dead-Time Counter 0 fCC6 Delay Bypass HSYNC DBYP CCU6_MCB05553 Figure 18-36 Hall Pattern Evaluation If the evaluation signal HCRDY (Hall Compare Ready, see Figure 18-37) becomes activated, the Hall inputs are sampled and the Hall compare logic starts the evaluation of the Hall inputs. User's Manual CCU6, UM_V0.5D3 18-71 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) Figure 18-36 illustrates the events for Hall pattern evaluation and the noise filter logic, Table 18-11 summarizes the selectable trigger input signals. Table 18-11 Hall Sensor Mode Trigger Event Selection HSYNC 000B 001B 010B 011B 100B 101B 110B 111B Selected Event (see register T12MSEL) Any edge at any of the inputs CCPOSx, independent from any PWM signal (permanent check). A T13 Compare-Match (CM_63). A T13 Period-Match (T13_PM). Hall sampling triggered by HW sources is switched off. A T12 Period-Match while counting up (T12_PM and CDIR = 0). A T12 One-Match while counting down (T12_OM and CDIR = 1). A T12 Compare-Match of compare channel CC61 while counting up (CM_61 and CDIR = 0). A T12 Compare-Match of compare channel CC61 while counting down (CM_61 and CDIR = 1). User's Manual CCU6, UM_V0.5D3 18-72 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.6.2 Hall Pattern Compare Logic Figure 18-37 gives an overview on the double-register structure and the pattern compare logic. Software writes the next modulation pattern (MCMPS) and the corresponding current (CURHS) and expected (EXPHS) Hall patterns into the shadow register MCMOUTS. Register MCMOUT holds the actually used values CURH and EXPH. The modulation pattern MCMP is provided to the T12 Output Modulation block. The current (CURH) and expected (EXPH) Hall patterns are compared to the sampled Hall sensor inputs (visible in register CMPSTAT). Sampling of the inputs and the evaluation of the comparator outputs is triggered by the evaluation signal HCRDY (Hall Compare Ready), that is detailed in the next section. Multi-Channel Mode Logic SW Write SW Write CURHS EXPHS SW Write MCMPS HP_ST MCM_ST Hall Pattern Evaluation CURH EXPH MCMP clear HCRDY Hall Inputs CCPOS0..2 Sample T12 Output Modulation CM_CHE Pattern Compare CM_WHE IDLE Hall Compare Logic CCU6_MCA05536 Figure 18-37 Hall Pattern Compare Logic * * If the sampled Hall pattern matches the value programmed in CURH, the detected transition was a spike (no Hall event) and no further actions are necessary. If the sampled Hall pattern matches the value programmed in EXPH, the detected transition was the expected event (correct Hall event CM_CHE) and the MCMP value has to change. If the sampled Hall pattern matches neither CURH nor EXPH, the transition was due to a major error (wrong Hall event CM_CWE) and can lead to an emergency shut down (IDLE). 18-73 V1.0, 2007-06 * User's Manual CCU6, UM_V0.5D3 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) At every correct Hall event (CM_CHE), the next Hall patterns are transferred from the shadow register MCMOUTS into MCMOUT (Hall pattern shadow transfer HP_ST), and a new Hall pattern with its corresponding output pattern can be loaded (e.g. from a predefined table in memory) by software into MCMOUTS. For the Modulation patterns, signal MCM_ST is used to trigger the transfer. Loading this shadow register can also be done by writing MCMOUTS.STRHP = 1 (for EXPH and CURH) or MCMOUTS.STRMCMP = 1 (for MCMP). 18.6.3 Hall Mode Flags Depending on the Hall pattern compare operation, a number of flags are set in order to indicate the status of the module and to trigger further actions and interrupt requests. Flag IS.CHE (Correct Hall Event) is set by signal CM_CHE when the sampled Hall pattern matches the expected one (EXPH). This flag can also be set by SW by setting bit ISS.SCHE = 1. If enabled by bit IEN.ENCHE = 1, the set signal for CHE can also generate an interrupt request to the CPU. Bit field INP.INPCHE defines which service request output becomes activated in case of an interrupt request.To clear flag CHE, SW needs to write ISR.RCHE = 1. Flag IS.WHE indicates a Wrong Hall Event. Its handling for flag setting and resetting as well as interrupt request generation are similar to the mechanism for flag CHE. The implementation of flag STR is done in the same way as for CHE and WHE. This flag is set by HW by the shadow transfer signal MCM_ST (see also Figure 18-35). Please note that for flags CHE, WHE, and STR, the interrupt request generation is triggered by the set signal for the flag. That means, a request can be generated even if the flag is already set. There is no need to clear the flag in order to enable further interrupt requests. The implementation for the IDLE flag is different. It is set by HW through signal CM_WHE if enabled by bit ENIDLE. Software can also set the flag via bit SIDLE. As long as bit IDLE is set, the modulation pattern field MCMP is cleared to force the outputs to the passive state. Flag IDLE must be cleared by software by writing RIDLE = 1 in order to return to normal operation. To fully restart from IDLE mode, the transfer requests for the bit fields in register MCMOUTS to register MCMOUT have to be initiated by software via bits STRMCM and STRHP in register MCMOUTS. In this way, the release from IDLE mode is under software control, but can be performed synchronously to the PWM signal. User's Manual CCU6, UM_V0.5D3 18-74 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Clear _ >1 Capture/Compare Unit 6 (CCU6) RCHE SCHE CM_CHE CHE Set INPCHE To SR0 To SR1 To SR2 ENCHE To SR3 Hall Compare Logic RWHE SWHE _ >1 Clear WHE Set INPERR To SR0 To SR1 To SR2 ENWHE To SR3 CM_WHE ENIDLE SIDLE RIDLE _ >1 Set IDLE Clear Clear MCMP CCU6_MCA05540 Figure 18-38 Hall Mode Flags User's Manual CCU6, UM_V0.5D3 18-75 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.6.4 Hall Mode for Brushless DC-Motor Control The CCU6 provides a mode for the Timer T12 Block especially targeted for convenient control of block commutation patterns for Brushless DC-Motors. This mode is selected by setting all T12MSEL.MSEL6x bit fields of the three T12 Channels to 1000B. In this mode, illustrated in Figure 18-39, channel CC60 is placed in capture mode to measure the time elapsed between the last two correct Hall events, channel CC61 in compare mode to provide a programmable phase delay between the Hall event and the application of a new PWM output pattern, and channel CC62 also in compare mode as first time-out criterion. A second time-out criterion can be built by the T12 period match event. Clear fT12 Counter Register T12 Hall Compare Logic CM_CHE CM_61 Comp. =? Comp. =? CM_62 Capture Register CC60R Compare Register CC61R Compare Register CC62R Compare Shadow Register CC61SR Compare Shadow Register CC62SR CCU6_MCA05538 Figure 18-39 T12 Block in Hall Sensor Mode The signal CM_CHE from the Hall compare logic is used to transfer the new compare values from the shadow registers CC6xSR into the actual compare registers CC6xR, performs the shadow transfer for the T12 period register, to capture the current T12 contents into register CC60R, and to clear T12. Note: In this mode, the shadow transfer signal T12_ST is not generated. Not all shadow bits, such as the PSLy bits, will be transferred to their main registers. To program the main registers, SW needs to write to these registers while Timer T12 is stopped. In this case, a SW write actualizes both registers. User's Manual CCU6, UM_V0.5D3 18-76 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) Hall Event captures and resets T12 CC62 Comp. T12 Count CC61 Comp. 0000 H CCPOS0 CCPOS1 CCPOS2 CURH EXPH MCMP CC6x COUT6y 1 0 1 = 101 = 001 1 0 0 = 001 = 011 1 1 0 = 011 = 010 0 1 0 CC62 Compare for Time-Out CC61 Compare for Phase Delay 0 1 1 = 110 = 100 0 0 = 010 = 110 Phase Delay CCU6_MCT05539 Figure 18-40 Brushless DC-Motor Control Example (all MSEL6x = 1000B) After the detection of an expected Hall pattern (CM_CHE active), the T12 count value is captured into channel CC60 (representing the actual rotor speed by measuring the elapsed time between the last two correct Hall events), and T12 is reset. When the timer reaches the compare value in channel CC61, the next multi-channel state is switched by triggering the shadow transfer of bit field MCMP (if enabled in bit field SWEN). This trigger event can be combined with the synchronization of the next multi-channel state to the PWM source (to avoid spikes on the output lines, see Section 18.5). This compare function of channel CC61 can be used as a phase delay from the position sensor input signals to the switching of the output signals, that is necessary if a sensorless back-EMF technique or Hall sensors are used. The compare value in channel CC62 can be used as a time-out trigger (interrupt), indicating that the actual motor speed is far below the desired destination value. An abnormal load change can be detected with this feature and PWM generation can be disabled. User's Manual CCU6, UM_V0.5D3 18-77 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.7 18.7.1 Modulation Control Registers Modulation Control This register contains bits enabling the modulation of the corresponding output signal by PWM pattern generated by the timers T12 and T13. Furthermore, the multi-channel mode can be enabled as additional modulation source for the output signals. MODCTR Modulation Control Register 15 ECT 13O rw 14 0 r 13 12 11 10 9 XSFR(40H) 8 7 MCM EN rw 6 0 r 5 4 Reset Value: 0000H 3 2 1 0 T13MODEN rw T12MODEN rw Field T12MODEN Bits [5:0] Type Description rw T12 Modulation Enable These bits enable the modulation of the corresponding output signal by a PWM pattern generated by timer T12. T12MODEN0 = MODCTR.0 for output CC60 T12MODEN1 = MODCTR.1 for output COUT60 T12MODEN2 = MODCTR.2 for output CC61 T12MODEN3 = MODCTR.3 for output COUT61 T12MODEN4 = MODCTR.4 for output CC62 T12MODEN5 = MODCTR.5 for output COUT62 0B The modulation of the corresponding output signal by a T12 PWM pattern is disabled. 1B The modulation of the corresponding output signal by a T12 PWM pattern is enabled. Multi-Channel Mode Enable 0B The modulation of the corresponding output signal by a multi-channel pattern according to bit field MCMOUT is disabled. 1B The modulation of the corresponding output signal by a multi-channel pattern according to bit field MCMOUT is enabled. MCMEN 7 rw User's Manual CCU6, UM_V0.5D3 18-78 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field T13MODEN Bits [13:8] Type Description rw T13 Modulation Enable These bits enable the modulation of the corresponding output signal by the PWM pattern CC63_O generated by timer T13. T13MODEN0 = MODCTR.8 for output CC60 T13MODEN1 = MODCTR.9 for output COUT60 T13MODEN2 = MODCTR.10 for output CC61 T13MODEN3 = MODCTR.11 for output COUT61 T13MODEN4 = MODCTR.12 for output CC62 T13MODEN5 = MODCTR.13 for output COUT62 The modulation of the corresponding output 0B signal by a T13 PWM pattern is disabled. 1B The modulation of the corresponding output signal by a T13 PWM pattern is enabled. Enable Compare Timer T13 Output The output COUT63 is in the passive state. 0B 1B The output COUT63 is enabled for the PWM signal generated by T13. reserved; returns 0 if read; should be written with 0; Capture/Compare Unit 6 (CCU6) ECT13O 15 rw 0 6, 14 r User's Manual CCU6, UM_V0.5D3 18-79 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.7.2 Trap Control Register The register TRPCTR controls the trap functionality. It contains independent enable bits for each output signal and control bits to select the behavior in case of a trap condition. The trap condition is a low level on the CTRAP input pin, that is monitored (inverted level) by bit IS.TRPF. While TRPF=1 (trap input active), the trap state bit IS.TRPS is set to 1. TRPCTR Trap Control Register 15 14 13 12 11 10 9 XSFR(42H) 8 7 6 5 0 r 4 Reset Value: 0000H 3 2 1 0 TRP TRP EN PEN 13 rw rw TRPEN rw TRP TRP TRP M2 M1 M0 rw rw rw Field TRPM1, TRPM0 Bits 1, 0 Type Description rw Trap Mode Control Bits 1, 0 These two bits define the behavior of the selected outputs when leaving the trap state after the trap condition has become inactive again. A synchronization to the timer driving the PWM pattern avoids unintended pulses when leaving the trap state. The combination [TRPM1, TRPM0] leads to: 00B The trap state is left (return to normal operation) after TRPF has become 0 again when a zero-match of T12 (while counting up) is detected (synchronization to T12). 01B The trap state is left (return to normal operation) after TRPF has become 0 again when a zero-match of T13 is detected (synchronization to T13). 10B reserved 11B The trap state is left (return to normal operation) immediately after TRPF has become 0 again without any synchronization to T12 or T13. User's Manual CCU6, UM_V0.5D3 18-80 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field TRPM2 Bits 2 Type Description rw Trap Mode Control Bit 2 This bit defines how the trap flag TRPF can be cleared after the trap input condition (CTRAP = 0 and TRPPEN = 1) is no longer valid (either by CTRAP = 1 or by TRPPEN = 0). 0B Automatic Mode: Bit TRPF is cleared by HW if the trap input condition is no longer valid. 1B Manual Mode: Bit TRPF stays 0 after the trap input condition is no longer valid. It has to be cleared by SW by writing ISR.RTRPF = 1. Trap Enable Control Setting a bit enables the trap functionality for the following corresponding output signals: TRPEN0 = TRPCTR.8 for output CC60 TRPEN1 = TRPCTR.9 for output COUT60 TRPEN2 = TRPCTR.10 for output CC61 TRPEN3 = TRPCTR.11 for output COUT61 TRPEN4 = TRPCTR.12 for output CC62 TRPEN5 = TRPCTR.13 for output COUT62 0B The trap functionality of the corresponding output signal is disabled. The output state is independent from bit IS.TRPS. The trap functionality of the corresponding 1B output signal is enabled. The output state is set to the passive while IS.TRPS=1. Trap Enable Control for Timer T13 0B The trap functionality for output COUT63 is disabled. The output state is independent from bit IS.TRPS. 1B The trap functionality for output COUT63 is enabled. The output state is set to the passive while IS.TRPS=1. Capture/Compare Unit 6 (CCU6) TRPEN [13:8] rw TRPEN13 14 rw User's Manual CCU6, UM_V0.5D3 18-81 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field TRPPEN Bits 15 Type Description rw Trap Pin Enable This bit enables the input (pin) function for the trap generation. An interrupt can only be generated if a falling edge is detected at pin CTRAP while TRPPEN = 1. 0B The CCU6 trap functionality based on the input CTRAP is disabled. A CCU6 trap can only be generated by SW by setting bit TRPF. 1B The CCU6 trap functionality based on the input CTRAP is enabled. A CCU6 trap can be generated by SW by setting bit TRPF or by CTRAP=0. reserved; returns 0 if read; should be written with 0; Capture/Compare Unit 6 (CCU6) 0 [7:3] r User's Manual CCU6, UM_V0.5D3 18-82 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.7.3 Passive State Level Register Register PSLR defines the passive state level of the PWM outputs of the module. The passive state level is the value that is driven during the passive state of the output. During the active state, the corresponding output pin drives the active state level, that is the inverted passive state level. The passive state level permits to adapt the driven output levels to the driver polarity (inverted, not inverted) of the connected power stage. The bits in this register have shadow bit fields to permit a concurrent update of all PWMrelated parameters (bit field PSL is updated with T12_ST, whereas PSL63 is updated with T13_ST). The actually used values can be read (attribute "rh"), whereas the shadow bits can only be written (attribute "w"). PSLR Passive State Level Register 15 14 13 12 0 r 11 10 9 XSFR(44H) 8 7 PSL 63 rwh 6 0 r 5 4 Reset Value: 0000H 3 PSL rwh 2 1 0 Field PSL Bits [5:0] Type Description rwh Compare Outputs Passive State Level These bits define the passive level driven by the module outputs during the passive state. PSL0 = PSLR.0 for output CC60 PSL1 = PSLR.1 for output COUT60 PSL2 = PSLR.2 for output CC61 PSL3 = PSLR.3 for output COUT61 PSL4 = PSLR.4 for output CC62 PSL5 = PSLR.5 for output COUT62 0B The passive level is 0. 1B The passive level is 1. Passive State Level of Output COUT63 This bit defines the passive level driven by the module output COUT63 during the passive state. The passive level is 0. 0B 1B The passive level is 1. reserved; returns 0 if read; should be written with 0; PSL63 7 rwh 0 6, [15:8] r User's Manual CCU6, UM_V0.5D3 18-83 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.7.4 Multi-Channel Mode Registers Register MCMCTR contains control bits for the multi-channel functionality. MCMCTR Multi-Channel Mode Control Register XSFR(4EH) 15 14 13 12 11 0 r 10 9 8 7 6 5 4 Reset Value: 0000H 3 0 r 2 1 SWSEL rw 0 SWSYN rw Field SWSEL Bits [2:0] Type Description rw Switching Selection Bit field SWSEL selects one of the following trigger request sources (next multi-channel event) for the shadow transfer MCM_ST from MCMPS to MCMP. The trigger request is stored in the reminder flag R until the shadow transfer is done and flag R is cleared automatically with the shadow transfer. The shadow transfer takes place synchronously with an event selected in bit field SWSYN. 000B No trigger request will be generated 001B Correct Hall pattern detected (CM_CHE) 010B T13 period-match detected (while counting up) 011B T12 one-match (while counting down) 100B T12 channel 1 compare-match detected (phase delay function) 101B T12 period match detected (while counting up) else reserved, no trigger request will be generated User's Manual CCU6, UM_V0.5D3 18-84 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field SWSYN Bits [5:4] Type Description rw Switching Synchronization Bit field SWSYN defines the synchronization mechanism of the shadow transfer event MCM_ST if it has been requested before (flag R set by an event selected by SWSEL) and if MCMEN = 1. This feature permits the synchronization of the outputs to the PWM source, that is used for modulation (T12 or T13). 00B Direct; the trigger event immediately leads to the shadow transfer 01B T13 zero-match triggers the shadow transfer 10B a T12 zero-match (while counting up) triggers the shadow transfer 11B reserved; no action reserved; returns 0 if read; should be written with 0; Capture/Compare Unit 6 (CCU6) 0 3, [15:6] r User's Manual CCU6, UM_V0.5D3 18-85 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) Register MCMOUTS contains bits used as pattern input for the multi-channel mode and the Hall mode. This register is a shadow register (that can be read and written) for register MCMOUT, indicating the currently active signals. MCMOUTS Multi-Channel Mode Output Shadow Register XSFR(4AH) 15 STR HP w 14 0 r 13 12 CURHS rw 11 10 9 EXPHS rw 8 7 STR MCM w 6 0 r 5 4 Reset Value: 0000H 3 2 1 0 MCMPS rw Field MCMPS Bits [5:0] Type Description rw Multi-Channel PWM Pattern Shadow Bit field MCMPS is the shadow bit field for bit field MCMP. The multi-channel shadow transfer is triggered by MCM_ST according to the transfer conditions defined by register MCMCTR. Shadow Transfer Request for MCMPS Writing STRMCM = 1 leads to an immediate activation of MCM_ST to update bit field MCMP by the value of MCMPS. When read, this bit always delivers 0. 0B No action. 1B Bit field MCMP is updated. Expected Hall Pattern Shadow Bit field EXPHS is the shadow bit field for bit field EXPH. The shadow transfer takes place when a correct Hall event is detected (CM_CHE). Current Hall Pattern Shadow Bit field CURHS is the shadow bit field for bit field CURH. The shadow transfer takes place when a correct Hall event is detected (CM_CHE). STRMCM 7 w EXPHS [10:8] rw CURHS [13:11] rw User's Manual CCU6, UM_V0.5D3 18-86 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field STRHP Bits 15 Type Description w Shadow Transfer Request for the Hall Pattern Writing STRHP = 1 leads to an immediate activation of HP_ST to update bit fields EXPH and CURH by EXPHS and CURHS. When read, this bit always delivers 0. No action. 0B 1B Bit fields EXPH and CURH are updated. reserved; returns 0 if read; should be written with 0; Capture/Compare Unit 6 (CCU6) 0 6, 14 r MCMOUT Multi-Channel Mode Output Register XSFR(4CH) 15 0 r 14 13 12 CURH rh 11 10 9 EXPH rh 8 7 0 r 6 R rh 5 4 Reset Value: 0000H 3 2 1 0 MCMP rh Field MCMP Bits [5:0] Type Description rh Multi-Channel PWM Pattern Bit field MCMP defines the output pattern for the multi-channel mode. If this mode is enabled by MODCTR.MCMEN = 1, the output state of all T12 related PWM outputs can be modified. This bit field is 0 while IS.IDLE = 1. MCMP0 = MCMOUT.0 for output CC60 MCMP1 = MCMOUT.1 for output COUT60 MCMP2 = MCMOUT.2 for output CC61 MCMP3 = MCMOUT.3 for output COUT61 MCMP4 = MCMOUT.4 for output CC62 MCMP5 = MCMOUT.5 for output COUT62 0B The output is set to the passive state. A PWM generated by T12 or T13 are not taken into account. 1B The output can be in the active state, depending on the enabled PWM modulation signals generated by T12, T13 and the trap state. 18-87 V1.0, 2007-06 User's Manual CCU6, UM_V0.5D3 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field R Bits 6 Type Description rh Reminder Flag This flag indicates that the shadow transfer from MCMPS to MCMP has been requested by the selected trigger source. It is cleared when the shadow transfer takes place or while MCMEN=0. A shadow transfer MCM_ST is not requested. 0B 1B A shadow transfer MCM_ST is requested, but has not yet been executed, because the selected synchronization condition has not yet occurred. Expected Hall Pattern Bit field EXPH is updated by a shadow transfer HP_ST from bit field EXPHS. If HCRDY = 1, EXPH is compared to the sampled CCPOSx inputs in order to detect the occurrence of the next desired (=expected) hall pattern or a wrong pattern. If the sampled hall pattern at the hall input pins is equal to bit field EXPH, a correct Hall event has been detected (CM_CHE). Current Hall Pattern Bit field CURH is updated by a shadow transfer HP_ST from bit field CURHS. If HCRDY = 1, CURH is compared to the sampled CCPOSx inputs in order to detect a spike. If the sampled Hall pattern at the Hall input pins is equal to bit field CURH, no Hall event has been detected. If the sampled Hall input pattern is neither equal to CURH nor equal to EXPH, the Hall event was not the desired one and may be due to a fatal error (e.g. blocked rotor, etc.). In this case, a wrong Hall event has been detected (CM_WHE). reserved; returns 0 if read; should be written with 0; Capture/Compare Unit 6 (CCU6) EXPH [10:8] rh CURH [13:11] rh 0 7, r [15:14] User's Manual CCU6, UM_V0.5D3 18-88 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.8 Interrupt Handling This section describes the interrupt handling of the CCU6 module. 18.8.1 Interrupt Structure The HW interrupt event or the SW setting of the corresponding interrupt set bit (in register ISS) sets the event indication flags (in register IS) and can trigger the interrupt generation. The interrupt pulse is generated independently from the interrupt status flag in register IS (it is not necessary to clear the related status bit to be able to generate another interrupt). The interrupt flag can be cleared by SW by writing to the corresponding bit in register ISR. If enabled by the related interrupt enable bit in register IEN, an interrupt pulse can be generated on one of the four service request outputs (SR0 to SR3) of the module. If more than one interrupt source is connected to the same interrupt node pointer (in register INP), the requests are logically OR-combined to one common service request output (see Figure 18-41). SW Requests Clear Interrupt Clear Set Interrupt _ >1 HW Interrupt Event Interrupt Status Set Interrupt Enable Interrupt Node Pointer To SR0 To SR1 To SR2 To SR3 CCU6_MCA05549 Figure 18-41 General Interrupt Structure The available interrupt events in the CCU6 are shown in Figure 18-42. User's Manual CCU6, UM_V0.5D3 18-89 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) T12_PM T12 Counter T12_OM SR0 Interrupt Request Reg. CC6x_0IC Interrupt Request Reg. CC6x_1IC Interrupt Request Reg. CC6x_2IC Interrupt Request Reg. CC6x_3IC CDIR T12 Capture Compare Channels CC6x CC6x_R CC6x_F SR1 SR2 T13 Counter T13_PM SR3 T13 Compare Channel CC63 CM_63 Interrupt Control Logic Interrupt Set Register ISS Interrupt Status Register IS Multi-Channel Mode Logic STR Interrupt Reset Register ISR Interrupt Enable Register IEN Node Pointer Register INP CCU6_MCA05548 CM_CHE Hall Compare Logic CM_WHE TRPF Trap Handling TRPS Figure 18-42 Interrupt Sources and Events User's Manual CCU6, UM_V0.5D3 18-90 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.8.2 Interrupt Registers 18.8.2.1 Interrupt Status Register Register IS contains the individual interrupt request bits. This register can only be read, write actions have no impact on the contents of this register. The SW can set or clear the bits individually by writing to the registers ISS (to set the bits) or to register ISR (to clear the bits). The interrupt generation is independent from the value of the bits in register IS, e.g. the interrupt will be generated (if enabled) even if the corresponding bit is already set. The trigger for an interrupt generation is the detection of a set condition (by HW or SW) for the corresponding bit in register IS. In compare mode (and hall mode), the timer-related interrupts are only generated while the timer is running (T1xR=1). In capture mode, the capture interrupts are also generated while the timer T12 is stopped. Note: Not all bits in register IS can generate an interrupt. Other status bits have been added, that have a similar structure for their set and clear actions. It is recommended that SW checks the interrupt bits bit-wisely (instead of common OR over the bits). IS Interrupt Status Register 15 14 13 12 11 10 9 XSFR(50H) 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 STR IDLE WHE CHE rh rh rh rh TRP TRP T13 T13 T12 T12 ICC ICC ICC ICC ICC ICC S F PM CM PM OM 62F 62R 61F 61R 60F 60R rh rh rh rh rh rh rh rh rh rh rh rh Field ICC60R, ICC61R, ICC62R Bits 0, 2, 4 Type Description rh Capture, Compare-Match Rising Edge Flag This bit indicates that event CC6x_R has been detected. This event occurs in compare mode when a compare-match is detected while T12 is counting up (CM_6x and CDIR = 0) and in capture mode when a rising edge is detected at the related input CC6xIN. 0B The event has not yet been detected. 1B The event has been detected. User's Manual CCU6, UM_V0.5D3 18-91 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field ICC60F, ICC61F, ICC62F Bits 1, 3, 5 Type Description rh Capture, Compare-Match Falling Edge Flag This bit indicates that event CC6x_F has been detected. This event occurs in compare mode when a compare-match is detected while T12 is counting down (CM_6x and CDIR = 1) and in capture mode when a falling edge is detected at the related input CC6xIN. 0B The event has not yet been detected. The event has been detected. 1B Timer T12 One-Match Flag This bit indicates that a timer T12 one-match while counting down (T12_OM and CDIR = 1) has been detected. 0B The event has not yet been detected. 1B The event has been detected. Timer T12 Period-Match Flag This bit indicates that a timer T12 period-match while counting up (T12_PM and CDIR = 0) has been detected. The event has not yet been detected. 0B 1B The event has been detected. Timer T13 Compare-Match Flag This bit indicates that a timer T13 compare-match (CM_63) has been detected. 0B The event has not yet been detected. 1B The event has been detected. Timer T13 Period-Match Flag This bit indicates that a timer T13 period-match (T13_PM) has been detected. The event has not yet been detected. 0B 1B The event has been detected. Trap Flag This bit indicates if a trap condition (input CTRAP = 0 or by SW) is / has been detected. If TRM2= 0, it becomes cleared automatically if CTRAP = 1 or TRPPEN = 0, whereas if TRM2 = 1, it has to be cleared by writing RTRPF = 1. 0B The trap condition has not been detected. 1B The trap condition is / has been detected. 18-92 V1.0, 2007-06 Capture/Compare Unit 6 (CCU6) T12OM 6 rh T12PM 7 rh T13CM 8 rh T13PM 9 rh TRPF 10 rh User's Manual CCU6, UM_V0.5D3 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field TRPS Bits 11 Type Description rh Trap State1) This bit indicates the actual trap state. It is set if TRPF = 1 and becomes cleared according to the mode selected in register TRPCTR. 0B The trap state is not active. 1B The trap state is active. Correct Hall Event This bit indicates that a correct Hall event (CM_CHE) has been detected. The event has not yet been detected. 0B 1B The event has been detected. Wrong Hall Event This bit indicates that a wrong Hall event (CM_WHE) has been detected. 0B The event has not yet been detected. 1B The event has been detected. IDLE State If enabled by ENIDLE = 1, this bit is set together with bit WHE and it has to be cleared by SW. 0B No action. 1B Bit field MCMP is cleared, the selected outputs are set to passive state. Multi-Channel Mode Shadow Transfer Request This bit indicates that a shadow transfer from MCMPS to MCMP (MCM_ST) has taken place. 0B The event has not yet been detected. 1B The event has been detected. Capture/Compare Unit 6 (CCU6) CHE 12 rh WHE 13 rh IDLE 14 rh STR 15 rh 1) During the trap state, the selected outputs are set to the passive state. The logic level driven during the passive state is defined by the corresponding bit in register PSLR. Bits TRPS=1 and TRPF=0 can occur if the trap condition is no longer active but the selected synchronization has not yet taken place. User's Manual CCU6, UM_V0.5D3 18-93 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.8.2.2 Interrupt Status Set Register Register ISS contains individual interrupt request set bits to generate a CCU6 interrupt request by software. Writing a 1 sets the bit(s) in register IS at the corresponding bit position(s) and can generate an interrupt event (if available and enabled). All bit positions read as 0. ISS Interrupt Status Set Register 15 14 13 12 11 10 9 XSFR(52H) 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 S S S S S S S S S S S S S S S S TRP T13 T13 T12 T12 CC CC CC CC CC CC STR IDLE WHE CHE WHC F PM CM PM OM 62F 62R 61F 61R 60F 60R w w w w w w w w w w w w w w w w w Field SCC60R SCC61R, SCC62R SCC60F, SCC61F, SCC62F ST12OM Bits 0, 2, 4 1, 3, 5 6 Type Description w Set Capture, Compare-Match Rising Edge Flag 0B No action 1B Bit CC6xR will be set. Set Capture, Compare-Match Falling Edge Flag 0B No action 1B Bit CC6xF will be set. Set Timer T12 One-Match Flag 0B No action 1B Bit T12OM will be set. Set Timer T12 Period-Match Flag 0B No action 1B Bit T12PM will be set. Set Timer T13 Compare-Match Flag 0B No action 1B Bit T13CM will be set. Set Timer T13 Period-Match Flag No action 0B 1B Bit T13PM will be set. Set Trap Flag 0B No action 1B Bits TRPF and TRPS will be set. w w ST12PM 7 w ST13CM 8 w ST13PM 9 w STRPF 10 w User's Manual CCU6, UM_V0.5D3 18-94 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field SWHC Bits 11 Type Description w Software Hall Compare 0B No action 1B The Hall compare action is triggered. Set Correct Hall Event Flag No action 0B Bit CHE will be set. 1B Set Wrong Hall Event Flag 0B No action 1B Bit WHE will be set. Set IDLE Flag 0B No action 1B Bit IDLE will be set. Set STR Flag 0B No action 1B Bit STR will be set. Capture/Compare Unit 6 (CCU6) SCHE 12 w SWHE 13 w SIDLE 14 w SSTR 15 w User's Manual CCU6, UM_V0.5D3 18-95 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.8.2.3 Status Reset Register Register ISR contains bits to individually clear the interrupt event flags by software. Writing a 1 clears the bit(s) in register IS at the corresponding bit position(s). All bit positions read as 0. ISR Interrupt Status Reset Register 15 14 13 12 11 0 r 10 9 XSFR(54H) 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 R R R R STR IDLE WHE CHE w w w w R R R R R R R R R R R TRP T13 T13 T12 T12 CC CC CC CC CC CC F PM CM PM OM 62F 62R 61F 61R 60F 60R w w w w w w w w w w w w Field RCC60R, RCC61R, RCC62R RCC60F, RCC61F, RCC62F RT12OM Bits 0, 2, 4 1, 3, 5 6 Type Description w Reset Capture, Compare-Match Rising Edge Flag 0B No action 1B Bit CC6xR will be cleared. Reset Capture, Compare-Match Falling Edge Flag No action 0B 1B Bit CC6xF will be cleared. Reset Timer T12 One-Match Flag 0B No action 1B Bit T12OM will be cleared. Reset Timer T12 Period-Match Flag 0B No action 1B Bit T12PM IS will be cleared. Reset Timer T13 Compare-Match Flag 0B No action 1B Bit T13CM will be cleared. Reset Timer T13 Period-Match Flag No action 0B 1B Bit T13PM will be cleared. Reset Trap Flag 0B No action 1B Bit TRPF will be cleared (not taken into account while input CTRAP=0 and TRPPEN=1. w w RT12PM 7 w RT13CM 8 w RT13PM 9 w RTRPF 10 w User's Manual CCU6, UM_V0.5D3 18-96 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field RCHE Bits 12 Type Description w Reset Correct Hall Event Flag 0B No action 1B Bit CHE will be cleared. Reset Wrong Hall Event Flag No action 1B Bit WHE will be cleared. 0B Reset IDLE Flag 0B No action 1B Bit IDLE will be cleared. Reset STR Flag 0B No action 1B Bit STR will be cleared. reserved; returns 0 if read; should be written with 0; Capture/Compare Unit 6 (CCU6) RWHE 13 w RIDLE 14 w RSTR 15 w 0 11 r User's Manual CCU6, UM_V0.5D3 18-97 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.8.2.4 Interrupt Enable Register Register IEN contains the interrupt enable bits and a control bit to enable the automatic idle function in the case of a wrong hall pattern. IEN Interrupt Enable Register 15 14 13 12 11 0 r 10 9 XSFR(58H) 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 EN EN EN EN STR IDLE WHE CHE rw rw rw rw EN EN EN EN EN EN EN EN EN EN EN TRP T13 T13 T12 T12 CC CC CC CC CC CC F PM CM PM OM 62F 62R 61F 61R 60F 60R rw rw rw rw rw rw rw rw rw rw rw Field ENCC60R, ENCC61R, ENCC62R Bits 0, 2, 4 Type Description rw Capture, Compare-Match Rising Edge Interrupt Enable for Channel CC6x 0B No interrupt will be generated if the set condition for bit CC6xR in register IS occurs. 1B An interrupt will be generated if the set condition for bit CC6xR in register IS occurs. The service request output that will be activated is selected by bit field INPCC6x. Capture, Compare-Match Falling Edge Interrupt Enable for Channel CC6x 0B No interrupt will be generated if the set condition for bit CC6xF in register IS occurs. 1B An interrupt will be generated if the set condition for bit CC6xF in register IS occurs. The service request output that will be activated is selected by bit field INPCC6x. Enable Interrupt for T12 One-Match 0B No interrupt will be generated if the set condition for bit T12OM in register IS occurs. 1B An interrupt will be generated if the set condition for bit T12OM in register IS occurs. The service request output that will be activated is selected by bit field INPT12. ENCC60F, ENCC61F, ENCC62F 1, 3, 5 rw ENT12OM 6 rw User's Manual CCU6, UM_V0.5D3 18-98 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field ENT12PM Bits 7 Type Description rw Enable Interrupt for T12 Period-Match 0B No interrupt will be generated if the set condition for bit T12PM in register IS occurs. 1B An interrupt will be generated if the set condition for bit T12PM in register IS occurs. The service request output that will be activated is selected by bit field INPT12. Enable Interrupt for T13 Compare-Match 0B No interrupt will be generated if the set condition for bit T13CM in register IS occurs. An interrupt will be generated if the set 1B condition for bit T13CM in register IS occurs. The service request output that will be activated is selected by bit field INPT13. Enable Interrupt for T13 Period-Match 0B No interrupt will be generated if the set condition for bit T13PM in register IS occurs. 1B An interrupt will be generated if the set condition for bit T13PM in register IS occurs. The service request output that will be activated is selected by bit field INPT13. Enable Interrupt for Trap Flag 0B No interrupt will be generated if the set condition for bit TRPF in register IS occurs. 1B An interrupt will be generated if the set condition for bit TRPF in register IS occurs. The service request output that will be activated is selected by bit field INPERR. Enable Interrupt for Correct Hall Event 0B No interrupt will be generated if the set condition for bit CHE in register IS occurs. An interrupt will be generated if the set 1B condition for bit CHE in register IS occurs. The service request output that will be activated is selected by bit field INPCHE. Capture/Compare Unit 6 (CCU6) ENT13CM 8 rw ENT13PM 9 rw ENTRPF 10 rw ENCHE 12 rw User's Manual CCU6, UM_V0.5D3 18-99 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field ENWHE Bits 13 Type Description rw Enable Interrupt for Wrong Hall Event 0B No interrupt will be generated if the set condition for bit WHE in register IS occurs. 1B An interrupt will be generated if the set condition for bit WHE in register IS occurs. The service request output that will be activated is selected by bit field INPERR. Enable Idle This bit enables the automatic entering of the idle state (bit IDLE will be set) after a wrong hall event has been detected (bit WHE is set). During the idle state, the bit field MCMP is automatically cleared. 0B The bit IDLE is not automatically set when a wrong hall event is detected. 1B The bit IDLE is automatically set when a wrong hall event is detected. Enable Multi-Channel Mode Shadow Transfer Interrupt No interrupt will be generated if the set 0B condition for bit STR in register IS occurs. 1B An interrupt will be generated if the set condition for bit STR in register IS occurs. The service request output that will be activated is selected by bit field INPCHE. reserved; returns 0 if read; should be written with 0; Capture/Compare Unit 6 (CCU6) ENIDLE 14 rw ENSTR 15 rw 0 11 r User's Manual CCU6, UM_V0.5D3 18-100 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.8.2.5 Interrupt Node Pointer Register Register INP contains the interrupt node pointers allowing a flexible interrupt handling. These bit fields define which service request output will be activated if the corresponding interrupt event occurs and the interrupt generation for this event is enabled. INP Interrupt Node Pointer Register 15 0 r 14 13 12 11 10 9 INP ERR rw XSFR(56H) 8 7 INP CHE rw 6 5 4 Reset Value: 3940H 3 2 1 0 INP T13 rw INP T12 rw INP CC62 rw INP CC61 rw INP CC60 rw Field INPCC60, INPCC61, INPCC62 Bits [1:0], [3:2], [5:4] Type Description rw Interrupt Node Pointer for Channel CC6x Interrupts This bit field defines the service request output activated due to a set condition for bit CC6xR (if enabled by bit ENCC6xR) or for bit CC6xF (if enabled by bit ENCC6xF). 00B Service request output SR0 is selected. 01B Service request output SR1 is selected. 10B Service request output SR2 is selected. 11B Service request output SR3 is selected. Interrupt Node Pointer for the CHE Interrupt This bit field defines the service request output activated due to a set condition for bit CHE (if enabled by bit ENCHE) of for bit STR (if enabled by bit ENSTR). Coding see INPCC6x. Interrupt Node Pointer for Error Interrupts This bit field defines the service request output activated due to a set condition for bit TRPF (if enabled by bit ENTRPF) or for bit WHE (if enabled by bit ENWHE). Coding see INPCC6x. INPCHE [7:6] rw INPERR [9:8] rw User's Manual CCU6, UM_V0.5D3 18-101 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field INPT12 Bits [11:10] Type Description rw Interrupt Node Pointer for Timer12 Interrupts This bit field defines the service request output activated due to a set condition for bit T12OM (if enabled by bit ENT12OM) or for bit T12PM (if enabled by bit ENT12PM). Coding see INPCC6x. Interrupt Node Pointer for Timer13 Interrupt This bit field defines the service request output activated due to a set condition for bit T13CM (if enabled by bit ENT13CM) or for bit T13PM (if enabled by bit ENT13PM). Coding see INPCC6x. reserved; returns 0 if read; should be written with 0; Capture/Compare Unit 6 (CCU6) INPT13 [13:12] rw 0 [15:14] r User's Manual CCU6, UM_V0.5D3 18-102 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.9 * * * General Module Operation This section provides information about the: Configuration of the behavior of the different device operating modes (see mode control description in Section 18.9.1) Input selection (see Section 18.9.2) General register description (see Section 18.9.3) 18.9.1 Mode Control The mode control concept for system control tasks, such as power saving, or suspend request for debugging, allows to program the module behavior under different device operating conditions. The behavior of a CCU6 kernel can be programmed for each of the device operating modes, that are requested by the global state control part of the SCU. Therefore, a CCU6 module provides a kernel state configuration register KSCFG defining the behavior in the following device operating modes: * Normal operation: This operating mode is the default operating mode when neither a suspend request nor a clock-off request are pending. The module clock is not switched off and the CCU6 registers can be read or written. The kernel behavior is defined by KSCFG.NOMCFG. Suspend mode: This operating mode is requested when a suspend request (issued by a debugger) is pending in the device. The module clock is not switched off and the CCU6 registers can be read or written. The kernel behavior is defined by KSCFG.SUMCFG. Clock-off mode: This operating mode is requested for power saving purposes. The module clock is switched off automatically when all kernels of the CCU6 module reached their specified state in a stop mode. In this case, CCU6 registers can not be accessed. The kernel behavior is defined by KSCFG.COMCFG. * * The kernel distinguishes four different blocks (T12, T13, Hall logic, and trap logic). These blocks can be individually enabled for the request of stop mode 0 and stop mode 1 by the sensitivity bits KSCSR.SBx. If the request sensitivity is disabled, the block continues normal operation. If the request sensitivity is enabled, the block operates as specified for the selected stop mode. The complete CCU6 acknowledge is given to the GSC when all four blocks have reached their defined end condition. User's Manual CCU6, UM_V0.5D3 18-103 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Table 18-12 CCU6 Functional Blocks Block Function 0 Timer T12: A functional enable is delivered until the specified stop condition is reached. Then, T12 stops counting and the CC6xIN input stages are frozen. Timer T13: A functional enable is delivered until the specified stop condition is reached. Then, T13 stops counting. Hall Logic: The hall logic is stopped immediately and the CCPOSx input stages are frozen. Trap Logic: The trap logic is stopped immediately and the CTRAP input stage is frozen. Sensitivity Bit KSCSR.SB0 Capture/Compare Unit 6 (CCU6) 1 KSCSR.SB1 2 KSCSR.SB2 3 KSCSR.SB3 The behavior of the CCU6 kernel can be programmed for each of the device operating modes (normal operation, suspend mode, clock-off mode). Therefore, it supports four kernel modes, as shown in Table 18-13. Table 18-13 CCU6 Kernel Behavior Kernel Mode run mode 0 run mode 1 Kernel Behavior kernel operation as specified, no impact on CCU6 operation (same behavior for run mode 0 and run mode 1) Code 00B 01B User's Manual CCU6, UM_V0.5D3 18-104 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Table 18-13 CCU6 Kernel Behavior (cont'd) Kernel Mode stop mode 0 Kernel Behavior Code The sensitivity bits are taken into account for: 10B T12 block: Timer T12 continues normal operation (if running) until they reach the end of the PWM period and then it stops (same stop condition as in single shot mode). When the timer stops, the CC6xIN inputs are frozen. T13 block: Timer T13 continues normal operation (if running) until they reach the end of the PWM period and then it stops (same stop condition as in single shot mode). Hall logic block: The CCPOSx input values are frozen. Trap logic block: The CTRAP input value is frozen. The output lines enabled for the trap condition are set to their 11B passive values (similar to a trap state). The sensitivity bits are taken into account for: T12 block: Timer T12 stops immediately and CC6xIN inputs are frozen. T13 block: Timer T13 stops. Hall logic block: The CCPOSx input values are frozen. Trap logic block: The CTRAP input value is frozen. Capture/Compare Unit 6 (CCU6) stop mode 1 Generally, bit field KSCFG.NOMCFG should be configured for run mode 0 as default setting for standard operation. If a CCU6 kernel should not react to a suspend request (and to continue operation as in normal mode), bit field KSCFG.SUMCFG has to be configured with the same value as KSCFG.NOMCFG. If a CCU6 kernel should show a different behavior and stop operation when a specific stop condition is reached, the code for stop mode 0 or stop mode 1 has to be written to KSCFG.SUMCFG. A similar mechanism applies for the clock-off mode with the possibility to program the desired behavior by bit field KSCFG.COMCFG. Note: The stop mode selection strongly depends on the application needs and it is very unlikely that different stop modes are required in parallel in the same application. As a result, only one stop mode type (either 0 or 1) should be used in the bit fields in register KSCFG. Do not mix stop mode 0 and stop mode 1 and avoid transitions from stop mode 0 to stop mode 1 (or vice versa) for the CCU6 module. If the module clock is disabled by KSCFG.MODEN = 0 or in clock-off mode when the stop condition is reached (in stop mode 0 or 1), the module can not be accessed by read or write operations (except register KSCFG that can always be accessed). As a consequence, it can not be configured. Please note that bit KSCFG.MODEN should only be set by SW while all configuration fields are configured for run mode 0. User's Manual CCU6, UM_V0.5D3 18-105 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.9.2 Input Selection Each CCU6 input signal can be selected from a vector of four possible inputs by programming the port input select registers PISELL and PISELH. This permits to adapt the pin functionality of the device to the application requirements. The output pins for the module output signals are chosen in the ports. Naming convention: The input vector CC60IN[D:A] for input signal CC60IN is composed of the signals CC60INA to CC60IND. Note: All functional inputs of the CCU6 are synchronized to fCC6 before they affect the module internal logic. The resulting delay of 2/fCC6 and for asynchronous signals an additional uncertainty of 1/fCC6 have to be taken into account for precise timing calculation. An edge of an input signal can only be correctly detected if the high phase and the low phase of the input signal are both longer than 1/fCC6. User's Manual CCU6, UM_V0.5D3 18-106 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.9.3 General Registers 18.9.3.1 Port Input Select Registers Registers PISELL and PISELH contain bit fields selecting the actual input signal for the module inputs. PISELL Port Input Select Register Low 15 14 13 12 11 10 9 XSFR(04H) 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 IST12HR rw ISPOS2 rw ISPOS1 rw ISPOS0 rw ISTRP rw ISCC62 rw ISCC61 rw ISCC60 rw Field ISCC60 Bits [1:0] Type Description rw Input Select for CC60 This bit field defines the input signal used as CC60 capture input. 00B The signal CC60INA is selected. 01B The signal CC60INB is selected. 10B The signal CC60INC is selected. 11B The signal CC60IND is selected. Input Select for CC61 This bit field defines the input signal used as CC61 capture input. 00B The signal CC61INA is selected. 01B The signal CC61INB is selected. 10B The signal CC61INC is selected. 11B The signal CC61IND is selected. Input Select for CC62 This bit field defines the input signal used as CC62 capture input. 00B The signal CC62INA is selected. 01B The signal CC62INB is selected. 10B The signal CC62INC is selected. 11B The signal CC62IND is selected. ISCC61 [3:2] rw ISCC62 [5:4] rw User's Manual CCU6, UM_V0.5D3 18-107 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field ISTRP Bits [7:6] Type Description rw Input Select for CTRAP This bit field defines the input signal used as CTRAP input. 00B The signal CTRAPA is selected. 01B The signal CTRAPB is selected. 10B The signal CTRAPC is selected. 11B The signal CTRAPD is selected. Input Select for CCPOS0 This bit field defines the input signal used as CCPOS0 input. 00B The signal CCPOS0A is selected. 01B The signal CCPOS0B is selected. 10B The signal CCPOS0C is selected. 11B The signal CCPOS0D is selected. Input Select for CCPOS1 This bit field defines the input signal used as CCPOS1 input. 00B The signal CCPOS1A is selected. 01B The signal CCPOS1B is selected. 10B The signal CCPOS1C is selected. 11B The signal CCPOS1D is selected. Input Select for CCPOS2 This bit field defines the input signal used as CCPOS2 input. 00B The signal CCPOS2A is selected. 01B The signal CCPOS2B is selected. 10B The signal CCPOS2C is selected. 11B The signal CCPOS2D is selected. Input Select for T12HR This bit field defines the input signal used as T12HR input. 00B The signal T12HRA is selected. 01B The signal T12HRB is selected. 10B The signal T12HRC is selected. 11B The signal T12HRD is selected. Capture/Compare Unit 6 (CCU6) ISPOS0 [9:8] rw ISPOS1 [11:10] rw ISPOS2 [13:12] rw IST12HR [15:14] rw User's Manual CCU6, UM_V0.5D3 18-108 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary PISELH Port Input Select Register High 15 14 13 12 11 0 r 10 9 Capture/Compare Unit 6 (CCU6) XSFR(06H) 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 ISCNT13 rw ISCNT12 rw IST13HR rw Field IST13HR Bits [1:0] Type Description rw Input Select for T13HR This bit field defines the input signal used as T13HR input. 00B The signal T13HRA is selected. 01B The signal T13HRB is selected. 10B The signal T13HRC is selected. 11B The signal T13HRD is selected. Input Select for T12 Counting Input This bit field defines the input event leading to a counting action of T12. 00B The T12 prescaler generates the counting events. Bit TCTR4.T12CNT is not taken into account. 01B Bit TCTR4.T12CNT written with 1 is a counting event. The T12 prescaler is not taken into account. 10B The timer T12 is counting each rising edge detected in the selected T12HR signal. 11B The timer T12 is counting each falling edge detected in the selected T12HR signal. ISCNT12 [3:2] rw User's Manual CCU6, UM_V0.5D3 18-109 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field ISCNT13 Bits [5:4] Type Description rw Input Select for T13 Counting Input This bit field defines the input event leading to a counting action of T13. 00B The T13 prescaler generates the counting events. Bit TCTR4.T13CNT is not taken into account. 01B Bit TCTR4.T13CNT written with 1 is a counting event. The T13 prescaler is not taken into account. 10B The timer T13 is counting each rising edge detected in the selected T13HR signal. 11B The timer T13 is counting each falling edge detected in the selected T13HR signal. reserved; returns 0 if read; should be written with 0; Capture/Compare Unit 6 (CCU6) 0 [15:6] r User's Manual CCU6, UM_V0.5D3 18-110 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.9.3.2 Kernel State Configuration Register The kernel state configuration register KSCFG allows the selection of the desired kernel modes for the different device operating modes. Bit fields KSCFG.NOMCFG and KSCFG.COMCFG are reset by a class 3 reset. Bit field KSCFG.SUMCFG is reset by a class 1 reset. Note: The coding of the bit fields NOMCFG, SUMCFG and COMCFG is described in Table 18-13. KSCFG Kernel State Configuration Register XSFR(00H) 15 BP COM w 14 0 r 13 12 11 10 0 r 9 8 7 6 0 r 5 4 Reset Value: 0000H 3 0 r 2 1 0 BP MOD MOD EN EN w rw BP COMCFG SUM rw w BP SUMCFG NOM rw w NOMCFG rw Field MODEN Bits 0 Type Description rw Module Enable This bit enables the module kernel clock and the module functionality. The module is switched off immediately 0B (without respecting a stop condition). It does not react on mode control actions and the module clock is switched off. The module does not react on read accesses and ignores write accesses (except to KSCFG). 1B The module is switched on and can operate. After writing 1 to MODEN, it is recommended to read register KSCFG to avoid pipeline effects in the control block before accessing other ADC registers. Bit Protection for MODEN This bit enables the write access to the bit MODEN. It always reads 0. MODEN is not changed. 0B 1B MODEN is updated with the written value. BPMODEN 1 w User's Manual CCU6, UM_V0.5D3 18-111 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field NOMCFG Bits [5:4] Type Description rw Normal Operation Mode Configuration This bit field defines the kernel mode applied in normal operation mode. 00B Run mode 0 is selected. 01B Run mode 1 is selected. 10B Stop mode 0 is selected. 11B Stop mode 1 is selected. Bit Protection for NOMCFG This bit enables the write access to the bit field NOMCFG. It always reads 0. 0B NOMCFG is not changed. 1B NOMCFG is updated with the written value. Suspend Mode Configuration This bit field defines the kernel mode applied in suspend mode. Coding like NOMCFG. Bit Protection for SUMCFG This bit enables the write access to the bit field SUMCFG. It always reads 0. 0B SUMCFG is not changed. 1B SUMCFG is updated with the written value. Clock Off Mode Configuration This bit field defines the kernel mode applied in clock-off mode. Coding like NOMCFG. Bit Protection for COMCFG This bit enables the write access to the bit field COMCFG. It always reads 0. 0B COMCFG is not changed. 1B COMCFG is updated with the written value. Reserved returns 0 if read; should be written with 0; Capture/Compare Unit 6 (CCU6) BPNOM 7 w SUMCFG [9:8] rw BPSUM 11 w COMCFG [13:12] rw BPCOM 15 w 0 [3:2], 6, 10, 14 r Note: The bit protection bits BPxxx allow partly modification of the configuration bits with a single write operation (without the need of a read-modify-write mechanism handled by the CPU). User's Manual CCU6, UM_V0.5D3 18-112 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.9.3.3 Kernel State Sensitivity Control Register The kernel state control sensitivity register bits define which internal block is effected by stop modes 0 and 1. KSCSR Kernel State Control Sensitivity Register XSFR(0EH) 15 14 13 12 11 10 0 r 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 SB3 SB2 SB1 SB0 rw rw rw rw Field SB0, SB1, SB2, SB3 Bits 0, 1, 2, 3 Type Description rw Sensitivity Block x This bit defines if block x of the CCU6 kernel is sensitive to stop mode 0 or stop mode 1. The functional definition of the blocks is given in Table 18-12. 0B Block x is not sensitive to stop mode 0 or stop mode 1 and behaves like in run mode 0. It continues normal operation without respecting the defined stop condition. 1B Block x is sensitive to stop mode 0 or stop mode 1. It is respecting the defined stop condition. reserved; returns 0 if read; should be written with 0; 0 [15:4] r User's Manual CCU6, UM_V0.5D3 18-113 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.9.3.4 Module Configuration Register The module configuration register contains bits describing the functionality that is available in the CCU6 module. MCFG Module Configuration Register 15 0 r 14 13 12 11 10 9 0 r XSFR(0CH) 8 7 6 5 4 Reset Value: 0007H 3 2 1 0 MCM T13 T12 rw rw rw Field T12 Bits 0 Type rw Description T12 Available This bit indicates if the T12 block is available. 0B The T12 block is not available. A write access to T12PR is ignored. 1B The T12 block is available. A write access to T12PR is executed. T13 Available This bit indicates if the T13 block is available. The T13 block is not available. 0B A write access to T13PR is ignored. 1B The T13 block is available. A write access to T13PR is executed. Multi-Channel Mode Available This bit indicates if the multi-channel mode functionality is available. 0B The multi-channel mode functionality is not available. A write access to MCMOUTS is ignored. 1B The multi-channel mode functionality is available. A write access to MCMOUTS is executed. Reserved; read as 0; should be written with 0. T13 1 rw MCM 2 rw 0 [15:3] r User's Manual CCU6, UM_V0.5D3 18-114 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.10 * * * * * * * Implementation This section describes the implementation of the CCU6 modules in the XC2000 device. Address map (see Section 18.10.1) Interrupt control registers (see Section 18.10.2) Synchronous start (see Section 18.10.3) Connections of CCU60 (see Section 18.10.4.1) Connections of CCU61 (see Section 18.10.4.2) Connections of CCU62 (see Section 18.10.4.3) Connections of CCU63 (see Section 18.10.4.4) 18.10.1 Address Map The four CCU6x modules (named CCU60 to CCU63) can be accessed in the following address ranges. The exact register address is given by the relative address of the register (given in Table 18-1) plus the kernel base address (given in Table 18-14) of the module. Table 18-14 Registers Address Space Module CCU60 CCU61 CCU62 CCU63 Base Address EA00H EA80H EB00H EB80H End Address EA7EH EAFEH EB7EH EBFEH Note User's Manual CCU6, UM_V0.5D3 18-115 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.10.2 Interrupt Control Registers The interrupt control registers are located in the SFR area. They are described in the general interrupt chapter. Table 18-15 CCU6 Interrupt Control Registers Short Name CCU60_0IC CCU60_1IC CCU60_2IC CCU60_3IC CCU61_0IC CCU61_1IC CCU61_2IC CCU61_3IC CCU62_0IC CCU62_1IC CCU62_2IC CCU62_3IC CCU63_0IC CCU63_1IC CCU63_2IC CCU63_3IC Description Interrupt Control Register for SR0 of CCU60 Interrupt Control Register for SR1 of CCU60 Interrupt Control Register for SR2 of CCU60 Interrupt Control Register for SR3 of CCU60 Interrupt Control Register for SR0 of CCU61 Interrupt Control Register for SR1 of CCU61 Interrupt Control Register for SR2 of CCU61 Interrupt Control Register for SR3 of CCU61 Interrupt Control Register for SR0 of CCU62 Interrupt Control Register for SR1 of CCU62 Interrupt Control Register for SR2 of CCU62 Interrupt Control Register for SR3 of CCU62 Interrupt Control Register for SR0 of CCU63 Interrupt Control Register for SR1 of CCU63 Interrupt Control Register for SR2 of CCU63 Interrupt Control Register for SR3 of CCU63 User's Manual CCU6, UM_V0.5D3 18-116 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.10.3 Synchronous Start Feature Synchronous start is supported by bit SYSCON.GLCCST (global capture/compare start) in the SCU module that is connected to the T12HR and T13HR inputs of all CCU6x modules. The same signal can also be connected to other capture/compare units in order to allow a synchronous start of the capture/compare timers. SCU SYSCON.GLCCST T12HR T13HR T12HR T13HR edge selection by T12RSEL set edge selection by T13RSEL set edge selection by T12RSEL set edge selection by T13RSEL set T12R CCU60 T13R T12R CCU61 T13R CCU6_sync_start Figure 18-43 Synchronization Concept User's Manual CCU6, UM_V0.5D3 18-117 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.10.4 Digital Connections The following tables show the digital connections of the CCU6x modules with other modules or pins in the XC2000 device. Each input signal can be selected among 4 possible input lines, e.g. the input vector for input signal CC60IN is composed of CC60IN[D:A]. The following sections refer to the interface signals, whereas the connections of the service request outputs SR[3:0] to the interrupt control registers of each CCU6x to the interrupt control registers is given in Section 18.10.2. The CCU6x modules are clocked with the XC2000 system clock, so fCC6 = fSYS. Note: All functional inputs of the CCU6 are synchronized to fCC6 before they can affect the module internal logic. The resulting delay of 2/fCC6 and an uncertainty of 1/fCC6 have to be taken into account for precise timing calculation. An edge of an input signal can only be correctly detected if both, the high phase and the low phase of the input signal are each longer than 1/fCC6. 18.10.4.1 Connections of CCU60 This table describes the module interconnections of CCU60. Table 18-16 CCU60 Digital Connections in XC2000 Signal CC60INA CC60INB CC60INC CC60IND CC61INA CC61INB CC61INC CC61IND CC62INA CC62INB CC62INC CC62IND from/to Module P10.0 P8.0 0 RTC interrupt P10.1 P8.1 0 0 P10.2 P8.2 0 0 I/O to CCU60 I I I I I I I I I I I I input signals for capture event on channel CC62 input signals for capture event on channel CC61 Can be used to/as input signals for capture event on channel CC60 User's Manual CCU6, UM_V0.5D3 18-118 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) Table 18-16 CCU60 Digital Connections in XC2000 (cont'd) Signal CTRAPA CTRAPB CTRAPC CTRAPD CCPOS0A CCPOS0B CCPOS0C CCPOS0D CCPOS1A CCPOS1B CCPOS1C CCPOS1D CCPOS2A CCPOS2B CCPOS2C CCPOS2D T12HRA T12HRB T12HRC T12HRD T13HRA T13HRB T13HRC T13HRD CC60 COUT60 from/to Module P10.6 P8.6 ESR2 1 P10.7 P9.7 0 0 P10.8 P9.6 0 0 P10.9 P9.5 0 0 CCU63_MCM_ST P5.5 P5.8 SYSCON.GLCCST EXTCLK (SCU) CCU60_T12_ZM P5.8 SYSCON.GLCCST P10.0 P8.0 P10.3 P8.3 I/O to CCU60 I I I I I I I I I I I I I I I I I I I I I I I I O O compare outputs of channel CC60 input signals for T13HR input signals for T12HR input signals for CCPOS2 input signals for CCPOS1 input signals for CCPOS0 Can be used to/as input signals for CTRAP, the ESRx input refers to the synchronized input signal, that can be filtered (if enabled) User's Manual CCU6, UM_V0.5D3 18-119 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) Table 18-16 CCU60 Digital Connections in XC2000 (cont'd) Signal CC61 COUT61 CC62 COUT62 COUT63 from/to Module P10.1 P8.1 P10.4 P8.4 P10.2 P8.2 P10.5 P8.5 P10.7 P10.10 P8.6 CCU60_T13HRB ADC0_REQTR0B ADC0_REQTR1B U0C0_DX2F U0C1_DX2F ERU_OGU02 CCU61_T12HRA ERU_OGU01 interrupt controller I/O to CCU60 O O O O O compare output of channel CC63 compare outputs of channel CC62 Can be used to/as compare outputs of channel CC61 T12_ZM T13_PM O O T12 zero match T13 period match MCM_ST SR[3:0] O O MCM shadow transfer interrupt output lines (service request) User's Manual CCU6, UM_V0.5D3 18-120 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.10.4.2 Connections of CCU61 This table describes the module interconnections of CCU61. Table 18-17 CCU61 Digital Connections in XC2000 Signal CC60INA CC60INB CC60INC CC60IND CC61INA CC61INB CC61INC CC61IND CC62INA CC62INB CC62INC CC62IND CTRAPA CTRAPB CTRAPC CTRAPD CCPOS0A CCPOS0B CCPOS0C CCPOS0D CCPOS1A CCPOS1B CCPOS1C CCPOS1D from/to Module P0.0 0 0 0 P0.1 0 0 0 P0.2 0 0 0 P0.6 P0.7 ESR2 1 0 0 0 0 0 0 0 0 I/O to CC61 I I I I I I I I I I I I I I I I I I I I I I I I input signals for CCPOS1 input signals for CCPOS0 input signals for CTRAP, the ESRx input refers to the synchronized input signal, that can be filtered (if enabled) input signals for capture event on channel CC62 input signals for capture event on channel CC61 Can be used to/as input signals for capture event on channel CC60 User's Manual CCU6, UM_V0.5D3 18-121 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) Table 18-17 CCU61 Digital Connections in XC2000 (cont'd) Signal CCPOS2A CCPOS2B CCPOS2C CCPOS2D T12HRA T12HRB T12HRC T12HRD T13HRA T13HRB T13HRC T13HRD CC60 COUT60 CC61 COUT61 CC62 COUT62 COUT63 T12_ZM T13_PM from/to Module 0 0 0 0 CCU60_MCM_ST P1.2 P5.8 SYSCON.GLCCST 0 CCU61_T12_ZM P5.8 SYSCON.GLCCST P0.0 P0.3 P0.1 P0.4 P0.2 P0.5 P0.6 CCU61_T13HRB ADC1_REQTR0B ADC1_REQTR1B U1C0_DX2F U1C1_DX2F ERU_OGU12 CCU62_T12HRA ERU_OGU11 I/O to CC61 I I I I I I I I I I I I O O O O O O O O O compare output of channel CC63 T12 zero match T13 period match compare outputs of channel CC62 compare outputs of channel CC61 compare outputs of channel CC60 input signals for T13HR input signals for T12HR Can be used to/as input signals for CCPOS2 MCM_ST O MCM shadow transfer User's Manual CCU6, UM_V0.5D3 18-122 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.10.4.3 Connections of CCU62 This table describes the module interconnections of CCU62. Table 18-18 CCU62 Digital Connections in XC2000 Signal CC60INA CC60INB CC60INC CC60IND CC61INA CC61INB CC61INC CC61IND CC62INA CC62INB CC62INC CC62IND CTRAPA CTRAPB CTRAPC CTRAPD CCPOS0A CCPOS0B CCPOS0C CCPOS0D CCPOS1A CCPOS1B CCPOS1C CCPOS1D from/to Module P1.7 0 0 0 P1.6 0 0 0 P1.2 0 0 0 P7.1 P1.0 ESR2 1 P7.2 0 0 0 P7.3 0 0 0 I/O to CCU62 I I I I I I I I I I I I I I I I I I I I I I I I input signals for CCPOS1 input signals for CCPOS0 input signals for CTRAP, the ESRx input refers to the synchronized input signal, which can be filtered (if enabled) input signals for capture event on channel CC62 input signals for capture event on channel CC61 Can be used to/as input signals for capture event on channel CC60 User's Manual CCU6, UM_V0.5D3 18-123 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) Table 18-18 CCU62 Digital Connections in XC2000 (cont'd) Signal CCPOS2A CCPOS2B CCPOS2C CCPOS2D T12HRA T12HRB T12HRC T12HRD T13HRA T13HRB T13HRC T13HRD CC60 COUT60 CC61 COUT61 CC62 COUT62 COUT63 T12_ZM T13_PM from/to Module P7.4 0 0 0 CCU61_MCM_ST P1.3 P5.8 SYSCON.GLCCST CAN_INT_O15 CCU62_T12_ZM P5.8 SYSCON.GLCCST P1.7 P1.5 P1.6 P1.4 P1.2 P1.1 P1.3 CCU62_T13HRB ADC0_REQTR2B U2C0_DX2F U2C1_DX2F ERU_OGU22 CCU63_T12HRA ERU_OGU21 I/O to CCU62 I I I I I I I I I I I I O O O O O O O O O compare output of channel CC63 T12 zero match T13 period match compare outputs of channel CC62 compare outputs of channel CC61 compare outputs of channel CC60 input signals for T13HR input signals for T12HR Can be used to/as input signals for CCPOS2 MCM_ST O MCM shadow transfer User's Manual CCU6, UM_V0.5D3 18-124 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) 18.10.4.4 Connections of CCU63 This table describes the module interconnections of CCU63. Table 18-19 CCU63 Digital Connections in XC2000 Signal CC60INA CC60INB CC60INC CC60IND CC61INA CC61INB CC61INC CC61IND CC62INA CC62INB CC62INC CC62IND CTRAPA CTRAPB CTRAPC CTRAPD CCPOS0A CCPOS0B CCPOS0C CCPOS0D CCPOS1A CCPOS1B CCPOS1C CCPOS1D from/to Module P9.0 P2.0 0 0 P9.1 P2.1 0 0 P9.2 P2.2 0 0 P9.6 P9.7 ESR2 1 P11.0 0 0 0 P11.1 0 0 0 I/O to CCU63 I I I I I I I I I I I I I I I I I I I I I I I I input signals for CCPOS1 input signals for CCPOS0 input signals for CTRAP, the ESRx input refers to the synchronized input signal, which can be filtered (if enabled) input signals for capture event on channel CC62 input signals for capture event on channel CC61 Can be used to/as input signals for capture event on channel CC60 User's Manual CCU6, UM_V0.5D3 18-125 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Capture/Compare Unit 6 (CCU6) Table 18-19 CCU63 Digital Connections in XC2000 (cont'd) Signal CCPOS2A CCPOS2B CCPOS2C CCPOS2D T12HRA T12HRB T12HRC T12HRD T13HRA T13HRB T13HRC T13HRD CC60 COUT60 CC61 COUT61 CC62 COUT62 COUT63 T12_ZM T13_PM MCM_ST from/to Module P11.2 0 0 0 CCU62_MCM_ST P5.4 P5.8 SYSCON.GLCCST CAN_INT_O15 CCU63_T12_ZM P5.8 SYSCON.GLCCST P9.0 P2.0 P9.3 P9.1 P2.1 P9.4 P9.2 P2.2 P9.5 P9.6 P9.6 P2.3 CCU63_T13HRB ADC1_REQTR2B ERU_OGU32 CCU60_T12HRA ERU_OGU31 I/O to CCU63 I I I I I I I I I I I I O O O O O O O O O O compare output of channel CC63 T12 zero match T13 period match MCM shadow transfer compare outputs of channel CC62 compare outputs of channel CC61 compare outputs of channel CC60 input signals for T13HR input signals for T12HR Can be used to/as input signals for CCPOS2 User's Manual CCU6, UM_V0.5D3 18-126 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19 Universal Serial Interface Channel The Universal Serial Interface Channel module (USIC) is a flexible interface module covering several serial communication protocols. A USIC module contains two independent communication channels named UxC0 and UxC1, with x being the number of the USIC module (e.g. channel y of USIC module x is referenced as UxCy). The user can program during run-time which protocol will be handled by each communication channel and which pins are used. This chapter is structured as follows: * * * * * * * Introduction (see Section 19.1) Operating the USIC (see Section 19.2) ASC protocol for UART and LIN (see Section 19.3) SSC protocol (see Section 19.4) IIC protocol (see Section 19.5) IIS protocol (see Section 19.6) Module implementation in XC2000 (see Section 19.7) 19.1 Introduction This section gives an overview about the feature set of the USIC and introduces the USIC structure. It describes the: * * * * * * * Feature set overview (see Section 19.1.1) Channel structure (see Section 19.1.2) Input stages (see Section 19.1.3) Output signals (see Section 19.1.4) Baud rate generator (see Section 19.1.5) Channel events and interrupts (see Section 19.1.6) Data shifting and handling (see Section 19.1.7) User's Manual USIC, UM_V0.2D5 19-1 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.1.1 Feature Set Overview Each USIC channel can be individually configured to match the application needs, e.g. the protocol can be selected or changed during run time without the need for a reset. The following protocols are supported: * UART (ASC, asynchronous serial channel) - module capability: receiver/transmitter with max. baud rate fsys/4 - application target baud rate range: 1.2 kBaud to 3.5 MBaud - number of data bits per data frame 1 to 63 - MSB or LSB first LIN Support by HW (low-cost network, baud rate up to 20 kBaud) - data transfers based on ASC protocol - baud rate detection possible by built-in capture event of baud rate generator - checksum generation under SW control for higher flexibility SSC/SPI (synchronous serial channel with or without slave select lines) - module capability: slave mode with max. baud rate fsys /2 - module capability: master mode with max. baud rate fsys /2 - application target baud rate range: 2 kBaud to 10 MBaud - number of data bits per data frame 1 to 63, more with explicit stop condition - MSB or LSB first IIC (Inter-IC Bus) - application baud rate 100 kBaud to 400 kBaud - 7-bit and 10-bit addressing supported - full master and slave device capability IIS (infotainment audio bus) - module capability: receiver with max. baud rate fSYS - module capability: transmitter with max. baud rate fSYS /2 - application target baud rate range: up to 26 MBaud * * * * In addition to the flexible choice of the communication protocol, the USIC structure has been designed to reduce the system load (CPU load) allowing efficient data handling. The following aspects have been considered: * Data buffer capability The standard buffer capability includes a double word buffer for receive data and a single word buffer for transmit data. This allows longer CPU reaction times (e.g. interrupt latency). Additional FIFO buffer capability In addition to the standard buffer capability, the received data and the data to be transmitted can be buffered in a FIFO buffer structure. The size of the receive and the transmit FIFO buffer can be programmed independently. Depending on the application needs, a total buffer capability of 64 data words can be assigned to the receive and transmit FIFO buffers of a USIC module (the two channels of the USIC module share the 64 data word buffer). * User's Manual USIC, UM_V0.2D5 19-2 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel * * * * * * * * In addition to the FIFO buffer, a bypass mechanism allows the introduction of highpriority data without flushing the FIFO buffer. Transmit control information For each data word to be transmitted, a 5-bit transmit control information has been added to automatically control some transmission parameters, such as word length, frame length, or the slave select control for the SPI protocol. The transmit control information is generated automatically by analyzing the address where the user SW has written the data word to be transmitted (32 input locations = 2^5 = 5 bit transmit control information). This feature allows individual handling of each data word, e.g. the transmit control information associated to the data words stored in a transmit FIFO can automatically modify the slave select outputs to select different communication targets (slave devices) without CPU load. Alternatively, it can be used to control the frame length. Flexible frame length control The number of bits to be transferred within a data frame is independent of the data word length and can be handled in two different ways. The first option allows automatic generation of frames up to 63 bits with a known length. The second option supports longer frames (even unlimited length) or frames with a dynamically controlled length. Interrupt capability The events of each USIC channel can be individually routed to one of 4 service request outputs SR[3:0], depending on the application needs. Furthermore, specific start and end of frame indications are supported in addition to protocol-specific events. Flexible interface routing Each USIC channel offers the choice between several possible input and output pins connections for the communications signals. This allows a flexible assignment of USIC signals to pins that can be changed without resetting the device. Input conditioning Each input signal is handled by a programmable input conditioning stage with programmable filtering and synchronization capability. Baud rate generation Each USIC channel contains an own baud rate generator. The baud rate generation can be based either on the internal module clock or on an external frequency input. This structure allows data transfers with a frequency that can not be generated internally, e.g. to synchronize several communication partners. Transfer trigger capability In master mode, data transfers can be triggered events generated outside the USIC module, e.g. at an input pin or a timer unit (transmit data validation). This feature allows time base related data transmission. Debugger support The USIC offers specific addresses to read out received data without interaction with User's Manual USIC, UM_V0.2D5 19-3 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel the FIFO buffer mechanism. This feature allows debugger accesses without the risk of a corrupted receive data sequence. To reach a desired baud rate, two criteria have to be respected, the module capability and the application environment. The module capability is defined with respect to the module's input clock frequency fsys, being the base for the module operation. Although the module's capability being much higher (depending on the module clock and the number of module clock cycles needed to represent a data bit), the reachable baud rate is generally limited by the application environment. In most cases, the application environment limits the maximum reachable baud rate due to driver delays, signal propagation times, or due to EMI reasons. Note: Depending on the selected additional functions (such as digital filters, input synchronization stages, sample point adjustment, data structure, etc.), the maximum reachable baud rate can be limited. Please also take care about additional delays, such as (internal or external) propagation delays and driver delays (e.g. for collision detection in ASC mode, for IIC, etc.). User's Manual USIC, UM_V0.2D5 19-4 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.1.2 Channel Structure The USIC module contains two independent communication channels, with structure shown in Figure 19-1. The data shift unit and the data buffering of each channel support full-duplex data transfers. The protocol-specific actions are handled by protocol pre-processors (PPP). In order to simplify data handling, an additional FIFO data buffer is optionally available for each USIC module to store transmit and receive data for each channel. This FIFO data buffer is not necessarily available in all devices (please refer to USIC implementation chapter for details). Due to the independent channel control and baud rate generation, the communication protocol, baud rate and the data format can be independently programmed for each communication channel. interrupt generation SRx to interrupt registers pins UxC0 baud rate generator data buff. data shift unit PPP (ASC, SSC,...) fsys input stages signal distribution Figure 19-1 Channel Structure User's Manual USIC, UM_V0.2D5 user interface baud rate generator 1 data buff. data shift unit PPP (ASC, SSC,...) fsys UxC1 input stages optional: FIFO data buffer shared between UxC0 and UxC1 USIC module x USIC_channels 19-5 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.1.3 Input Stages For each protocol up to three input signals are available, the number of actually used inputs depends on the selected protocol. Each input signal is handled by an input stage (named DX0, DX1, DX2) for signal conditioning, such as input selection, polarity control, or a digital input filter. They can be classified according to their meaning for the protocols, see Table 19-1. The inputs marked as "optional" are not needed for the standard function of a protocol and may be used for enhancements. The descriptions of protocol-specific items are given in the related protocol chapters, for the external frequency input please refer to the baud rate generator, and for the transmit data validation to the data handling section. Table 19-1 Selected Protocol ASC, LIN Input Signals for Different Protocols Shift Data Input (handled by DX0) RxD Shift Clock Input (handled by DX1) Shift Control Input (handled by DX2) optional: optional: external frequency transmit data validation input or TxD collision detection optional: external frequency input or delay compensation SCLKIN SCL optional: external frequency input or delay compensation SCLKIN optional: transmit data validation or delay compensation SELIN optional: transmit data validation optional: transmit data validation or delay compensation WAIN SSC, SPI (master) DIN (MRST, MISO) SSC, SPI (slave) IIC IIS (master) DIN (MTSR, MOSI) SDA DIN IIS (slave) DIN Note: To allow a certain flexibility in assigning required USIC input functions to port pins of the device, each input stage can select the desired input location among several posibilities. The available USIC signals and their port locations are listed in the implementation chapter, see Section 19.7.5. User's Manual USIC, UM_V0.2D5 19-6 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.1.4 Output Signals For each protocol up to eleven protocol-related output signals are available, the number of actually used outputs depends on the selected protocol. They can be classified according to their meaning for the protocols, see Table 19-2. The outputs marked as "optional" are not needed for the standard function of a protocol and may be used for enhancements. The descriptions of protocol-specific items are given in the related protocol chapters. The MCLKOUT output signal has a stable frequency relation to the shift clock output (the frequency of MCLKOUT can be higher than for SCLKOUT) for synchronization purposes of a slave device to a master device. If the baud rate generator is not needed for a specific protocol (e.g. in SSC slave mode), the SCLKOUT and MCLKOUT signals can be used as clock outputs with 50% duty cycle with a frequency that can be independent from the communication baud rate. Table 19-2 Output Signals for Different Protocols Shift Clock Output SCLKOUT not used Shift Control Outputs SELO[7:0] not used Master Clock Output MCLKOUT optional: master time base optional: master time base optional: independent clock output optional: master time base optional: master time base optional: independent clock output Selected Shift Data Protocol Output DOUT ASC, LIN TxD SSC, SPI DOUT (master) (MTSR, MOSI) SSC, SPI DOUT (slave) (MRST, MISO) IIC IIS (master) IIS (slave) SDA DOUT DOUT master shift clock slave select, chip select optional: independent clock output SCL not used not used master shift clock WA optional: independent clock output not used Note: To allow a certain flexibility in assigning required USIC output functions to port pins of the device, most output signals are made available on several port pins. The port control itself defines pin-by-pin which signal is used as output signal for a port pin (see port chapter). The available USIC signals and their port locations are listed in the implementation chapter, see Section 19.7.5. User's Manual USIC, UM_V0.2D5 19-7 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.1.5 Baud Rate Generator Each USIC Channel contains a baud rate generator structured as shown in Figure 19-2. It is based on coupled divider stages, providing the frequencies needed for the different protocols. It contains: * * * A fractional divider to generate the input frequency fPIN = fFD for baud rate generation based on the internal system frequency fSYS. The DX1 input to generate the input frequency fPIN = fDX1 for baud rate generation based on an external signal. A protocol-related counter to provide the master clock signal MCLK, the shift clock signal SCLK, and other protocol-related signals. It can also be used for time interval measurement, e.g. baud rate detection. A time quanta counter associated to the protocol pre-processor defining protocolspecific timings, such shift control signals or bit timings, based on the input frequency fCTQIN. The output signals MCLKOUT and SCLKOUT of the protocol-related divider that can be made available on pins. In order to adapt to different applications, some output characteristics of these signals can be configured. For device-specific details about availability of USIC signals on pins please refer to the implementation chapter. * * DX1 input fDX1 fPIN fFD fSYS fract. divider protocol related counter fCTQIN protocol preprocessor enable SCLKOUT SCLK output config. enable MCLKOUT MCLK output config. USIC_baud_rate_gen Figure 19-2 Baud Rate Generator User's Manual USIC, UM_V0.2D5 19-8 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.1.6 Channel Events and Interrupts The notification of the user about events occurring during data traffic and data handling is based on: * * * Data transfer events related to the transmission or reception of a data word, independent of the selected protocol. Protocol-specific events depending on the selected protocol. Data buffer events related to data handling by the optional FIFO data buffers. 19.1.7 Data Shifting and Handling The data handling of the USIC module is based on an independent data shift unit (DSU) and a buffer structure that is similar for the supported protocols. The data shift and buffer registers are 16-bit wide (maximum data word length), but several data words can be concatenated to achieve longer data frames. The DSU inputs are the shift data (handled by input stage DX0), the shift clock (handled by the input stage DX1), and the shift control (handled by the input stage DX2). The signal DOUT represents the shift data output. shift data input bypass data BYP buffered transmit data INx optional transmit data buffer bypass FIFO out in basic data buffer TBU F T SR input DX0 shift data output DOUT data shift unit DSU shift clock input Figure 19-3 Principle of Data Buffering The principle of data handling comprises: * A transmitter with a transmit shift register (TSR) in the DSU and a transmit data buffer (TBUF). A data validation scheme allows triggering and gating of data transfers by external events under certain conditions. A receiver with two alternating receive shift registers (RSR0 and RSR1) in the DSU and a double receive buffer structure (RBUF0, RBUF1). The alternating receive shift 19-9 V1.0, 2007-06 user interface transmit data TBUFx input DX1 optional receive data buffer buffered receive data OUTRL out R BUF 0 R SR0 shift control input FIFO in input DX2 R BUF 1 RSR 1 receive data RBUF USIC_data_buffer * User's Manual USIC, UM_V0.2D5 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel * * registers support the reception of data streams and data frames longer than one data word. Optional transmit and receive data buffers according to the first-in-first-out principle (FIFO), that are not necessarily available in all devices. For device-specific details about availability of the FIFO buffer please refer to the USIC implementation chapter. A user interface to handle data, interrupts, and status and control information. 19.1.7.1 Basic Data Buffer Structure The read access to received data and the write access of data to be transmitted can be handled by a basic data buffer structure. The received data stored in the receiver buffers RBUF0/RBUF1 can be read directly from these registers. In this case, the user has to take care about the reception sequence to read these registers in the correct order. To simplify the use of the receive buffer structure, register RBUF has been introduced. A read action from this register delivers the data word received first (oldest data) to respect the reception sequence. With a read access from at least the low byte of RBUF, the data is automatically declared to be no longer new and the next received data word becomes visible in RBUF and can be read out next. control info TCI TBUF 5 location 16 data RBUF01SRL RBUF0 RBUF01SRH RBUF1 TBUF31 32 address es DS TBUF01 TBUF00 data write access Figure 19-4 Data Access Structure without additional Data Buffer It is recommended to read the received data words by accesses to RBUF and to avoid handling of RBUF0 and RBUF1. The USIC module also supports the use of debug accesses to receive data words. Debugger read accesses should not disturb the receive data sequence and, as a consequence, should not target RBUF. Therefore, register User's Manual USIC, UM_V0.2D5 19-10 V1.0, 2007-06 ... RBUFSR RBUF data read access RBUFD mirror debug read access USIC_data_access XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel RBUFD has been introduced. It contains the same value as RBUF, but a read access from RBUFD does not change the status of the data (same data can be read several times). In addition to the received data, some additional status information about each received data word is available in the receiver buffer status registers RBUF01SRL/H (related to data in RBUF0 and RBUF1) and RBUFSR (related to data in RBUF). Transmit data can be loaded to TBUF by SW by writing to the transmit buffer input locations TBUFx (x = 00-31), consisting of 32 consecutive addresses. The data written to one of these input locations is stored in the transmit buffer TBUF. Additionally, the address of the written location is evaluated and can be used for additional control purposes. This 5-bit wide information (named transmit control information TCI) can be used for different purposes in different protocols. 19.1.7.2 FIFO Buffer Structure To allow easier data setup and handling, an additional data buffering mechanism can be optionally supported. The data buffer is based on the first-in-first-out principle (FIFO) that ensures that the sequence of transferred data words is respected. If a FIFO buffer structure is used, the data handling scheme (data with associated control information) is similar to the one without FIFO. The additional FIFO buffer can be independently enabled/disabled for transmission and reception (e.g. if data FIFO buffers are available for a specific USIC channel, it is possible to configure the transmit data path without and the receive data path with FIFO buffering). The transmit FIFO buffer can be reached by SW at 32 consecutive address locations INx instead of TBUFx (x = 0 - 31). The number of the written address location is used as additional control information and is transported through the FIFO together with the written data. The receive FIFO can be read out at two independent addresses, OUTR and OUTDRL instead of RBUF and RBUFD. A read from the OUTR location triggers the next data packet to be available for the next read (general FIFO mechanism). In order to allow nonintrusive debugging (without risk of data loss), a second address location (OUTDRL) has been introduced. A read at this location delivers the same value as OUTR, but without modifying the FIFO contents. The transmit FIFO also has the capability to bypass the data stream and to load bypass data to TBUF. This can be used to generate high-priority messages or to send an emergency message if the transmit FIFO runs empty. The transmission control of the FIFO buffer can also use the transfer trigger and transfer gating scheme of the transmission logic for data validation (e.g. to trigger data transfers by events). Note: The available size of a FIFO data buffer for a USIC channel depends on the specific device. Please refer to the implementation chapter for details about available FIFO buffer capability. User's Manual USIC, UM_V0.2D5 19-11 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel control info TCI TBUF RBUF01SRL RBUF0 RBUF01SRH RBUF1 Transmit FIFO 5 location 16 data 32 addres ses Receive FIFO IN31 ... IN01 IN00 data write access OUTRH mirror OUTDRH OUTDRL debug read access USIC_FIFO_access OUTRL data read access Figure 19-5 Data Access Structure with FIFO User's Manual USIC, UM_V0.2D5 19-12 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.2 Operating the USIC This section describes how to operate the USIC communication channel. It describes: * * * * * * * * * * * * * * Register Overview (see Section 19.2.1) General channel operation (see Section 19.2.2) Channel control and configuration registers (see Section 19.2.3) Protocol related registers (see Section 19.2.4) Input stages (see Section 19.2.5) Input stage control registers (see Section 19.2.6) Baud rate generation (see Section 19.2.7) Baud rate and shift control registers (see Section 19.2.8) Operating the transmit path (see Section 19.2.9) Operating the receive path (see Section 19.2.10) Transfer control and status registers (see Section 19.2.11) Data buffer registers (see Section 19.2.12) Operating the FIFO data buffer (see Section 19.2.13) FIFO buffer and bypass registers (see Section 19.2.14) 19.2.1 Register Overview The module itself being 32 bit wide, some registers have been split up in two parts for the 16-bit implementation. Both parts keep the same name as the former 32-bit register, with an additional index. The lower part ends with the index L, whereas the upper (higher) part ends with the index H. Former 32-bit registers consisting of only 16 used bits keep their name (without additional index), because only the used bits appear in the register map. 19.2.1.1 Overview The table below shows all registers which are required for programming a USIC channel, as well as the FIFO buffer. It summarizes the USIC communication channel registers and defines their relative addresses and the reset values. 19.2.1.2 Register Table Please note that all registers can be accessed with any access width (8-bit, 16-bit), independent of the described width. Short addressing is not supported. User's Manual USIC, UM_V0.2D5 19-13 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Table 19-3 Register Short Name Universal Serial Interface Channel USIC Kernel-Related and Kernel Registers Register Long Name Offset Addr. Reset Value Description see Channel Registers (once per USIC channel) FDRL FDRH KSCFG CCR INPRL INPRH CCFG BRGL BRGH DX0CR DX1CR DX2CR SCTRL SCTRH FMRL FMRH TCSRL TCSRH PCRL PCRH PSR PSCR RBUFD RBUF0 RBUF1 RBUFSR Fractional Divider Register L Fractional Divider Register H Channel Control Register Interrupt Node Pointer Register L Interrupt Node Pointer Register H Channel Configuration Register Baud Rate Generator Register L Baud Rate Generator Register H Input Control Register 0 Input Control Register 1 Input Control Register 2 Shift Control Register L Shift Control Register H Flag Modification Register L Flag Modification Register H Transmit Control/Status Register L Transmit Control/Status Register H Protocol Control Register L Protocol Control Register H Protocol Status Register Protocol Status Clear Register Receiver Buffer Register for Debugger Receiver Buffer 0 Register Receiver Buffer 1 Register Receiver Buffer Status Register 04H 06H 10H 14H 16H 18H 1CH 1EH 20H 24H 28H 30H 32H 38H 3AH 3CH 3EH 40H 42H 44H 48H 4CH 50H 54H 58H 0000H 0000H 0000H 0000H 0000H 0000H 00CFH 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H Page 19-49 Page 19-50 Page 19-33 Page 19-28 Page 19-35 Page 19-36 Page 19-31 Page 19-51 Page 19-53 Page 19-42 Page 19-42 Page 19-42 Page 19-60 Page 19-62 Page 19-70 Page 19-50 Page 19-63 Page 19-68 Page 19-37 Page 19-37 Page 19-38 Page 19-39 Page 19-79 Page 19-73 Page 19-76 Page 19-80 Kernel State Configuration Register 0CH User's Manual USIC, UM_V0.2D5 19-14 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Table 19-3 Register Short Name RBUF Universal Serial Interface Channel USIC Kernel-Related and Kernel Registers (cont'd) Register Long Name Offset Addr. 5CH Reset Value 0000H 0000H 0000H 0000H Description see Page 19-79 Page 19-73 Page 19-76 Page 19-72 Receiver Buffer Register RBUF01SR Receiver Buffer 01 Status Register L 60H L RBUF01SR Receiver Buffer 01 Status Register H H TBUF00 to TBUF31 Transmit Buffer Input Locations 62H 80H to FFH FIFO Buffer Registers (once per USIC channel) BYP BYPCRL BYPCRH TRBPTRL TRBPTRH TBCTRL TBCTRH RBCTRL RBCTRH TRBSRL TRBSRH TRBSCR OUTRL OUTRH OUTDRL OUTDRH Bypass Data Register Bypass Control Register L Bypass Control Register H Transmit / Receive Buffer Pointer Register L Transmit / Receive Buffer Pointer Register H Transmit Buffer Control Register L Transmit Buffer Control Register H Receive Buffer Control Register L Receive Buffer Control Register H Transmit / Receive Buffer Status Register L Transmit / Receive Buffer Status Register H Transmit / Receive Buffer Status Clear Register Receive Buffer Output Register L Receive Buffer Output Register H Receive Buffer Output Register for Debugger L Receive Buffer Output Register for Debugger H 19-15 100H 104H 106H 108H 10AH 110H 112H 114H 116H 118H 11AH 11CH 120H 122H 124H 126H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0808H 0000H 0000H 0000H 0000H 0000H 0000H Page 19-91 Page 19-91 Page 19-93 Page 19-110 Page 19-110 Page 19-100 Page 19-100 Page 19-103 Page 19-103 Page 19-94 Page 19-97 Page 19-98 Page 19-108 Page 19-108 Page 19-109 Page 19-109 User's Manual USIC, UM_V0.2D5 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Table 19-3 Register Short Name IN00 to IN31 Universal Serial Interface Channel USIC Kernel-Related and Kernel Registers (cont'd) Register Long Name Offset Addr. Reset Value Description see Page 19-107 - Transmit FIFO Buffer Input Locations reserved reserved 180H to 0000H 1FFH 6CH 6EH 0000H 0000H All USIC registers (except bit field KSCFG. SUMCFG) are always reset by a class 3 reset. Bit field KSCFG.SUMCFG is reset by a class 1 reset. Note: The register bits marked "w" always deliver 0 when read. They are used to modify flipflops in other registers or to trigger internal actions. User's Manual USIC, UM_V0.2D5 19-16 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.2.2 Operating the USIC Communication Channel This section describes how to operate a USIC communication channel, including protocol control and status, mode control and interrupt handling. The following aspects have to be taken into account: * * * * * Enable the USIC module for operation and configure the behavior for the different device operation modes (see Section 19.2.2.2). Configure the pinning (refer to description in the corresponding protocol section). Configure the data structure (shift direction, word length, frame length, polarity, etc.). Configure the data buffer structure of the optional FIFO buffer area. A FIFO buffer can only be enabled if the related bit in register CCFG is set. Select a protocol by CCR.MODE. A protocol can only be selected if the related bit in register CCFG is set. 19.2.2.1 Protocol Control and Status The protocol-related status and control information are located in the protocol status register PSR and in the protocol control registers PCRL and PCRH. These registers are shared between all available protocols. As a consequence, the meaning of the bit positions in these registers changes with the selected protocol. Use of PCRL/H Bits The signification of the bits in registers PCRL/H is indicated by the alias names for the different protocols. Table 19-4 Bit CTR[0] CTR[1] CTR[2] CTR[3] CTR[4] CTR[5] CTR[6] CTR[7] CTR [12:8] CTR [15:13] Overview of PCRL/H Bits for the ASC Protocol Description Sample Mode Stop Bits Idle Detection Mode Sync.-Break Interrupt Enable Collision Detection Enable Receiver Noise Detection Interrupt Enable Format Error Interrupt Enable Frame Finished Interrupt Enable Sample Position Pulse Length Alias SMD STPB IDM SBIEN CDEN RNIEN FEIEN FFIEN SP PL User's Manual USIC, UM_V0.2D5 19-17 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Table 19-4 Bit others Table 19-5 Bit CTR[0] CTR[1] CTR[2] CTR[3] CTR [5:4] CTR [7:6] CTR [12:8] CTR[14] CTR[15] CTR [23:16] CTR[24] CTR[31] others Universal Serial Interface Channel Overview of PCRL/H Bits for the ASC Protocol (cont'd) Description Start-Stop of MCLK Reserved Overview of PCRL/H Bits for the SSC Protocol Alias Description MSLSEN MSLS Enable SELCTR Select Control SELINV FEM CTQ SEL1 PCTQ1 DCTQ1 MSLS IEN DX2T IEN SELO [7:0] TIWEN MCLK Select Inversion Frame End Mode Input Selection for CTQ Divider Factor to Generate fPDIV Divider Factor to Generate fTCTQ / RCTQ MSLS Interrupt Enable DX2T Interrupt Enable Select Output Enable Inter-Word Delay TIW Start Stop of-MCLK Reserved Alias CTR[31] MCLK Table 19-6 Bit CTR [15:0] CTR[16] CTR[17] Overview of PCRL/H Bits for the IIC Protocol Alias SLAD [15:0] ACK00 STIM Description Slave Address Acknowledge 00H Symbol Timing User's Manual USIC, UM_V0.2D5 19-18 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Table 19-6 Bit CTR[18] CTR[19] CTR[20] CTR[21] CTR[22] CTR[23] CTR[24] CTR[25] CTR [29:26] CTR[31] others Table 19-7 Bit CTR[0] CTR[1] CTR[2] CTR[4] CTR[5] CTR[6] Universal Serial Interface Channel Overview of PCRL/H Bits for the IIC Protocol (cont'd) Alias SCR IEN RSCR IEN PCR IEN NACK IEN ARL IEN SRR IEN ERR IEN SACK DIS HDEL MCLK Description Start Condition Received Interrupt Enable Repeated Start Condition Received Interrupt Enable Stop Condition Received Interrupt Enable Non-Acknowledge Interrupt Enable Arbitration Lost Interrupt Enable Slave Read Request Interrupt Enable Error Interrupt Enable Slave Acknowledge Disable Hardware Delay Start-Stop of MCLK Reserved Overview of PCRL/H Bits for the IIS Protocol Alias WAGEN DTEN SELINV WAFE IEN WARE IEN END IEN Description WA Generation Enable Data Transfers Enable Select Inversion WA Falling Edge Interrupt Enable WA Rising Edge Interrupt Enable END Interrupt Enable User's Manual USIC, UM_V0.2D5 19-19 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Table 19-7 Bit CTR[15] CTR [21:16] CTR[31] others Use of PSR Flags The signification of the flags in register PSR is indicated by the alias names for the different protocols. The setting by HW of flags marked "y" in the column "PI" are considered as protocol event and can generate a protocol interrupt (if enabled). Table 19-8 Bit ST[0] ST[1] ST[2] ST[3] ST[4] ST[5] ST[6] ST[7] ST[8] Overview of PSR Flags for the ASC Protocol Description Transmission Idle Reception Idle Synchronization Break Detected Collision Detected Receiver Noise Detected Format Error in Stop Bit 0 Format Error in Stop Bit 1 Receive Frame Finished Transmitter Frame Finished PI? y y y y y y y Universal Serial Interface Channel Overview of PCRL/H Bits for the IIS Protocol (cont'd) Alias DX2T IEN TDEL MCLK Description DX2T Interrupt Enable Transfer Delay Start-Stop of MCLK Reserved Alias TXIDLE RXIDLE SBD COL RNS FER0 FER1 RFF TFF Table 19-9 Bit ST[0] ST[1] ST[2] ST[3] Overview of PSR Flags for the SSC Protocol Description MSLS Status DX2S Status DX2T Event Detected PI? y y Alias MSLS DX2S DX2TEV MSLSEV MSLS Event Detected User's Manual USIC, UM_V0.2D5 19-20 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel Table 19-10 Overview of PSR Flags for the IIC Protocol Bit ST[0] ST[1] ST[2] ST[3] ST[4] ST[5] ST[6] ST[7] ST[8] Alias SLSEL WTDF SCR RSCR PCR NACK ARL SRR ERR Description Slave Select Wrong TDF Code Start Condition Received Repeated Start Condition Received Stop Condition Received Non-Acknowledge Received Arbitration Lost Slave Read Request Error PI? y y y y y y y y Table 19-11 Overview of PSR Flags for the IIS Protocol Bit ST[0] ST[1] ST[3] ST[4] ST[5] ST[6] Alias WA DX2S DX2T EV WAFE WARE END Description Word Address DX2S Status DX2T Event Detected WA Falling Edge Event Detected WA Rising Edge Event Detected WA Generation End PI? y y y y 19.2.2.2 Mode Control The mode control concept for system control tasks, such as power saving, or suspend request for debugging, allows to program the module behavior under different device operating conditions. The behavior of a communication channel can be programmed for each of the device operating modes, that are requested by the global state control part of the SCU. Therefore, each communication channel has an associated register KSCFG defining its behavior in the following operating modes: * Normal operation: This operating mode is the default operating mode when neither a suspend request nor a clock-off request are pending. The module clock is not switched off and the USIC registers can be read or written. The channel behavior is defined by KSCFG.NOMCFG. User's Manual USIC, UM_V0.2D5 19-21 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary * Universal Serial Interface Channel * Suspend mode: This operating mode is requested when a suspend request is pending in the device. The module clock is not switched off and the USIC registers can be read or written. The channel behavior is defined by KSCFG.SUMCFG. Clock-off mode: This operating mode is requested for power saving purposes. The module clock is switched off automatically when all channels of the USIC module reached their specified state in a stop mode. In this case, USIC registers can not be accessed. The channel behavior is defined by KSCFG.COMCFG. The behavior of a USIC communication channel can be programmed for each of the device operating modes (normal operation, suspend mode, clock-off mode). Therefore, the USIC communication channel provides four kernel modes, as shown in Table 19-12. Table 19-12 USIC Communication Channel Behavior Kernel Mode run mode 0 run mode 1 stop mode 0 stop mode 1 explicit stop condition as described in the protocol chapters Channel Behavior channel operation as specified, no impact on data transfer Code 00B 01B 10B 11B Generally, bit field KSCFG.NOMCFG should be configured for run mode 0 as default setting for standard operation. If a communication channel should not react to a suspend request (and to continue its operation as in normal mode), bit field KSCFG.SUMCFG has to be configured with the same value as KSCFG.NOMCFG. If the communication channel should show a different behavior and stop operation when a specific stop condition is reached, the code for stop mode 0 or stop mode 1 have to be written to KSCFG.SUMCFG. A similar mechanism applies for the clock-off mode with the possibility to program the desired behavior by bit field KSCFG.COMCFG. The stop conditions are defined for the selected protocol (see mode control description in the protocol section). Note: The stop mode selection strongly depends on the application needs and it is very unlikely that different stop modes are required in parallel in the same application. As a result, only one stop mode type (either 0 or 1) should be used in the bit fields in register KSCFG. Do not mix stop mode 0 and stop mode 1 and avoid transitions from stop mode 0 to stop mode 1 (or vice versa) for the same communication channel. If the module clock is disabled by KSCFG.MODEN = 0 or in clock-off mode when the stop condition is reached (in stop mode 0 or 1), the module can not be accessed by read or write operations (except register KSCFG that can always be accessed). User's Manual USIC, UM_V0.2D5 19-22 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.2.2.3 General Channel Events and Interrupts The general event and interrupt structure is shown in Figure 19-6. If a defined condition is met, an event is detected and an event indication flag becomes automatically set. The flag stays set until it is cleared by SW. If enabled, an interrupt can be generated if an event is detected. The actual status of the event indication flag has no influence on the interrupt generation. As a consequence, the event indication flag does not need to be cleared to generate further interrupts. Additionally, the service request output SRx of the USIC channel that becomes activated in case of an event can be selected by an interrupt node pointer. This structure allows to assign events to interrupts, e.g. depending on the application, several events can share the same interrupt routine (several events activate the same SRx output) or can be handled individually (only one event activates an SRx output). The SRx outputs are connected to interrupt control registers to handle the CPU reaction to the service requests. This assignment is described in the implementation chapter, see Section 19.7.4. clear event indication event condition met clear event indication set event interrupt enable AND interrupt node pointer interrupt to INT_O0 to INT_O3 USIC_gen_ints ... Figure 19-6 General Event and Interrupt Structure User's Manual USIC, UM_V0.2D5 19-23 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.2.2.4 Data Transfer Events and Interrupts The data transfer events are based on the transmission or reception of a data word. The related indication flags are located in register PSR. All events can be individually enabled for interrupt generation. * Receive event to indicate that a data word has been received: If a new received word becomes available in the receive buffer RBUF, either a receive event or an alternative receive event occurs. The receive event occurs if bit RBUFSR.PERR = 0. It is indicated by flag PSR.RIF and can lead to a receive interrupt (if enabled). Receiver start event to indicate that a data word reception has started: When the receive clock edge that shifts in the first bit of a new data word is detected and reception is enabled, a receiver start event occurs. It is indicated by flag PSR.RSIF and can lead to a transmit buffer interrupt (if enabled). In full duplex mode, this event follows half a shift clock cycle after the transmit buffer event and indicates when the shift control settings are internally "frozen" for the current data word reception and a new setting can be programmed. In SSC and IIS mode, the transmit data valid flag TCSRL.TDV is cleared in single shot mode with the receiver start event. Alternative receive event to indicate that a specific data word has been received: If a new received word becomes available in the receive buffer RBUF, either a receive event or an alternative receive event occurs. The alternative receive event occurs if bit RBUFSR.PERR = 1. It is indicated by flag PSR.AIF and can lead to an alternative receive interrupt (if enabled). Depending on the selected protocol, bit RBUFSR.PERR is set to indicate a parity error in ASC mode, the reception of the first byte of a new frame in IIC mode, and the WA information about right/left channel in IIS mode, whereas it is always 0 in SSC mode. Transmit shift event to indicate that a data word has been transmitted: A transmit shift event occurs with the last shift clock edge of a data word. It is indicated by flag PSR.TSIF and can lead to a transmit shift interrupt (if enabled). Transmit buffer event to indicate that a data word transmission has been started: When a data word from the transmit buffer TBUF has been loaded to the shift register and a new data word can be written to TBUF, a transmit buffer event occurs. This happens with the transmit clock edge that shifts out the first bit of a new data word and transmission is enabled. It is indicated by flag PSR.TBIF and can lead to a transmit buffer interrupt (if enabled). This event also indicates when the shift control settings (word length, shift direction, etc.) are internally "frozen" for the current data word transmission. In ASC and IIC mode, the transmit data valid flag TCSRL.TDV is cleared in single shot mode with the transmit buffer event. Data lost event to indicate a loss of the oldest received data word: If the data word available in register RBUF (oldest data word from RBUF0 or RBUF1) 19-24 V1.0, 2007-06 * * * * * User's Manual USIC, UM_V0.2D5 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel has not been read out before it becomes overwritten with new incoming data, this event occurs. It is indicated by flag PSR.DLIF and can lead to a protocol interrupt (if enabled). The table below shows the registers, bits and bit fields indicating the data transfer events and controlling the interrupts of a USIC channel. Table 19-13 Data Transfer Events and Interrupt Handling Event Receive event Receiver start event Alternative receive event Transmit shift event Transmit buffer event Data lost event Indication Flag PSR. RIF PSR. RSIF PSR. AIF PSR. TSIF PSR. TBIF PSR. DLIF Indication cleared by PSCR. CRIF PSCR. CRSIF PSCR. CAIF PSCR. CTSIF PSCR. CTBIF PSCR. CDLIF Interrupt enabled by CCR. RIEN CCR. RSIEN CCR. AIEN CCR. TSIEN CCR. TBIEN CCR. DLIEN SRx Output selected by INPRL. RINP INPRL. TBINP INPRL. AINP INPRL. TSINP INPRL. TBINP INPRH. PINP The following figure shows the transmit events and interrupts. CTSIF end of last transmit shift clock period of data word clear TSIF set transmit shift event TSIEN AND TSINP transmit shift interrupt to INT_O to INT_O ... CTBIF first transmit shift clock of data word clear TBIF set transmit buffer event TBIEN AND transmit buffer interrupt TBINP to INT_O to INT_O USIC_transm_in ... Figure 19-7 Transmit Events and Interrupts User's Manual USIC, UM_V0.2D5 19-25 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel The following figure shows the receive events and interrupts. CRIF new data in RBUF PERR clear RIF set standard receive event RIEN AND standard receive interrupt RINP to INT_O to INT_O to INT_O to INT_O ... 0 1 alternative receive event AND alternative receive interrupt ... set CAIF clear AIF AIEN AINP CRSIF first receive shift clock of data word clear RSIF set receive start event RSIEN AND receive start interrupt TBINP to INT_O to INT_O ... CDLIF RBUF becomes overwritten without having been read out clear DLIF set data lost event DLIEN AND data lost interrupt PINP to INT_O to INT_O USIC_rec_in ... Figure 19-8 Receive Events and Interrupts User's Manual USIC, UM_V0.2D5 19-26 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.2.2.5 Protocol-specific Events and Interrupts These events are related to protocol-specific actions that are described in the corresponding protocol chapters. The related indication flags are located in register PSR. All events can be individually enabled for the generation of the common protocol interrupt. * Protocol-specific events in ASC mode: Synchronization break, data collision on the transmit line, receiver noise, format error in stop bits, receiver frame finished, transmitter frame finished Protocol-specific events in SSC mode: MSLS event (start-end of frame in master mode), DX2T event (start/end of frame in slave mode), both based on slave select signals Protocol-specific events in IIC mode: Wrong transmit code (error in frame sequence), start condition received, repeated start condition received, stop condition received, non-acknowledge received, arbitration lost, slave read request, other general errors Protocol-specific events in IIS mode: DX2T event (change on WA line), WA falling edge or rising edge detected, WA generation finished * * * Table 19-14 Protocol-specific Events and Interrupt Handling Event Protocol-specific events in ASC mode Protocol-specific events in SSC mode Protocol-specific events in IIC mode Protocol-specific events in IIS mode Indication Flag PSR. ST[8:2] PSR. ST[3:2] PSR. ST[8:1] PSR. ST[6:3] Indication cleared by PSCR. CST[8:2] PSCR. CST[3:2] PSCR. CST[8:1] PSCR. CST[6:3] Interrupt enabled by PCRL. CTR[7:3] PCRL. CTR[15:14] PCRH. CTR[24:18] PCRL. CTR[6:4], PCRL. CTR[15] SRx Output selected by INPRH. PINP INPRH. PINP INPRH. PINP INPRH. PINP User's Manual USIC, UM_V0.2D5 19-27 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.2.3 Channel Control and Configuration Registers 19.2.3.1 Channel Control Register The channel control register contains the enable/disable bits for interrupt generation on channel events, the control of the parity generation and the protocol selection of a USIC channel. CCR Channel Control Register 15 AI EN rw 14 RI EN rw 13 TBI EN rw 12 TSI EN rw 11 DLI EN rw 10 RSI EN rw 9 PM rw (10H) 8 7 6 0 r 5 4 Reset Value: 0000H 3 2 1 0 MODE rw Field MODE Bits [3:0] Type Description rw Operating Mode This bit field selects the protocol for this USIC channel. Selecting a protocol that is not available (see register CCFG) or a reserved combination disables the USIC channel. When switching between two protocols, the USIC channel has to be disabled before selecting a new protocol. In this case, registers PCRH, PCRL, and PSR have to be cleared or updated by SW. 00H The USIC channel is disabled. All protocolrelated state machines are set to an idle state. 01H The SSC (SPI) protocol is selected. 02H The ASC (SCI, UART) protocol is selected. 03H The IIS protocol is selected. 04H The IIC protocol is selected. else reserved User's Manual USIC, UM_V0.2D5 19-28 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field PM Bits [9:8] Type Description rw Parity Mode This bit field defines the parity generation of the sampled input values. 00B The parity generation is disabled. 01B reserved 10B Even parity is selected (parity bit = 1 on odd number of 1s in data, parity bit = 0 on even number of 1s in data). 11B Odd parity is selected (parity bit = 0 on odd number of 1s in data, parity bit = 1 on even number of 1s in data). Receiver Start Interrupt Enable This bit enables the interrupt generation in case of a receiver start event. 0B The receiver start interrupt is disabled. The receiver start interrupt is enabled. 1B In case of a receiver start event, the service request output SRx indicated by INPRL.TBINP is activated. Data Lost Interrupt Enable This bit enables the interrupt generation in case of a data lost event (data received in RBUFx while RDVx = 1). 0B The data lost interrupt is disabled. 1B The data lost interrupt is enabled. In case of a data lost event, the service request output SRx indicated by INPRH.PINP is activated. Transmit Shift Interrupt Enable This bit enables the interrupt generation in case of a transmit shift event. 0B The transmit shift interrupt is disabled. 1B The transmit shift interrupt is enabled. In case of a transmit shift interrupt event, the service request output SRx indicated by INPRL.TSINP is activated. Universal Serial Interface Channel RSIEN 10 rw DLIEN 11 rw TSIEN 12 rw User's Manual USIC, UM_V0.2D5 19-29 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field TBIEN Bits 13 Type Description rw Transmit Buffer Interrupt Enable This bit enables the interrupt generation in case of a transmit buffer event. 0B The transmit buffer interrupt is disabled. 1B The transmit buffer interrupt is enabled. In case of a transmit buffer event, the service request output SRx indicated by INPRL.TBINP is activated. Receive Interrupt Enable This bit enables the interrupt generation in case of a receive event. 0B The receive interrupt is disabled. 1B The receive interrupt is enabled. In case of a receive event, the service request output SRx indicated by INPRL.RINP is activated. Alternative Receive Interrupt Enable This bit enables the interrupt generation in case of a alternative receive event. 0B The alternative receive interrupt is disabled. 1B The alternative receive interrupt is enabled. In case of an alternative receive event, the service request output SRx indicated by INPRL.AINP is activated. Reserved read as 0; should be written with 0. Universal Serial Interface Channel RIEN 14 rw AIEN 15 rw 0 [7:4] r User's Manual USIC, UM_V0.2D5 19-30 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.2.3.2 Channel Configuration Register The channel configuration register contains bits describing the functionality that is available in the USIC channel. CCFG Channel Configuration Register 15 14 13 12 0 r 11 10 9 (18H) 8 7 TB r 6 RB r 5 0 r 4 Reset Value: 00CFH 3 IIS r 2 IIC r 1 0 ASC SSC r r Field SSC Bits 0 Type Description r SSC Protocol Available This bit indicates if the SSC protocol is available. 0B The SSC protocol is not available. 1B The SSC protocol is available. ASC Protocol Available This bit indicates if the ASC protocol is available. The ASC protocol is not available. 0B 1B The ASC protocol is available. IIC Protocol Available This bit indicates if the IIC functionality is available. 0B The IIC protocol is not available. The IIC protocol is available. 1B IIS Protocol Available This bit indicates if the IIS protocol is available. 0B The IIS protocol is not available. 1B The IIS protocol is available. Receive FIFO Buffer Available This bit indicates if an additional receive FIFO buffer is available. 0B A receive FIFO buffer is not available. 1B A receive FIFO buffer is available. Transmit FIFO Buffer Available This bit indicates if an additional transmit FIFO buffer is available. 0B A transmit FIFO buffer is not available. 1B A transmit FIFO buffer is available. 19-31 V1.0, 2007-06 ASC 1 r IIC 2 r IIS 3 r RB 6 r TB 7 r User's Manual USIC, UM_V0.2D5 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field 0 Bits [5:4], [15:8] Type Description r Reserved read as 0; should be written with 0. Universal Serial Interface Channel User's Manual USIC, UM_V0.2D5 19-32 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.2.3.3 Kernel State Configuration Register The kernel state configuration register KSCFG allows the selection of the desired kernel modes for the different device operating modes. KSCFG Kernel State Configuration Register 15 BP COM w 14 0 r 13 12 11 BP SUM w 10 0 r 9 (0CH) 8 7 BP NOM w 6 0 r 5 4 Reset Value: 0000H 3 0 r 2 0 r 1 0 BP MOD MOD EN EN w rw COMCFG rw SUMCFG rw NOMCFG rw Field MODEN Bits 0 Type Description rw Module Enable This bit enables the module kernel clock and the module functionality. 0B The module is switched off immediately (without respecting a stop condition). It does not react on mode control actions and the module clock is switched off. The module does not react on read accesses and ignores write accesses (except to KSCFG). 1B The module is switched on and can operate. After writing 1 to MODEN, it is recommended to read register KSCFG to avoid pipeline effects in the control block before accessing other ADC registers. Bit Protection for MODEN This bit enables the write access to the bit MODEN. It always reads 0. 0B MODEN is not changed. 1B MODEN is updated with the written value. Normal Operation Mode Configuration This bit field defines the kernel mode applied in normal operation mode. 00B Run mode 0 is selected. 01B Run mode 1 is selected. 10B Stop mode 0 is selected. 11B Stop mode 1 is selected. BPMODEN 1 w NOMCFG [5:4] rw User's Manual USIC, UM_V0.2D5 19-33 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field BPNOM Bits 7 Type Description w Bit Protection for NOMCFG This bit enables the write access to the bit field NOMCFG. It always reads 0. 0B NOMCFG is not changed. 1B NOMCFG is updated with the written value. Suspend Mode Configuration This bit field defines the kernel mode applied in suspend mode. Coding like NOMCFG. Bit Protection for SUMCFG This bit enables the write access to the bit field SUMCFG. It always reads 0. 0B SUMCFG is not changed. 1B SUMCFG is updated with the written value. Clock Off Mode Configuration This bit field defines the kernel mode applied in clock-off mode. Coding like NOMCFG. Bit Protection for COMCFG This bit enables the write access to the bit field COMCFG. It always reads 0. 0B COMCFG is not changed. 1B COMCFG is updated with the written value. Reserved returns 0 if read; should be written with 0; Universal Serial Interface Channel SUMCFG [9:8] rw BPSUM 11 w COMCFG [13:12] rw BPCOM 15 w 0 [3:2], 6, 10, 14 r User's Manual USIC, UM_V0.2D5 19-34 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.2.3.4 Interrupt Node Pointer Registers The interrupt node pointer registers define the service request output SRx that is activated if the corresponding event occurs and interrupt generation is enabled. INPRL Interrupt Node Pointer Register L 15 0 r 14 13 12 11 0 r 10 9 (14H) 8 7 0 r 6 5 4 Reset Value: 0000H 3 0 r 2 1 0 AINP rw RINP rw TBINP rw TSINP rw Field TSINP Bits [1:0] Type Description rw Transmit Shift Interrupt Node Pointer This bit field defines which service request output SRx will be activated in case of a transmit shift interrupt. 00B Output SR0 will be activated. 01B Output SR1 will be activated. 10B Output SR2 will be activated. 11B Output SR3 will be activated. Transmit Buffer Interrupt Node Pointer This bit field defines which service request output SRx will be activated in case of a transmit buffer interrupt or a receive start interrupt. Coding like TSINP. Receive Interrupt Node Pointer This bit field defines which service request output SRx will be activated in case of a receive interrupt. Coding like TSINP. Alternative Receive Interrupt Node Pointer This bit field defines which service request output SRx will be activated in case of a alternative receive interrupt. Coding like TSINP. Reserved read as 0; should be written with 0. TBINP [5:4] rw RINP [9:8] rw AINP [13:12] rw 0 [3:2], [7:6], [11:10], [15:14] r User's Manual USIC, UM_V0.2D5 19-35 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary INPRH Interrupt Node Pointer Register H 15 14 13 12 11 10 9 0 r Universal Serial Interface Channel (16H) 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 PINP rw Field PINP Bits [1:0] Type Description rw Protocol Interrupt Node Pointer This bit field defines which service request output SRx will be activated in case of a protocol interrupt. 00B Output SR0 will be activated. 01B Output SR1 will be activated. 10B Output SR2 will be activated. 11B Output SR3 will be activated. Reserved read as 0; should be written with 0. 0 [15:2] r User's Manual USIC, UM_V0.2D5 19-36 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.2.4 Protocol Related Registers 19.2.4.1 Protocol Control Registers The bits in the protocol control registers define protocol-specific functions. They have to be configured by SW before enabling a new protocol. Only the bits used for the selected protocol are taken into account, whereas the other bit positions always read as 0. The protocol-specific meaning is described in the related protocol section. PCRL Protocol Control Register L 15 14 13 12 11 10 9 (40H) 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 CTR CTR CTR CTR CTR CTR CTR CTR CTR CTR CTR CTR CTR CTR CTR CTR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Field CTRx (x = 15-0) Bits x Type Description rw Protocol Control Bit x This bit is a protocol control bit. PCRH Protocol Control Register H 15 14 13 12 11 10 9 (42H) 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 CTR CTR CTR CTR CTR CTR CTR CTR CTR CTR CTR CTR CTR CTR CTR CTR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh Field CTRx (x = 30-16) CTR31 Bits x - 16 Type Description rwh Protocol Control Bit x This bit is a protocol control bit that can be overwritten by protocol-specific information. Start Stop Control of MCLK This bit controls the start and the stop of the MCLK signal. 0B Signal MCLK is not generated (MCLK = 0). 1B Signal MCLK generation is enabled. 15 rwh User's Manual USIC, UM_V0.2D5 19-37 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.2.4.2 Protocol Status Register The flags in the protocol status register can be cleared by writing a 1 to the corresponding bit position in register PSCR. Writing a 1 to a bit position in PSR sets the corresponding flag, but doesn't lead to further actions (no interrupt generation). Writing a 0 has no effect. These flags should be cleared by SW before enabling a new protocol. The protocol-specific meaning is described in the related protocol section. PSR Protocol Status Register 15 AIF rwh 14 13 12 11 10 9 ST 9 rwh (44H) 8 ST 8 rwh 7 ST 7 rwh 6 ST 6 rwh 5 ST 5 rwh 4 ST 4 rwh Reset Value: 0000H 3 ST 3 rwh 2 ST 2 rwh 1 ST 1 rwh 0 ST 0 rwh RIF TBIF TSIF DLIF RSIF rwh rwh rwh rwh rwh Field STx (x = 9-0) RSIF Bits x 10 Type Description rwh rwh Protocol Status Flag x See protocol specific description. Receiver Start Indication Flag A receiver start event has not occurred. 0B 1B A receiver start event has occurred. Data Lost Indication Flag 0B A data lost event has not occurred. 1B A data lost event has occurred. Transmit Shift Indication Flag 0B A transmit shift event has not occurred. 1B A transmit shift event has occurred. Transmit Buffer Indication Flag A transmit buffer event has not occurred. 0B 1B A transmit buffer event has occurred. Receive Indication Flag 0B A receive event has not occurred. 1B A receive event has occurred. Alternative Receive Indication Flag 0B An alternative receive event has not occurred. 1B An alternative receive event has occurred. DLIF 11 rwh TSIF 12 rwh TBIF 13 rwh RIF 14 rwh AIF 15 rwh User's Manual USIC, UM_V0.2D5 19-38 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.2.4.3 Protocol Status Clear Register Read accesses to this register always deliver 0 at all bit positions. PSCR Protocol Status Clear Register 15 C AIF w 14 13 12 11 10 9 (48H) 8 C ST 8 w 7 C ST 7 w 6 C ST 6 w 5 C ST 5 w 4 C ST 4 w Reset Value: 0000H 3 C ST 3 w 2 C ST 2 w 1 C ST 1 w 0 C ST 0 w C C C C C C ST RIF TBIF TSIF DLIF RSIF 9 w w w w w w Field CSTx (x = 9-0) CRSIF Bits x Type Description w Clear Status Flag x in PSR 0B No action 1B Flag PSR.STx is cleared. Clear Receiver Start Indication Flag 0B No action 1B Flag PSR.RSIF is cleared. Clear Data Lost Indication Flag 0B No action Flag PSR.DLIF is cleared. 1B Clear Transmit Shift Indication Flag 0B No action 1B Flag PSR.TSIF is cleared. Clear Transmit Buffer Indication Flag 0B No action 1B Flag PSR.TBIF is cleared. Clear Receive Indication Flag 0B No action 1B Flag PSR.RIF is cleared. Clear Alternative Receive Indication Flag 0B No action 1B Flag PSR.AIF is cleared. 10 w CDLIF 11 w CTSIF 12 w CTBIF 13 w CRIF 14 w CAIF 15 w User's Manual USIC, UM_V0.2D5 19-39 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.2.5 Operating the Input Stages All three input stages offer the same feature set. They are used for all protocols, because the signal conditioning can be adapted in a very flexible way and the digital filters can be switched on and off separately. 19.2.5.1 General Input Structure All input stages are built in a similar way as shown in Figure 19-9. All enable/disable functions and selections are controlled independently for each input stage by bits in the registers DX0CR, DX1CR, and DX2CR. The desired input signal can be selected among the input lines DXnA to DXnG and a permanent 1-level by programming bit field DSEL. Please refer to the implementation chapter for the device-specific input signal assignment. Bit DPOL allows a polarity inversion of the selected input signal to adapt the input signal polarity to the internal polarity of the data shift unit and the protocol state machine. For some protocols, the input signals can be directly forwarded to the data shift unit for the data transfers (DSEN = 0, INSW = 1) without any further signal conditioning. In this case, the data path does not contain any delay due to synchronization or filtering. In the case of noise on the input signals, there is the possibility to synchronize the input signal (signal DXnS is synchronized to fSYS) and additionally to enable a digital noise filter in the signal path. The synchronized input signal (and optionally filtered if DFEN = 1) is taken into account by DSEN = 1. Please note that the synchronization leads to a delay in the signal path of 2-3 times the period of fSYS. DSEL DPOL 0 DSEN 0 1 INSW 1 0 DXnA DXnB . .. 000 1 001 110 111 . .. data shift unit protocol preprocessor DXnT DXnG 1 DXnINS DXnS digital filter DFEN edge detect. CM USIC_input_condit Figure 19-9 Input Conditioning If the input signals are handled by a protocol pre-processor, the data shift unit is directly connected to the protocol pre-processor by INSW = 0. The protocol pre-processor is User's Manual USIC, UM_V0.2D5 19-40 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel connected to the synchronized input signal DXnS and, depending on the selected protocol, also evaluates the edges. 19.2.5.2 Digital Filter The digital filter can be enabled to reduce noise on the input signals. Before being filtered, the input signal becomes synchronized to fSYS. If the filter is disabled, signal DXnS corresponds to the synchronized input signal. If the filter is enabled, pulses shorter than one filter sampling period are suppressed in signal DXnS. After an edge of the synchronized input signal, signal DXnS changes to the new value if two consecutive samples of the new value have been detected. In order to adapt the filter sampling period to different applications, it can be programmed. The first possibility is the system frequency fSYS. Longer pulses can be suppressed if the fractional divider output frequency fFD is selected. This frequency is programmable in a wide range and can also be used to determine the baud rate of the data transfers. In addition to the synchronization delay of 2-3 periods of fSYS, an enabled filter adds a delay of up to two filter sampling periods between the selected input and signal DXnS. 19.2.5.3 Edge Detection The synchronized (and optionally filtered) signal DXnS can be used as input to the data shift unit and is also an input to the selected protocol pre-processor. If the protocol preprocessor does not use the DXnS signal for protocol-specific handling, DXnS can be used for other tasks, e.g. to control data transmissions in master mode (a data word can be tagged valid for transmission, see chapter about data buffering). A programmable edge detection indicates that the desired event has occurred by activating the trigger signal DXnT (introducing a delay of one period of fSYS before a reaction to this event can take place). 19.2.5.4 Selected Input Monitoring The selected input signal of each input stage has been made available with the signals DX0INS, DX1INS, and DX2INS. These signals can be used in the system to trigger other actions, e.g. to generate interrupts. 19.2.5.5 Loop Back Mode The USIC transmitter output signals can be connected to the corresponding receiver inputs of the same communication channel in loop back mode. Therefore, the input "G" of the input stages that are needed for the selected protocol have to be selected. In this case, drivers for ASC, SSC, and IIS can be evaluated on-chip without the connections to port pins. Data transferred by the transmitter can be received by the receiver as if it would have been sent by another communication partner. User's Manual USIC, UM_V0.2D5 19-41 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.2.6 Input Stage Registers 19.2.6.1 Input Control Registers The input control registers contain the bits to define the characteristics of the input stages (input stage DX0 is controlled by register DX0CR, etc.). DX0CR Input Control Register 0 DX1CR Input Control Register 1 DX2CR Input Control Register 2 15 DXS rh 14 13 0 r 12 11 CM rw 10 9 (20H) (24H) (28H) 8 7 0 r 6 DS EN rw 5 DF EN rw 4 IN SW rw Reset Value: 0000H Reset Value: 0000H Reset Value: 0000H 3 0 r 2 1 DSEL rw 0 SF D SEL POL rw rw Field DSEL Bits [2:0] Type Description rw Data Selection for Input Signal This bit field defines the input data signal for the corresponding input line for protocol pre-processor. The selection can be made from the input vector DXn[G:A]. 000B The data input DXnA is selected. 001B The data input DXnB is selected. ... 110B The data input DXnG is selected. 111B The data input is always 1. Input Switch This bit defines if the data shift unit input is derived from the input data path DXn or from the selected protocol pre-processors. 0B The input of the data shift unit is controlled by the protocol pre-processor. 1B The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol preprocessor. 19-42 V1.0, 2007-06 INSW 4 rw User's Manual USIC, UM_V0.2D5 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field DFEN Bits 5 Type Description rw Digital Filter Enable This bit enables/disables the digital filter for signal DXnS. 0B The input signal is not digitally filtered. 1B The input signal is digitally filtered. Data Synchronization Enable This bit selects if the asynchronous input signal or the synchronized (and optionally filtered) signal DXnS can be used as input for the data shift unit. The unsynchronized signal can be taken as 0B input for the data shift unit. 1B The synchronized signal can be taken as input for the data shift unit. Data Polarity for DXn This bit defines the signal polarity of the input signal. 0B The input signal is not inverted. 1B The input signal is inverted. Sampling Frequency Selection This bit defines the sampling frequency of the digital filter for the synchronized signal DXnS. The sampling frequency is fSYS. 0B 1B The sampling frequency is fFD. Combination Mode This bit field selects which edge of the synchronized (and optionally filtered) signal DXnS actives the trigger output DXnT of the input stage. 00B The trigger activation is disabled. 01B A rising edge activates DXnT. 10B A falling edge activates DXnT. 11B Both edges activate DXnT. Synchronized Data Value This bit indicates the value of the synchronized (and optionally filtered) input signal. 0B The current value of DXnS is 0. 1B The current value of DXnS is 1. Reserved read as 0; should be written with 0. Universal Serial Interface Channel DSEN 6 rw DPOL 8 rw SFSEL 9 rw CM [11:10] rw DXS 15 rh 0 3, 7, r [14:12] User's Manual USIC, UM_V0.2D5 19-43 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.2.7 Operating the Baud Rate Generator The following blocks can be configured to operate the baud rate generator. 19.2.7.1 Fractional Divider The fractional divider generates its output frequency fFD by dividing the input frequency fSYS either by an integer factor n or by multiplication by n/1024. It has two operating modes: * Normal divider mode (FDRL.DM = 01B): In this mode, the output frequency fFD is derived from the input clock fSYS by an integer division by a value between 1 and 1024. The division is based on a counter FDRH.RESULT that is incremented by 1 with fSYS. After reaching the value 3FFH, the counter is loaded with FDRL.STEP and then continues counting. In order to achieve fFD = fSYS, the value of STEP has to be programmed with 3FFH. The output frequency in normal divider mode is defined by the equation: (19.1) f FD * 1 = f SYS x -n with n = 1024 - STEP Fractional divider mode (FDRL.DM = 10B): In this mode, the output frequency fFD is derived from the input clock fSYS by a fractional multiplication by n/1024 for a value of n between 0 and 1023. In general, the fractional divider mode allows to program the average output clock frequency with a finer granularity than in normal divider mode. Please note that in fractional divider mode fFD can have a maximum period jitter of one fSYS period. This jitter is not accumulated over several cycles. The frequency fFD is generated by an addition of FDRL.STEP to FDRH.RESULT with fSYS. The frequency fFD is based on the overflow of the addition result over 3FFH. The output frequency in fractional divider mode is defined by the equation: (19.2) f FD n = f SYS x ----------1024 with n = STEP The output frequency fFD of the fractional divider is selected for baud rate generation by BRGL.CLKSEL = 00B. 19.2.7.2 External Frequency Input The baud rate can be generated referring to an external frequency input (instead of to fSYS) if in the selected protocol the input stage DX1 is not needed (DX1CTR.INSW = 0). In this case, an external frequency input signal at the DX1 input stage can be synchronized and sampled with the system frequency fSYS. It can be optionally filtered by the digital filter in the input stage. This feature allows data transfers with frequencies User's Manual USIC, UM_V0.2D5 19-44 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel that can not be generated by the device itself, e.g. for specific audio frequencies. If BRGL.CLKSEL = 10B, the trigger signal DX1T determines fDX1. In this mode, either the rising edge, the falling edge, or both edges of the input signal can be used for baud rate generation, depending on the configuration of the DX1T trigger event by bit field DX1CTR.CM. The signal MCLK toggles with each trigger event of DX1T. If BRGL.CLKSEL = 11B, the rising edges of the input signal can be used for baud rate generation. The signal MCLK represents the synchronized input signal DX1S. Both, the high time and the low time of external input signal must each have a length of minimum 2 periods of fSYS to be used for baud rate generation. 19.2.7.3 Protocol-Related Counter in Divider Mode In divider mode, the protocol-related counter is used for an integer division delivering the output frequency fPDIV. Additionally, two divider stages with a fixed division by 2 provide the output signals MCLK and SCLK with 50% duty cycle. If the fractional divider mode is used, the maximum fractional jitter of 1 period of fSYS can also appear in these signals. The outputs frequencies of this divider is controlled by registers BRGL and BRGH. In order to define a frequency ratio between the master clock MCLK and the shift clock SCLK, the divider stage for MCLK is located in front of the divider by PDIV+1, whereas the divider stage for SCLK is located at the output of this divider. (19.3) f MCLK f PIN = --------2 (19.4) f SCLK f PDIV = ------------2 In the case that the master clock is used as reference for external devices (e.g. for IIS components) and a fixed phase relation to SCLK and other timing signals is required, it is recommended to use the MCLK signal as input for the PDIV divider. If the MCLK signal is not used or a fixed phase relation is not necessary, the faster frequency fPIN can be selected as input frequency. (19.5) f PDIV 1 f PIN x ----------------------PDIV + 1 = 1 f MCLK x ---------------------- PDIV + 1 if if PPPEN = 0 PPPEN = 1 User's Manual USIC, UM_V0.2D5 19-45 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 11 10 01 fCTQIN fPIN 00 divide by 2 fMCLK 0 1 fPPP divide by PDIV+1 fPDIV divide by 2 fSCLK SCLK MCLK PPPEN TMEN = 0 CTQSEL USIC_PDIV_TMEN0 Figure 19-10 Protocol-Related Counter (Divider Mode) 19.2.7.4 Protocol-Related Counter in Capture Mode In capture mode, the protocol-related counter stage can be used for time interval measurement (BRGL.TMEN = 1). In this case, the frequency division is disabled (reception and transmission are not possible) and the counter is working as capture timer by counting fPPP periods. When reaching its maximum value, the counter stops counting. If an event is indicated by DX0T or DX1T, the actual counter value is captured into bit field BRGH.PDIV and the counter restarts from 0. Additionally, a transmit shift interrupt event is generated (bit PSRL.TSIF becomes set). fPIN DX0T clear OR DX1T capture divide by 2 fMCLK 0 1 fPPP up counter value capture in PDIV MCLK PPPEN TMEN = 1 USIC_PDIV_TMEN1 Figure 19-11 Protocol-Related Counter (Capture Mode) The capture mode can be used to measure the baud rate in slave mode before starting data transfers, e.g. to measure the time between two edges of a data signal (by DX0T) User's Manual USIC, UM_V0.2D5 19-46 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel or of a shift clock signal (by DX1T). The conditions to activate the DXnT trigger signals can be configured in each input stage. 19.2.7.5 Time Quanta Counter The time quanta counter CTQ associated to the protocol pre-processor allows to generate time intervals for protocol-specific purposes. The length of a time quantum tq is given by the selected input frequency fCTQIN and the programmed pre-divider value. The meaning of the time quanta depend on the selected protocol, please refer to the corresponding chapters for more protocol-specific information. fCTQIN pre-divider tq time quanta counter CTQ DCTQ protocol preprocessor PCTQ Figure 19-12 Time Quanta Counter USIC_CTQ 19.2.7.6 Shift Clock Output Configuration The master clock output signal MCLKOUT available at the corresponding output pin can be configured in polarity. The MCLK signal can be generated for each protocol in order to provide a kind of higher frequency time base compared to the shift clock. The configuration mechanism of the master clock output signal MCLKOUT ensures that no shortened pulses can occur. Each MCLK period consists of two phases, an active phase, followed by a passive phase. The polarity of the MCLKOUT signal during the active phase is defined by the inverted level of bit BRGH.MCLKCFG, evaluated at the start of the active phase. The polarity of the MCLKOUT signal during the passive phase is defined by bit BRGH.MCLKCFG, evaluated at the start of the passive phase. If bit BRGH.MCLKOUT is programmed with another value, the change is taken into account with the next change between the phases. This mechanism ensures that no shorter pulses than the length of a phase occur at the MCLKOUT output. In the example shown in Figure 19-13, the value of BRGH.MCLKCFG is changed from 0 to 1 during the passive phase of MCLK period 2. The generation of the MCLKOUT signal is enabled/disabled by the protocol preprocessor, based on bit PCRH.MCLK. After this bit has become set, signal MCLKOUT is generated with the next active phase of the MCLK period. If PCRH.MCLK = 0 (MCLKOUT generation disabled), the level for the passive phase is also applied for active phase. User's Manual USIC, UM_V0.2D5 19-47 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel MCLK period 1 MCLK period 2 MCLK period 3 MCLK period 4 MCLKOUT active phase passive phase active phase passive phase active phase passive phase active phase passive phase BRGH.MCLKCFG = 0 BRGH.MCLKCFG = 1 USIC_MCLKOUT_config Figure 19-13 Master Clock Output Configuration The shift clock output signal SCLKOUT available at the corresponding output pin can be configured in polarity and additionally, a delay of one period of fPDIV (= half SCLK period) can be introduced. The delay allows to adapt the order of the shift clock edges to the application requirements. If the delay is used, it has to be taken into account for the calculation of the signal propagation times and loop delays. The mechanism for the polarity control of the SCLKOUT signal is similar to the one for MCLKOUT, but based on bit field BRGH.SCLKCFG. The generation of the SCLKOUT signal is enabled/disabled by the protocol pre-processor. Depending on the selected protocol, the protocol pre-processor can control the generation of the SCLKOUT signal independently of the divider chain, e.g. for protocols without the need of a shift clock available at a pin, the SCLKOUT generation is disabled. User's Manual USIC, UM_V0.2D5 19-48 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.2.8 Baud Rate Generator Registers 19.2.8.1 Fractional Divider Registers The fractional divider registers FDRL and FDRH allow the generation of the internal frequency fFD, that is derived from the system clock fSYS. FDRL Fractional Divider Register L 15 DM rw 14 13 12 0 r 11 10 9 (04H) 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 STEP rw Field STEP Bits [9:0] Type Description rw Step Value In normal divider mode STEP contains the reload value for RESULT after RESULT has reached 3FFH. In fractional divider mode STEP defines the value added to RESULT with each input clock cycle. Divider Mode This bit fields defines the functionality of the fractional divider block. 00B The divider is switched off, fFD = 0. 01B Normal divider mode selected. 10B Fractional divider mode selected. 11B The divider is switched off, fFD = 0. Reserved read as 0; should be written with 0. DM [15:14] rw 0 [13:10] r User's Manual USIC, UM_V0.2D5 19-49 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary FDRH Fractional Divider Register H 15 0 rw 14 13 12 0 r 11 10 9 Universal Serial Interface Channel (06H) 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 RESULT rh Field RESULT Bits [9:0] Type Description rh Result Value In normal divider mode this bit field is updated with fSYS according to: RESULT = RESULT + 1 In fractional divider mode this bit field is updated with fSYS according to: RESULT = RESULT + STEP If bit field DM is written with 01B or 10B, RESULT is loaded with a start value of 3FFH. Reserved for Future Use Must be written with 0 to allow correct fractional divider operation. Reserved read as 0; should be written with 0. 0 [15:14] rw 0 [13:10] r User's Manual USIC, UM_V0.2D5 19-50 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.2.8.2 Baud Rate Generator Registers The protocol-related divider for baud rate generation is controlled by the registers BRGL and BRGH. BRGL Baud Rate Generator Register L 15 0 r 14 13 12 DCTQ rw 11 10 9 (1CH) 8 7 6 5 0 r 4 Reset Value: 0000H 3 2 0 r 1 0 PCTQ rw CTQSEL rw PPP TM EN EN rw rw CLKSEL rw Field CLKSEL Bits [1:0] Type Description rw Clock Selection This bit field defines the input frequency fPIN. 00B The fractional divider frequency fFD is selected. 01B reserved, no action 10B The trigger signal DX1T defines fPIN. Signal MCLK toggles with fPIN. 11B Signal MCLK corresponds to the DX1S signal and the frequency fPIN is derived from the rising edges of DX1S. Timing Measurement Enable This bit defines the functionality of the protocolrelated divider. 0B Divider mode: fPDIV = fPPP / (PDIV + 1) Data transfers are possible and the trigger signals DX0T and DX1T are ignored. 1B Capture mode: The 10-bit counter is incremented by 1 with fPPP and stops counting when reaching its maximum value. If one of the trigger signals DX0T or DX1T become active, the counter value is captured into bit field PDIV, the counter is cleared and a transmit shift event is generated. Data transfers are not possible. TMEN 3 rw User's Manual USIC, UM_V0.2D5 19-51 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field PPPEN Bits 4 Type Description rw Enable 2:1 Divider for fPPP This bit defines the input frequency fPPP. 0B The 2:1 divider for fPPP is disabled. fPPP = fPIN 1B The 2:1 divider for fPPP is enabled. fPPP = fMCLK = fPIN / 2. Input Selection for CTQ This bit defines the length of a time quantum for the protocol pre-processor. 00B fCTQIN = fPDIV 01B fCTQIN = fPPP 10B fCTQIN = fSCLK 11B fCTQIN = fMCLK Pre-Divider for Time Quanta Counter This bit field defines length of a time quantum tq for the time quanta counter in the protocol pre-processor. tq = (PCTQ + 1) / fCTQIN Denominator for Time Quanta Counter This bit field defines the number of time quanta tq taken into account by the time quanta counter in the protocol pre-processor. Reserved read as 0; should be written with 0. Universal Serial Interface Channel CTQSEL [7:6] rw PCTQ [9:8] rw DCTQ [14:10] rw 0 2, 5, 15 r User's Manual USIC, UM_V0.2D5 19-52 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel BRGH Baud Rate Generator Register H 15 14 13 12 11 0 r 10 9 (1EH) 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 M SCLKCFG CLK CFG rw rw PDIV rwh Field PDIV Bits [9:0] Type Description rwh Divider Mode: Divider Factor to Generate fPDIV This bit field defines the ratio between the input frequency fPPP and the divider frequency fPDIV. Capture Mode: Captured Time Interval The value of the counter is captured into this bit field if one of the trigger signals DX0T or DX1T are activated by the corresponding input stage. MCLKCFG 13 rw Master Clock Configuration This bit field defines the level of the passive phase of the MCLKOUT signal. 0B The passive level is 0. 1B The passive level is 1. Shift Clock Output Configuration This bit field defines the level of the passive phase of the SCLKOUT signal and enables/disables a delay of half of a SCLK period. 00B The passive level is 0 and the delay is disabled. 01B The passive level is 1 and the delay is disabled. 10B The passive level is 0 and the delay is enabled. 11B The passive level is 1 and the delay is enabled. Reserved read as 0; should be written with 0. SCLKCFG [15:14] rw 0 [12:10] r User's Manual USIC, UM_V0.2D5 19-53 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.2.9 Operating the Transmit Data Path The transmit data path is based on a 16-bit wide transmit shift register TSR and a transmit buffer TBUF. The data transfer parameters like data word length, data frame length, or the shift direction are controlled commonly for transmission and reception by the shift control registers. Register TCSRL mainly controls the transmit data handling, whereas register TCSRH monitors the transmit status. A change of the value of the data shift output signal DOUT only happens at the corresponding edge of the shift clock input signal. The level of the last data bit of a data word/frame is held constant at DOUT until the next data word begins with the next corresponding edge of the shift clock. 19.2.9.1 Transmit Buffering The transmit shift register TSR can not be directly accessed by SW, because it is automatically updated with the value stored in the transmit buffer TBUF if a currently transmitted data word is finished and new data is valid for transmission. Data words can be loaded directly into TBUF by writing to one of the transmit buffer input locations TBUFx (see Chapter 19.2.9.2) or, optionally, by a FIFO buffer stage (see Chapter 19.2.13). shift clock domain shift data output shift clock input shift control input TSR shift control & status status of TSR control of TSR 16 data TCSRH transmit control TCSRL TBUF system clock domain optional FIFO TBUFx USIC_DSU_transmit Figure 19-14 Transmit Data Path User's Manual USIC, UM_V0.2D5 19-54 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.2.9.2 Transmit Control Information The transmit control information TCI can be used as additional control parameter for data transfers. The TCI is derived from the address x of the written TBUFx transmit buffer input location. It can be used to dynamically change the data word length, the data frame length, or other protocol-specific functions (for more details about this topic, please refer to the corresponding protocol chapters). The way how the TCI is used in different applications can be programmed by bits WLEMD, FLEMD, SELMD, and WAMD in register TCSRL. Please note that not all possible settings lead to useful system behavior. * Word length control: If TCSRL.WLEMD = 1, bit field SCTRH.WLE is updated with TCI[3:0] if a transmit buffer input location TBUFx is written. This function can be used in all protocols to dynamically change the data word length between 1 and 16 data bits per data word. Additionally, bit TCSRL.EOF is updated with TCI[4]. This function can be used in SSC master mode to control the slave select generation to finish data frames. It is recommended to program TCSRL.FLEMD = TCSRL.SELMD = 0. Frame length control: If TCSRL.FLEMD = 1, bit field SCTRH.FLE[4:0] is updated with TCI[4:0] and SCTRH.FLE[5] becomes 0 if a transmit buffer input location TBUFx is written. This function can be used in all protocols to dynamically change the data frame length between 1 and 32 data bits per data frame. It is recommended to program TCSRL.SELMD = TCSRL.WLEMD = TCSRL.WAMD = 0. Select output control: If TCSRL.SELMD = 1, bit field PCR.CTR[20:16] is updated with TCI[4:0] and PCR.CTR[23:21] becomes 0 if a transmit buffer input location TBUFx is written. This function can be used in SSC master mode to define the targeted slave device(s). It is recommended to program TCSRL.WLEMD = TCSRL.FLEMD = TCSRL.WAMD = 0. Word address control: If TCSRL.WAMD = 1, bit TCSRL.WA is updated with TCI[4] if a transmit buffer input location TBUFx is written. This function can be used in IIS mode to define if the data word is transmitted on the right or the left channel. It is recommended to program TCSRL.SELMD = TCSRL.FLEMD = 0. * * * User's Manual USIC, UM_V0.2D5 19-55 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.2.9.3 Transmit Data Validation The data word in the transmit buffer TBUF can be tagged valid or invalid for transmission by bit TCSRL.TDV (transmit data valid). A combination of data flow related and event related criteria define whether the data word is considered valid for transmission. A data validation logic checks the start conditions for each data word. Depending on the result of the check, the transmit shift register is loaded with different values, according to the following rules: * If a USIC channel is the communication master (it defines the start of each data word transfer), a data word transfer can only be started with valid data in the transmit buffer TBUF. In this case, the transmit shift register is loaded with the content of TBUF, that is not changed due to this action. If a USIC channel is a communication slave (it can not define the start itself, but has to react), a data word transfer requested by the communication master has to be started independently of the status of the data word in TBUF. If a data word transfer is requested and started by the master, the transmit shift register is loaded at the first corresponding shift clock edge either with the data word in TBUF (if it is valid for transmission) or with the level defined by bit SCTRL.PDL (if the contents of TBUF has not been valid at the transmission start). In both cases, the contents of TBUF is not changed. * The control and status bits for the data validation are located in registers TCSRL or TCSRH. The data validation is based on the logic blocks shown in Figure 19-15. TDVTR transfer trigger TE TDV data shift unit DSU DX2T shift control input DX2 DX2S transfer gating TDEN TBUF data validation TDSSM USIC_TDV Figure 19-15 Transmit Data Validation * A transfer gating logic enables or disables the data word transfer from TBUF under SW or under HW control. If the input stage DX2 is not needed for data shifting, signal DX2S can be used for gating purposes. The transfer gating logic is controlled by bit field TCSRL.TDEN. User's Manual USIC, UM_V0.2D5 19-56 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary * Universal Serial Interface Channel * A transfer trigger logic supports data word transfers related to events, e.g. timer based or related to an input pin. If the input stage DX2 is not needed for data shifting, signal DX2T can be used for trigger purposes. The transfer trigger logic is controlled by bit TCSRL.TDVTR and the occurrence of a trigger event is indicated by bit TCSRH.TE. A data validation logic combining the inputs from the gating logic, the triggering logic and DSU signals. A transmission of the data word located in TBUF can only be started if the gating enables the start, bit TCSRL.TDV = 1, and bit TCSRH.TE = 1. The contents of the transmit buffer TBUF should not be overwritten with new data while it is valid for transmission and a new transmission can start. If the contents of TBUF has to be changed, it is recommended to clear bit TCSRL.TDV by writing FMR.MDTV = 10B before updating the data. Bit TCSRL.TDV becomes automatically set when TBUF is updated with new data. Another possibility are the interrupts TBI (for ASC and IIC) or RSI (for SSC and IIS) indicating that a transmission has started. While a transmission is in progress, TBUF can be loaded with new data. In this case the user has to take care that an update of the TBUF contents takes place before a new transmission starts. If bit TCSRL.TDSSM = 0, the contents of the transmit buffer TBUF is always considered as valid for transmission. The transfer trigger mechanism can be used to start the transfer of the same data word based on the selected event (e.g. on a timer base or an edge at a pin) to realize a kind of life-sign mechanism. Furthermore, in slave mode, it is ensured that always a correct data word is transmitted instead of the passive data level. Bit TCSRL.TDSSM = 1 has to be programmed to allow word-by-word data transmission with a kind of single-shot mechanism. After each transmission start, a new data word has to be loaded into the transmit buffer TBUF, either by SW write actions to one of the transmit buffer input locations TBUFx or by an optional data buffer (e.g. FIFO buffer). To avoid that data words are sent out several times or to allow data handling with an additional data buffer (e.g. FIFO), bit TCSRL.TDSSM has to be 1. Bit TCSRL.TDV becoming automatically set when a new data word is loaded into the transmit buffer TBUF, a transmission start can be requested by a write action of the data to be transmitted to at least the low byte of one of the transmit buffer input locations TBUFx. The additional information TCI can be used to control the data word length or other parameters independently for each data word by a single write access. Bit field FMR.MTDV allows SW driven modification (set or clear) of bit TCSRL.TDV. Together with the gating control bit field TCSRL.TDEN, the user can set up the transmit data word without starting the transmission. A possible program sequence could be: clear TCSRL.TDEN = 00B, write data to TBUFx, clear TCSRL.TDV by With this structure, the following data transfer functionality can be achieved: * * * * User's Manual USIC, UM_V0.2D5 19-57 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel writing FMR.MDTV = 10B, re-enable the gating with TCSRL.TDEN = 01B and then set TCSRL.TDV under SW control by writing FMR.MTDV = 01B. 19.2.10 Operating the Receive Data Path The receive data path is based on two 16-bit wide receive shift registers RSR0 and RSR1 and a receive buffer for each of them (RBUF0 and RBUF1). The data transfer parameters like data word length, data frame length, or the shift direction are controlled commonly for transmission and reception by the shift control registers. Register RBUF01SRL monitors the status of RBUF0 and register RBUF01SRH of RBUF1. 19.2.10.1 Receive Buffering The receive shift registers can not be directly accessed by SW, but their contents are automatically loaded into the receive buffer registers RBUF0 (or RBUF1 respectively) if a complete data word has been received or the frame is finished. The received data words in RBUF0 or RBUF1 can be read out in the correct order directly from register RBUF or, optionally, from a FIFO buffer stage (see Chapter 19.2.13). shift clock domain shift data input shift clock input shift control input RSR1 RSR0 shift control & status status of RSR0 status of RSR1 16 data 16 data RBUF01 SRL receiver control RBUF01 SRH RBUF0 RBUF1 system clock domain RBUF SR RBUF USIC_DSU_receive Figure 19-16 Receive Data Path User's Manual USIC, UM_V0.2D5 19-58 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.2.10.2 Baud Rate Constraints The following baud rate constraints have to be respected to ensure correct data reception and buffering. The user has to take care about these restrictions when selecting the baud rate and the data word length with respect to the module clock frequency fSYS. * A received data word in a receiver shift register RSRx must be held constant for at least 4 periods of fSYS in order to ensure correct loading of the related receiver buffer register RBUFx. The shift control signal has to be constant inactive for at least 5 periods of fSYS between two consecutive frames in order to correctly detect the end of a frame. The shift control signal has to be constant active for at least 1 period of fSYS in order to correctly detect a frame (shortest frame). A minimum setup and hold time of the shift control signal with respect to the shift clock signal of 10ns has to be ensured. * * * User's Manual USIC, UM_V0.2D5 19-59 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.2.11 Transfer Control and Status Registers 19.2.11.1 Shift Control Registers The data shift unit is controlled by the following registers. The values in these registers are applied for data transmission and reception. Please note that the shift control settings SDIR, WLE, and FLE are shared between transmitter and receiver. They are internally "frozen" for a each data word transfer in the transmitter with the first transmit shift clock edge and with the first receive shift clock edge in the receiver. The SW has to take care that updates of these bit fields by SW are done coherently (e.g. refer to the receiver start event indication PSR.RSIF). SCTRL Shift Control Register L 15 14 13 0 r 12 11 10 9 (30H) 8 7 6 5 4 0 r Reset Value: 0000H 3 2 1 PDL rw 0 S DIR rw TRM rw DOCFG rw Field SDIR Bits 0 Type Description rw Shift Direction This bit defines the shift direction of the data words for transmission and reception. Shift LSB first. The first data bit of a data word 0B is located at bit position 0. 1B Shift MSB first. The first data bit of a data word is located at the bit position given by bit field SCTRH.WLE. Passive Data Level This bit defines the output level at the shift data output signal when no data is available for transmission. The PDL level is output with the first relevant transmit shift clock edge of a data word. 0B The passive data level is 0. 1B The passive data level is 1. Data Output Configuration This bit defines the relation between the internal shift data value and the data output signal DOUT. X0B DOUT = shift data value X1B DOUT = inverted shift data value 19-60 V1.0, 2007-06 PDL 1 rw DOCFG [7:6] rw User's Manual USIC, UM_V0.2D5 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field TRM Bits [9:8] Type Description rw Transmission Mode This bit field describes how the shift control signal is interpreted by the DSU. Data transfers are only possible while the shift control signal is active. 00B The shift control signal is considered as inactive and data frame transfers are not possible. 01B The shift control signal is considered active if it is at 1-level. This is the setting to be programmed to allow data transfers. 10B The shift control signal is considered active if it is at 0-level. It is recommended to avoid this setting and to use the inversion in the DX2 stage in case of a low-active signal. 11B The shift control signal is considered active without referring to the actual signal level. Data frame transfer is possible after each edge of the signal. Reserved read as 0; should be written with 0. Universal Serial Interface Channel 0 [5:2], [15:10] r User's Manual USIC, UM_V0.2D5 19-61 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel SCTRH Shift Control Register H 15 14 0 r 13 12 11 10 9 (32H) 8 7 0 r 6 5 4 Reset Value: 0000H 3 FLE rwh 2 1 0 WLE rwh Field FLE Bits [5:0] Type Description rwh Frame Length This bit field defines how many bits are transferred within a data frame. A data frame can consist of several concatenated data words. If TCSRL.FLEMD = 1, the value can be updated automatically by the data handler. Word Length This bit field defines the data word length (amount of bits that are transferred in each data word) for reception and transmission. The data word is always right-aligned in the data buffer at the bit positions [WLE down to 0]. If TCSRL.WLEMD = 1, the value can be updated automatically by the data handler. 00H The data word contains 1 data bit located at bit position 0. 01H The data word contains 2 data bits located at bit positions [1:0]. ... 0FH The data word contains 16 data bits located at bit positions [15:0]. Reserved read as 0; should be written with 0. WLE [11:8] rwh 0 [7:6], [15:12] r User's Manual USIC, UM_V0.2D5 19-62 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.2.11.2 Transmission Control and Status Registers The data transmission is controlled by register TCSRL. TCSRL Transmit Control/Status Register L 15 0 r 14 13 WA rwh 12 TD VTR rw 11 10 9 0 r (3CH) 8 7 6 5 4 0 r Reset Value: 0000H 3 2 1 0 TDEN rw TD TDV EOF SOF SSM rw rh rwh rwh WA FLE SEL WLE MD MD MD MD rw rw rw rw Field WLEMD Bits 0 Type Description rw WLE Mode This bit enables the data handler to automatically update the bit field SCTRH.WLE by the transmit control information TCI[3:0] and bit TCSR.EOF by TCI[4] (see Section 19.2.9.2). If enabled, an automatic update takes place when new data is loaded to register TBUF, either by writing to one of the transmit buffer input locations TBUFx or by an optional data buffer. The automatic update of SCTRH.WLE and 0B TCSR.EOF is disabled. 1B The automatic update of SCTR.WLE and TCSR.EOF is enabled. Select Mode This bit can be used mainly for the SSC protocol. It enables the data handler to automatically update bit field PCRH.CTR[20:16] by the transmit control information TCI[4:0] and clear bit field PCRH.CTR[23:21] (see Section 19.2.9.2). If enabled, an automatic update takes place when new data is loaded to register TBUF, either by writing to one of the transmit buffer input locations TBUFx or by an optional data buffer. The automatic update of PCRH.CTR[23:16] is 0B disabled. 1B The automatic update of PCRH.CTR[23:16] is disabled. SELMD 1 rw User's Manual USIC, UM_V0.2D5 19-63 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field FLEMD Bits 2 Type Description rw FLE Mode This bit enables the data handler to automatically update bits SCTRH.FLE[4:0] by the transmit control information TCI[4:0] and to clear bit SCTRH.FLE[5] (see Section 19.2.9.2). If enabled, an automatic update takes place when new data is loaded to register TBUF, either by writing to one of the transmit buffer input locations TBUFx or by an optional data buffer. 0B The automatic update of FLE is disabled. The automatic update of FLE is enabled. 1B WA Mode This bit can be used mainly for the IIS protocol. It enables the data handler to automatically update bit TCSRL.WA by the transmit control information TCI[4] (see Section 19.2.9.2). If enabled, an automatic update takes place when new data is loaded to register TBUF, either by writing to one of the transmit buffer input locations TBUFx or by an optional data buffer. 0B The automatic update of bit WA is disabled. 1B The automatic update of bit WA is enabled. Start Of Frame This bit is only taken into account for the SSC protocol, otherwise it is ignored. It indicates that the data word in TBUF is considered as the first word of a new SSC frame if it is valid for transmission (TCSRL.TDV = 1). This bit becomes cleared when the TBUF data word is transferred to the transmit shift register. The data word in TBUF is not considered as 0B first word of a frame. The data word in TBUF is considered as first 1B word of a frame. A currently running frame is finished and MSLS becomes deactivated (respecting the programmed delays). Universal Serial Interface Channel WAMD 3 rw SOF 5 rw User's Manual USIC, UM_V0.2D5 19-64 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field EOF Bits 6 Type Description rwh End Of Frame This bit is only taken into account for the SSC protocol, otherwise it is ignored. It can be modified automatically by the data handler if bit WLEMD = 1. It indicates that the data word in TBUF is considered as the last word of an SSC frame. If it is the last word, the MSLS signal becomes inactive after the transfer, respecting the programmed delays. This bit becomes cleared when the TBUF data word is transferred to the transmit shift register. The data word in TBUF is not considered as 0B last word of an SSC frame. 1B The data word in TBUF is considered as last word of an SSC frame. Transmit Data Valid This bit indicates that the data word in the transmit buffer TBUF can be considered as valid for transmission. The TBUF data word can only be sent out if TDV = 1. It is automatically set when data is moved to TBUF (by writing to one of the transmit buffer input locations TBUFx, or optionally, by the bypass or FIFO mechanism). The data word in TBUF is not valid for 0B transmission. 1B The data word in TBUF is valid for transmission and a transmission start is possible. New data should not be written to a TBUFx input location while TDV = 1. Universal Serial Interface Channel TDV 7 rh User's Manual USIC, UM_V0.2D5 19-65 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field TDSSM Bits 8 Type Description rw TBUF Data Single Shot Mode This bit defines if the data word TBUF data is considered as permanently valid or if the data should only be transferred once. 0B The data word in TBUF is not considered as invalid after it has been loaded into the transmit shift register. The loading of the TBUF data into the shift register does not clear TDV. 1B The data word in TBUF is considered as invalid after it has been loaded into the shift register. In ASC and IIC mode, TDV is cleared with the TBI event, whereas in SSC and IIS mode, it is cleared with the RSI event. TDSSM = 1 has to be programmed if an optional data buffer is used. TBUF Data Enable This bit field controls the gating of the transmission start of the data word in the transmit buffer TBUF. 00B A transmission start of the data word in TBUF is disabled. If a transmission is started, the passive data level is sent out. 01B A transmission of the data word in TBUF can be started if TDV = 1. 10B A transmission of the data word in TBUF can be started if TDV = 1 while DX2S = 0. 11B A transmission of the data word in TBUF can be started if TDV = 1 while DX2S = 1. TBUF Data Valid Trigger This bit enables the transfer trigger unit to set bit TCSRH.TE if the trigger signal DX2T becomes active for event driven transfer starts, e.g. timer-based or depending on an event at an input pin. Bit TDVTR has to be 0 for protocols where the input stage DX2 is used for data shifting. 0B Bit TCSRH.TE is permanently set. 1B Bit TCSRH.TE is set if DX2T becomes active while TDV = 1. Universal Serial Interface Channel TDEN [11:10] rw TDVTR 12 rw User's Manual USIC, UM_V0.2D5 19-66 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field WA Bits 13 Type Description rwh Word Address This bit is only taken into account for the IIS protocol, otherwise it is ignored. It can be modified automatically by the data handler if bit WAMD = 1. Bit WA defines for which channel the data stored in TBUF will be transmitted. The data word in TBUF will be transmitted after 0B a falling edge of WA has been detected (referring to PSR.WA). 1B The data word in TBUF will be transmitted after a rising edge of WA has been detected (referring to PSR.WA). Reserved read as 0; should be written with 0. Universal Serial Interface Channel 0 4, 9, [15:14] r User's Manual USIC, UM_V0.2D5 19-67 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel The data transmission status is monitored by register TCSRH. TCSRH Transmit Control/Status Register H 15 14 0 r 13 12 TE rh 11 TVC rh 10 TV rh 9 0 r (3EH) 8 T SOF rh 7 6 5 4 0 r Reset Value: 0000H 3 2 1 0 Field TSOF Bits 8 Type Description rh Transmitted Start Of Frame This bit indicates if the latest start of a data word transmission has taken place for the first data word of a new data frame. This bit is updated with the transmission start of each data word. 0B The latest data word transmission has not been started for the first word of a data frame. 1B The latest data word transmission has been started for the first word of a data frame. Transmission Valid This bit represents the transmit buffer underflow and indicates if the latest start of a data word transmission has taken place with a valid data word from the transmit buffer TBUF. This bit is updated with the transmission start of each data word. The latest start of a data word transmission has 0B taken place while no valid data was available. As a result, the transmission of a data words with passive level (SCTRL.PDL) has been started. 1B The latest start of a data word transmission has taken place with valid data from TBUF. Transmission Valid Cumulated This bit cumulates the transmit buffer underflow indication TV. It is cleared automatically together with bit TV and has to be set by writing FMRL.ATVC = 1. 0B Since TVC has been set, at least one data buffer underflow condition has occurred. 1B Since TVC has been set, no data buffer underflow condition has occurred. 19-68 V1.0, 2007-06 TV 10 rh TVC 11 rh User's Manual USIC, UM_V0.2D5 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field TE Bits 12 Type Description rh Trigger Event If the transfer trigger mechanism is enabled, this bit indicates that a trigger event has been detected (DX2T = 1) while TCSRL.TDV = 1. If the event trigger mechanism is disabled, the bit TE is permanently set. It is cleared by writing FMRL.MTDV = 10B or when the data word located in TBUF is loaded into the shift register. 0B The trigger event has not yet been detected. A transmission of the data word in TBUF can not be started. 1B The trigger event has been detected (or the trigger mechanism is switched off) and a transmission of the data word in TBUF can not be started. Reserved read as 0; should be written with 0. Universal Serial Interface Channel 0 [7:0], 9, [15:13] r User's Manual USIC, UM_V0.2D5 19-69 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.2.11.3 Flag Modification Registers The flag modification registers FMRL, FMRH allow the modification of control and status flags related to data handling by using only write accesses. Read accesses to FMRL, FMRH always deliver 0 at all bit positions. Additionally, the service request outputs of this USIC channel can be activated by SW (the activation is triggered by the write access and is deactivated automatically). FMRL Flag Modification Register L 15 14 13 12 11 10 9 0 r (38H) 8 7 6 5 4 A TVC w Reset Value: 0000H 3 0 r 2 1 0 C C RDV RDV 0 1 w w MTDV w Field MTDV Bits [1:0] Type Description w Modify Transmit Data Valid Writing to this bit field can modify bits TCSRL.TDV and TCSRH.TE to control the start of a data word transmission by SW. 00B No action. 01B Bit TDV is set, TE is unchanged. 10B Bits TDV and TE are cleared. 11B reserved Activate Bit TVC Writing to this bit can set bit TCSRH.TVC to start a new cumulation of the transmit buffer underflow condition. No action. 0B 1B Bit TCSRH.TVC is set. Clear Bits RDV for RBUF0 Writing 1 to this bit clears bits RBUF01SRL.RDV00 and RBUF01SRH.RDV10 to declare the received data in RBUF0 as no longer valid (to emulate a read action). 0B No action. 1B Bits RBUF01SRL.RDV00 and RBUF01SRH.RDV10 are cleared. ATVC 4 w CRDV0 14 w User's Manual USIC, UM_V0.2D5 19-70 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field CRDV1 Bits 15 Type Description w Clear Bit RDV for RBUF1 Writing 1 to this bit clears bits RBUF01SRL.RDV01 and RBUF01SRH.RDV11 to declare the received data in RBUF1 as no longer valid (to emulate a read action). No action. 0B 1B Bits RBUF01SRL.RDV01 and RBUF01SRH.RDV11 are cleared. Reserved read as 0; should be written with 0. Universal Serial Interface Channel 0 [3:2], [13:5] r FMRH Flag Modification Register H 15 14 13 12 11 10 0 r 9 (3AH) 8 7 6 5 4 Reset Value: 0000H 3 SI O3 w 2 SI O2 w 1 SI O1 w 0 SI O0 w Field SIO0, SIO1, SIO2, SIO3 Bits 0, 1, 2, 3 Type Description w Set Interrupt Output SRx Writing a 1 to this bit field activates the service request output SRx of this USIC channel. It has no impact on service request outputs of other USIC channels. 0B No action. 1B The service request output SRx is activated. Reserved returns 0 if read; should be written with 0; 0 [15:4] r User's Manual USIC, UM_V0.2D5 19-71 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.2.12 Data Buffer Registers 19.2.12.1 Transmit Buffer Locations The 32 independent data input locations TBUF00 to TBUF31 are address locations that can be used as data entry locations for the transmit buffer. Data written to one of these locations will appear in a common register TBUF. Additionally, the 5 bit coding of the number [31:0] of the addressed data input location represents the transmit control information TCI (please refer to the protocol sections for more details). The internal transmit buffer register TBUF contains the data that will be loaded to the transmit shift register for the next transmission of a data word. It can be read out at all TBUF00 to TBUF31 addresses. TBUFx (x = 00-31) Transmit Buffer Input Location x 15 14 13 12 11 10 9 (80H + x*4) 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 TDATA rwh Field TDATA Bits [15:0] Type Description rwh Transmit Data This bit field contains the data to be transmitted (read view). A data write action to at least the low byte of TDATA sets TCSRL.TDV. User's Manual USIC, UM_V0.2D5 19-72 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.2.12.2 Receive Buffer Registers RBUF0, RBUF1 The receive buffer register RBUF0 contains the data received from RSR0. A read action does not change the status of the receive data from "not yet read = valid" to "already read = not valid". RBUF0 Receiver Buffer Register 0 15 14 13 12 11 10 9 (50H) 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 DSR0 rh Field DSR0 Bits [15:0] Type Description rh Data of Shift Register 0 The receive buffer status register RBUF01SRL provides the status of the data in receive buffer RBUF0. RBUF01SRL Receiver Buffer 01 Status Register L (60H) 15 14 13 12 11 0 r 10 9 8 7 0 r 6 SOF 0 rh 5 0 r 4 P PAR ERR 0 0 rh rh Reset Value: 0000H 3 2 1 0 DS RDV RDV 0 01 00 rh rh rh WLEN0 rh Field WLEN0 Bits [3:0] Type Description rh Received Data Word Length in RBUF0 This bit field indicates how many bits have been received within the last data word stored in RBUF0. This number indicates how many data bits have to be considered as receive data, whereas the other bits in RBUF0 have been cleared automatically. The received bits are always right-aligned. 00H One bit has been received. ... 0FH Sixteen bits have been received. User's Manual USIC, UM_V0.2D5 19-73 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field SOF0 Bits 6 Type Description rh Start of Frame in RBUF0 This bit indicates whether the data word in RBUF0 has been the first data word of a data frame. 0B The data in RBUF0 has not been the first data word of a data frame. 1B The data in RBUF0 has been the first data word of a data frame. Protocol-Related Argument in RBUF0 This bit indicates the value of the protocol-related argument. This value is elaborated depending on the selected protocol and adds additional information to the data word in RBUF0. The meaning of this bit is described in the corresponding protocol chapter. Protocol-related Error in RBUF0 This bit indicates if the value of the protocol-related argument meets an expected value. This value is elaborated depending on the selected protocol and adds additional information to the data word in RBUF0. The meaning of this bit is described in the corresponding protocol chapter. 0B The received protocol-related argument PAR matches the expected value. The reception of the data word sets bit PSR.RIF and can generate a receive interrupt. 1B The received protocol-related argument PAR does not match the expected value. The reception of the data word sets bit PSR.AIF and can generate an alternative receive interrupt. Universal Serial Interface Channel PAR0 8 rh PERR0 9 rh User's Manual USIC, UM_V0.2D5 19-74 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field RDV00 Bits 13 Type Description rh Receive Data Valid in RBUF0 This bit indicates the status of the data content of register RBUF0. This bit is identical to bit RBUF01SRH.RDV10 and allows consisting reading of information for the receive buffer registers. It is set when a new data word is stored in RBUF0 and automatically cleared if it is read out via RBUF. 0B Register RBUF0 does not contain data that has not yet been read out. 1B Register RBUF0 contains data that has not yet been read out. Receive Data Valid in RBUF1 This bit indicates the status of the data content of register RBUF1. This bit is identical to bit RBUF01SRH.RDV11 and allows consisting reading of information for the receive buffer registers. It is set when a new data word is stored in RBUF1 and automatically cleared if it is read out via RBUF. 0B Register RBUF1 does not contain data that has not yet been read out. 1B Register RBUF1 contains data that has not yet been read out. Data Source This bit indicates which receive buffer register (RBUF0 or RBUF1) is currently visible in registers RBUF(D) and in RBUFSR for the associated status information. It indicates which buffer contains the oldest data (the data that has been received first). This bit is identical to bit RBUF01SRH.DS1 and allows consisting reading of information for the receive buffer registers. 0B The register RBUF contains the data of RBUF0 (same for associated status information). 1B The register RBUF contains the data of RBUF1 (same for associated status information). Reserved read as 0; should be written with 0. Universal Serial Interface Channel RDV01 14 rh DS0 15 rh 0 [5:4], 7, [12:10] r User's Manual USIC, UM_V0.2D5 19-75 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel The receive buffer register RBUF1 contains the data received from RSR1. A read action does not change the status of the receive data from "not yet read = valid" to "already read = not valid". RBUF1 Receiver Buffer Register 1 15 14 13 12 11 10 9 (54H) 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 DSR1 rh Field DSR1 Bits [15:0] Type Description rh Data of Shift Register 1 The receive buffer status register RBUF01SRH provides the status of the data in receive buffer RBUF1. RBUF01SRH Receiver Buffer 01 Status Register H (62H) 15 14 13 12 11 0 r 10 9 8 7 0 r 6 SOF 1 rh 5 0 r 4 P PAR ERR 1 1 rh rh Reset Value: 0000H 3 2 1 0 DS RDV RDV 1 11 10 rh rh rh WLEN1 rh Field WLEN1 Bits [3:0] Type Description rh Received Data Word Length in RBUF1 This bit field indicates how many bits have been received within the last data word stored in RBUF1. This number indicates how many data bits have to be considered as receive data, whereas the other bits in RBUF1 have been cleared automatically. The received bits are always right-aligned. 00H One bit has been received. ... 0FH Sixteen bits have been received. User's Manual USIC, UM_V0.2D5 19-76 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field SOF1 Bits 6 Type Description rh Start of Frame in RBUF1 This bit indicates whether the data word in RBUF1 has been the first data word of a data frame. 0B The data in RBUF1 has not been the first data word of a data frame. 1B The data in RBUF1 has been the first data word of a data frame. Protocol-Related Argument in RBUF1 This bit indicates the value of the protocol-related argument. This value is elaborated depending on the selected protocol and adds additional information to the data word in RBUF1. The meaning of this bit is described in the corresponding protocol chapter. Protocol-related Error in RBUF1 This bit indicates if the value of the protocol-related argument meets an expected value. This value is elaborated depending on the selected protocol and adds additional information to the data word in RBUF1. The meaning of this bit is described in the corresponding protocol chapter. 0B The received protocol-related argument PAR matches the expected value. The reception of the data word sets bit PSR.RIF and can generate a receive interrupt. 1B The received protocol-related argument PAR does not match the expected value. The reception of the data word sets bit PSR.AIF and can generate an alternative receive interrupt. Receive Data Valid in RBUF0 This bit indicates the status of the data content of register RBUF0. This bit is identical to bit RBUF01SRL.RDV00 and allows consisting reading of information for the receive buffer registers. 0B Register RBUF0 does not contain data that has not yet been read out. 1B Register RBUF0 contains data that has not yet been read out. Universal Serial Interface Channel PAR1 8 rh PERR1 9 rh RDV10 13 rh User's Manual USIC, UM_V0.2D5 19-77 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field RDV11 Bits 14 Type Description rh Receive Data Valid in RBUF1 This bit indicates the status of the data content of register RBUF1. This bit is identical to bit RBUF01SRL.RDV01 and allows consisting reading of information for the receive buffer registers. Register RBUF1 does not contain data that has 0B not yet been read out. 1B Register RBUF1 contains data that has not yet been read out. Data Source This bit indicates which receive buffer register (RBUF0 or RBUF1) is currently visible in registers RBUF(D) and in RBUFSR for the associated status information. It indicates which buffer contains the oldest data (the data that has been received first). This bit is identical to bit RBUF01SRL.DS0 and allows consisting reading of information for the receive buffer registers. The register RBUF contains the data of RBUF0 0B (same for associated status information). 1B The register RBUF contains the data of RBUF1 (same for associated status information). Reserved read as 0; should be written with 0. Universal Serial Interface Channel DS1 15 rh 0 [5:4], 7, [12:10] r User's Manual USIC, UM_V0.2D5 19-78 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.2.12.3 Receive Buffer Registers RBUF, RBUFD The receiver buffer register RBUF shows the contents of the either RBUF0 or RBUF1, depending on the order of reception. Always the oldest data (the data word that has been received first) from both receive buffers can be read from RBUF. It is recommended to read out the received data from RBUF instead of RBUF0/1. With a read access of at least the low byte of RBUF, the status of the receive data is automatically changed from "not yet read = valid" to "already read = not valid", the content of RBUF becomes updated, and the next received data word becomes visible in RBUF. RBUF Receiver Buffer Register 15 14 13 12 11 10 9 (5CH) 8 DSR rh 7 6 5 4 Reset Value: 0000H 3 2 1 0 Field DSR Bits [15:0] Type Description rh Received Data This bit field monitors the content of either RBUF0 or RBUF1, depending on the reception sequence. If a debugger should be used to monitor the received data, the automatic update mechanism has to be de-activated to guaranty data consistency. Therefore, the receiver buffer register for debugging RBUFD is available. It is similar to RBUF, but without the automatic update mechanism by a read action. So a debugger (or other monitoring function) can read RBUFD without disturbing the receive sequence. RBUFD Receiver Buffer Reg. for Debugger 15 14 13 12 11 10 9 (4CH) 8 DSR rh 7 6 5 4 Reset Value: 0000H 3 2 1 0 User's Manual USIC, UM_V0.2D5 19-79 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel Field DSR Bits [15:0] Type Description rh Data from Shift Register Same as RBUF.DSR, but without releasing the buffer after a read action. The receive buffer status register RBUFSR provides the status of the data in receive buffers RBUF and RBUFD. If bits RBUF01SRL.DS0 (or RBUF01SRH.DS1) are 0, the content of RBUF01SRL is monitored in RBUFSR, otherwise the content of RBUF01SRH is shown. RBUFSR Receiver Buffer Status Register 15 DS rh 14 13 12 11 0 r 10 9 (58H) 8 7 0 r 6 SOF rh 5 0 r 4 Reset Value: 0000H 3 2 1 0 RDV RDV 1 0 rh rh P PAR ERR rh rh WLEN rh Field WLEN Bits [3:0] Type Description rh Received Data Word Length in RBUF or RBUFD Description see RBUF01SRL.WLEN0 or RBUF01SRH.WLEN1. Start of Frame in RBUF or RBUFD Description see RBUF01SRL.SOF0 or RBUF01SRH.SOF1. Protocol-Related Argument in RBUF or RBUFD Description see RBUF01SRL.PAR0 or RBUF01SRH.PAR1. Protocol-related Error in RBUF or RBUFD Description see RBUF01SRL.PERR0 or RBUF01SRH.PERR1. Receive Data Valid in RBUF or RBUFD Description see RBUF01SRL.RDV00 or RBUF01SRH.RDV10. Receive Data Valid in RBUF or RBUFD Description see RBUF01SRL.RDV01 or RBUF01SRH.RDV11. SOF 6 rh PAR 8 rh PERR 9 rh RDV0 13 rh RDV1 14 rh User's Manual USIC, UM_V0.2D5 19-80 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field DS Bits 15 Type Description rh Data Source of RBUF or RBUFD Description see RBUF01SRL.DS0 or RBUF01SRH.DS1. Reserved read as 0; should be written with 0. Universal Serial Interface Channel 0 [5:4], 7, [12:10] r User's Manual USIC, UM_V0.2D5 19-81 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.2.13 Operating the FIFO Data Buffer The FIFO data buffers of a USIC module are built in a similar way, with transmit buffer and receive buffer capability for each channel. Depending on the device, the amount of available FIFO buffer area can vary. In the XC2000, totally 64 buffer entries can be distributed among the transmit or receive FIFO buffers of both channels of the USIC module. buffered receive data receive FIFO transmit FIFO bypass receive data transmit data buffered transmit data data shift unit CH0 shift data in OU T R IN x OU T R IN x RBU F TBU F shift data out Figure 19-17 FIFO Buffer Overview In order to operate the FIFO data buffers, the following issues have to be considered: * FIFO buffer available and selected: The transmit FIFO buffer and the bypass structure are only available if CCFG.TB = 1, whereas the receive FIFO buffer is only available if CCFG.RB = 1. It is recommended to configure all buffer parameters while there is no data traffic for this USIC channel and the FIFO mechanism is disabled by TBCTRH.SIZE = 0 (for transmit buffer) or RBCTRH.SIZE = 0 (for receive buffer). The allocation of a buffer area by writing TBCTRL or RBCTRL has to be done while the corresponding FIFO buffer is disabled. The FIFO buffer interrupt control bits can be modified independently of data traffic. FIFO buffer setup: The total amount of available FIFO buffer entries limits the length of the transmit and 19-82 V1.0, 2007-06 user interface buffered receive data receive FIFO transmit FIFO bypass receive data transmit data buffered transmit data data shift unit CH1 shift data in RBU F TBU F shift data out USIC_FIFO_bidirect * User's Manual USIC, UM_V0.2D5 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel * receive buffers for each USIC channel. The configuration of the size of each FIFO buffer and their locations in the available buffer range is described in Section 19.2.13.1. Bypass setup: In addition to the transmit FIFO buffer, a bypass can be configured as described in Section 19.2.13.3. 19.2.13.1 FIFO Buffer Partitioning If available, the FIFO buffer area consists of a defined number of FIFO buffer entries, each containing a data part and the associated control information (RCI for receive data, TCI for transmit data). One FIFO buffer entry represents the finest granularity that can be allocated to a receive FIFO buffer or a transmit FIFO buffer. All available FIFO buffer entries of a USIC module are located one after the other in the FIFO buffer area. The overall counting starts with FIFO entry 0, followed by 1, 2, etc. For each USIC module, a certain number of FIFO entries is available, that can be allocated to the channels of the same USIC module. It is not possible to assign FIFO buffer area to USIC channels that are not located within the same USIC module. For each USIC channel, the size of the transmit and the receive FIFO buffer can be chosen independently. For example, it is possible to allocate the full amount of available FIFO entries as transmit buffer for one USIC channel. Some possible scenarios of FIFO buffer partitioning are shown in Figure 19-18. Each FIFO buffer consists of a set of consecutive FIFO entries. The size of a FIFO data buffer can only be programmed as a power of 2, starting with 2 entries, then 4 entries, then 8 entries, etc. A FIFO data buffer can only start at a FIFO entry aligned to its size. For example, a FIFO buffer containing n entries can only start with FIFO entry 0, n, 2*n, 3*n, etc. and consists of the FIFO entries [x*n, (x+1)*n-1], with x being an integer number (incl. 0). It is not possible to have "holes" with unused FIFO entries within a FIFO buffer, whereas there can be unused FIFO entries between two FIFO buffers. User's Manual USIC, UM_V0.2D5 19-83 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel available buffer area transmit data area for CH1 receive data area for CH1 transmit data area for CH0 receive data area for CH0 available buffer area transmit data area for CH1 unused entries available buffer area transmit data area for CH0 available buffer area transmit data area for CH1 receive data area for CH0 receive data area for CH0 transmit data area for CH0 scenario 1 scenario 2 scenario 3 scenario 4 USIC_FIFO_part Figure 19-18 FIFO Buffer Partitioning The data storage inside the FIFO buffers is based on pointers, that are internally updated whenever the data contents of the FIFO buffers have been modified. This happens automatically when new data is put into a FIFO buffer or the oldest data is taken from a FIFO buffer. As a consequence, the user program does not need to modify the pointers for data handling. Only during the initialization phase, the start entry of a FIFO buffer has to be defined by writing the number of the first FIFO buffer entry in the FIFO buffer to the corresponding bit field DPTR in register RBCTRL (for a receive FIFO buffer) or TBCTRL (for a transmit FIFO buffer) while the related bit field RBCTRH.SIZE=0 (or TBCTRH.SIZE = 0, respectively). The assignment of buffer entries to a FIFO buffer (regarding to size and pointers) must not be changed by SW while the related USIC channel is taking part in data traffic. 19.2.13.2 Data Buffer Events and Interrupts The transmit FIFO buffer mechanism detects the following events, that can lead to interrupts (if enabled). * Standard transmit buffer event: The filling level of the transmit buffer (given by TRBSRH.TBFLVL) exceeds (TBCTRH.LOF = 1) or falls below (TBCTRH.LOF = 0) a programmed limit (TBCTRL.LIMIT). The trigger of this event is the transition from equal to below or bigger, not the fact of being below or above. If the standard transmit buffer event is used to indicate that new data has to be written to one of the INx locations, TBCTRH.LOF = 0 should be programmed. Transmit buffer error event: The SW has written to a full buffer. The written value is ignored. * User's Manual USIC, UM_V0.2D5 19-84 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary clear Universal Serial Interface Channel CSTBI LOF transfer data to TBUF write data to INx CTBERI write to full transmit buffer STBI set standard transmit buffer event STBIEN AND STBINP to INT_O0 to INT_O3 ... standard transmit buffer interrupt 0 AND 1 LIMIT equals TBFLVL clear TBERI set transmit buffer error event TBERIEN AND ATBINP to INT_O0 to INT_O3 USIC_TB_ints transmit buffer error interrupt ... Figure 19-19 Transmit Buffer Events The receive FIFO buffer mechanism detects the following events, that can lead to an interrupt (if enabled). The standard receive buffer event and the alternative receive buffer event can be programmed to two different modes, one referring to the filling level of the receive buffer, the other one related to a bit position in the receive control information RCI of the data word that becomes available in OUTRL. If the interrupt generation refers to the filling level of the receive FIFO buffer, only the standard receive buffer event is used, whereas the alternative receive buffer event is not used. This mode can be selected to indicate that a certain amount of data has been received, without regarding the contents of the associated RCI. If the interrupt generation refers to RCI, the filling level is not taken into account. Each time a new data word becomes available in OUTRL, an event is detected. If bit RCI[4] = 0, a standard receive buffer event is signaled, otherwise an alternative receive buffer device (RCI[4] = 1). Depending on the selected protocol and the setting of RBCTRH.RCIM, the value of RCI[4] can hold different information that can be used for protocol-specific interrupt handling (see protocol sections for more details). * Standard receive buffer event in filling level mode (RBCTRH.RNM = 0): The filling level of the receive buffer (given by TRBSRH.RBFLVL) exceeds (RBCTRH.LOF = 1) or falls below (RBCTRH.LOF = 0) a programmed limit (RBCTRL.LIMIT). The trigger of this event is the transition from equal to below or greater, not the fact of being below or above. If the standard receive buffer event is used to indicate that new data has to be read from OUTRL, RBCTRH.LOF = 1 should be programmed. Standard receive buffer event in RCI mode (RBCTRH.RNM = 1): If the OUTR stage is updated with a new data value with RCI[4] = 0. 19-85 V1.0, 2007-06 * User's Manual USIC, UM_V0.2D5 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary * * * Universal Serial Interface Channel Alternative receive buffer event in filling level mode (RBCTRH.RNM = 0): not used Alternative receive buffer event in RCI mode (RBCTRH.RNM = 1): If the OUTR stage is updated with a new value with RCI[4] = 1. Receive buffer error event: The SW reads from an empty buffer. The read data is invalid. The following figure shows the receiver buffer events and interrupts in filling level mode. Note: A buffer event in filling level mode occurs only when the filling level transitions away from the threshold value. Transitions starting with a filling level other than the threshold level generate no trigger event. clear CSRBI LOF data read out new data received CRBERI read from empty receive buffer SRBI set standard receive buffer event SRBIEN AND SRBINP to INT_O0 to INT_O3 ... standard receive buffer interrupt 0 AND 1 LIMIT equals RBFLVL clear RBERI set receive buffer error event RBERIEN AND ARBINP receive buffer error interrupt to INT_O0 to INT_O3 USIC_RB_RNM0 ... Figure 19-20 Receiver Buffer Events in Filling Level Mode User's Manual USIC, UM_V0.2D5 19-86 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel The following figure shows the receiver buffer events and interrupts in RCI mode. clear CSRBI new data in OUTRL RCI[4] SRBI set standard receive buffer event SRBIEN AND SRBINP to INT_O0 to INT_O3 to INT_O0 to INT_O3 ... 0 1 standard receive buffer interrupt alternative receive buffer event AND alternative receive buffer interrupt ... set CARBI clear ARBI ARBIEN ARBINP CRBERI read from empty receive buffer clear RBERI set receive buffer error event RBERIEN AND receive buffer error interrupt to INT_O0 to INT_O3 USIC_RB_RNM1 ... Figure 19-21 Receiver Buffer Events in RCI Mode The table below shows the registers, bits and bit fields to indicate the buffer events and to control the interrupts related to the FIFO buffers (transmit and the receive) of a USIC channel. Table 19-15 Buffer Events and Interrupt Handling Event Standard transmit buffer event Transmit buffer error event Standard receive buffer event Alternative receive buffer event Receive buffer error event Indication Flag TRBSRL. STBI TRBSRL. TBERI TRBSRL. SRBI TRBSRL. ARBI TRBSRL. RBERI Indication cleared by TRBSCR. CSTBI TRBSCR. CTBERI TRBSCR. CSRBI TRBSCR. CARBI TRBSCR. CRBERI Interrupt enabled by TBCTRH. STBIEN TBCTRH. TBERIEN RBCTRH. SRBIEN RBCTRH. ARBIEN RBCTRH. RBERIEN SRx Output selected by TBCTRH. STBINP TBCTRH. ATBINP RBCTRH. SRBINP RBCTRH. ARBINP RBCTRH. ARBINP User's Manual USIC, UM_V0.2D5 19-87 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.2.13.3 FIFO Buffer Bypass The data bypass mechanism is part of the transmit FIFO control block. It allows to introduce a data word in the data stream without modifying the transmit FIFO buffer contents, e.g. to send a high-priority message. The bypass structure consists of a bypass data word of maximum 16 bits in register BYP and some associated control information in registers BYPCRL and BYPCRH. For example, these bits define the word length of the bypass data word and configure a transfer trigger and gating mechanism similar to the one for the transmit buffer TBUF. The bypass data word can be tagged valid or invalid for transmission by bit BYRCRL.BDV (bypass data valid). A combination of data flow related and event related criteria define whether the bypass data word is considered valid for transmission. A data validation logic checks the start conditions for this data word. Depending on the result of the check, the transmit buffer register TBUF is loaded with different values, according to the following rules: * * * Data from the transmit FIFO buffer or the bypass data can only be transferred to TBUF if TCSRL.TDV = 0 (TBUF is empty). Bypass data can only be transferred to TBUF if the bypass is enabled by BYPCRL.BDEN or the selecting gating condition is met. If the bypass data is valid for transmission and has either a higher transmit priority than the FIFO data or if the transmit FIFO is empty, the bypass data is transferred to TBUF. If the bypass data is valid for transmission and has a lower transmit priority than the FIFO buffer that contains valid data, the oldest transmit FIFO data is transferred to TBUF. If the bypass data is not valid for transmission and the FIFO buffer contains valid data, the oldest FIFO data is transferred to TBUF. If neither the bypass data is valid for transmission nor the transmit FIFO buffer contains valid data, TBUF is unchanged. A transfer gating logic enables or disables the bypass data word transfer to TBUF under SW or under HW control. If the input stage DX2 is not needed for data shifting, signal DX2S can be used for gating purposes. The transfer gating logic is controlled by bit field BYPCRL.BDEN. A transfer trigger logic supports data word transfers related to events, e.g. timer based or related to an input pin. If the input stage DX2 is not needed for data shifting, signal DX2T can be used for trigger purposes. The transfer trigger logic is controlled by bit BYPCRL.BDVTR. A bypass data validation logic combining the inputs from the gating logic, the triggering logic and TCSRL.TDV. * * * The bypass data validation is based on the logic blocks shown in Figure 19-22. * * * User's Manual USIC, UM_V0.2D5 19-88 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel BDVTR transfer trigger TBUF, TDV DX2T shift control input DX2 DX2S BDV transfer gating BDEN bypass data validation BDSSM USIC_BDV Figure 19-22 Bypass Data Validation With this structure, the following bypass data transfer functionality can be achieved: * Bit BYPCRL.BDSSM = 1 has to be programmed for a single-shot mechanism. After each transfer of the bypass data word to TBUF, the bypass data word has to be tagged valid again. This can be achieved either by writing a new bypass data word to BYP or by DX2T if BDVTR = 1 (e.g. trigger on a timer base or an edge at a pin). Bit BYPCRL.BDSSM = 0 has to be programmed if the bypass data is permanently valid for transmission (e.g. as alternative data if the data FIFO runs empty). * 19.2.13.4 FIFO Access Constraints The data in the shared FIFO buffer area is accessed by the HW mechanisms for data transfer of each communication channel (for transmission and reception) and by SW to read out received data or to write data to be transmitted. As a consequence, the data delivery rate can be limited by the FIFO mechanism. Each access by HW to the FIFO buffer area has priority over a SW access, that is delayed in case of an access collision. In order to avoid data loss and stalling of the CPU due to delayed SW accesses, the baud rate, the word length and the SW access mechanism have to be taken into account. Each access to the FIFO data buffer area by SW or by HW takes one period of fSYS. Especially a continuous flow of very short, consecutive data words can lead to an access limitation. User's Manual USIC, UM_V0.2D5 19-89 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.2.13.5 Handling of FIFO Transmit Control Information In addition to the transmit data, the transmit control information TCI can be transferred from the transmit FIFO or bypass structure to the USIC channel. Depending on the selected protocol and the enabled update mechanism, some settings of the USIC channel parameters can be modified. The modifications are based on the TCI of the FIFO data word loaded to TBUF or by the bypass control information if the bypass data is loaded into TBUF. * * TCSRL.SELMD = 1: update of PCRH.CTR[20:16] by FIFO TCI or BYPCRH.BSELO with additional clear of PCRH.CTR[23:21] TCSRL.WLEMD = 1: update of SCTRH.WLE and TCSRL.EOF by FIFO TCI or BYPCRL.BWLE (if the WLE information is overwritten by TCI or BWLE, the user has to take care that FLE is set accordingly) TCSRL.FLEMD = 1: update of SCTRH.FLE[4:0] by FIFO TCI or BYPCRL.BWLE with additional clear of SCTRH.FLE[5] TCSRL.WAMD = 1: update of TCSRL.WA by FIFO TCI[4] * * FIFO / bypass 16 BDATA transmit data 16 USIC channel TBUF SELMD transmit FIFO 5 TCI BSELO bypass control BWLE 5 0 CTR[20:16] CTR[23:11] WLEMD 4+1 WLE, EOF FLEMD FLE[4:0] 0 FLE[5] WAMD TCI[4] WA USIC_FIFO_TCI Figure 19-23 TCI Handling with FIFO / Bypass User's Manual USIC, UM_V0.2D5 19-90 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.2.14 FIFO Buffer and Bypass Registers 19.2.14.1 Bypass Registers A write action to at least the low byte of the bypass data register sets BYPCRL.BDV = 1 (bypass data tagged valid). BYP Bypass Data Register 15 14 13 12 11 10 9 (100H) 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 BDATA rw Bit (Field) BDATA Width [15:0] Type Description rw Bypass Data This bit field contains the bypass data. BYPCRL Bypass Control Register L 15 BDV rh 14 0 r 13 12 11 10 9 0 r (104H) 8 BD SSM rw 7 6 0 r 5 4 Reset Value: 0000H 3 2 1 0 B BD PRIO VTR rw rw BDEN rw BWLE rw Field BWLE Bits [3:0] Type Description rw Bypass Word Length This bit field defines the word length of the bypass data. The word length is given by BWLE + 1 with the data word being right-aligned in the data buffer at the bit positions [BWLE down to 0]. The bypass data word is always considered as an own frame with the length of BWLE. Same coding as SCTRH.WLE. User's Manual USIC, UM_V0.2D5 19-91 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field BDSSM Bits 8 Type Description rw Bypass Data Single Shot Mode This bit defines if the bypass data is considered as permanently valid or if the bypass data is only transferred once (single shot mode). 0B The bypass data is still considered as valid after it has been loaded into TBUF. The loading of the data into TBUF does not clear BDV. 1B The bypass data is considered as invalid after it has been loaded into TBUF. The loading of the data into TBUF clears BDV. Bypass Data Enable This bit field defines if and how the transfer of bypass data to TBUF is enabled. 00B The transfer of bypass data is disabled. 01B The transfer of bypass data to TBUF is possible. Bypass data will be transferred to TBUF according to its priority if BDV = 1. 10B Gated bypass data transfer is enabled. Bypass data will be transferred to TBUF according to its priority if BDV = 1 and while DX2S = 0. 11B Gated bypass data transfer is enabled. Bypass data will be transferred to TBUF according to its priority if BDV = 1 and while DX2S = 1. Bypass Data Valid Trigger This bit enables the bypass data for being tagged valid when DX2T is active (for time framing or timeout purposes). 0B Bit BDV is not influenced by DX2T. 1B Bit BDV is set if DX2T is active. Bypass Priority This bit defines the priority between the bypass data and the transmit FIFO data. 0B The transmit FIFO data has a higher priority than the bypass data. 1B The bypass data has a higher priority than the transmit FIFO data. Universal Serial Interface Channel BDEN [11:10] rw BDVTR 12 rw BPRIO 13 rw User's Manual USIC, UM_V0.2D5 19-92 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field BDV Bits 15 Type Description rh Bypass Data Valid This bit defines if the bypass data is valid for a transfer to TBUF. This bit is set automatically by a write access to at least the low-byte of register BYP. It can be cleared by SW by writing TRBSCR.CBDV. The bypass data is not valid. 0B 1B The bypass data is valid. Reserved read as 0; should be written with 0. Universal Serial Interface Channel 0 [7:4], 9, 14 r BYPCRH Bypass Control Register H 15 14 13 12 11 10 0 r 9 (106H) 8 7 6 5 4 Reset Value: 0000H 3 2 BSELO rw 1 0 Field BSELO Bits [4:0] Type Description rw Bypass Select Outputs This bit field contains the value that is written to PCRH.CTR[20:16] if bypass data is transferred to TBUF while TCSRL.SELMD = 1. In the SSC protocol, this bit field can be used to define which SELOx output line will be activated when bypass data is transmitted. Reserved read as 0; should be written with 0. 0 [15:5] r User's Manual USIC, UM_V0.2D5 19-93 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.2.14.2 General FIFO Buffer Control Registers The transmit and receive FIFO status information of UxCy is given in registers UxCy_TRBSRL/H. The bits related to the transmitter buffer in this register can only by written if the transmit buffer functionality is enabled by CCFG.TB = 1, otherwise write accesses are ignored. A similar behavior applies for the bits related to the receive buffer referring to CCFG.RB = 1. The interrupt flags (event flags) in the transmit and receive FIFO status register TRBSRL can be cleared by writing a 1 to the corresponding bit position in register TRBSCR, whereas writing a 0 has to effect on these bits. Writing a 1 by SW to SRBI, RBERI, ARBI, STBI, or TBERI sets the corresponding bit to simulate the detection of a transmit/receive buffer event, but without activating any service request output (therefore, see FMR.SIOx). Bits TBUS and RBUS have been implemented for testing purposes. They can be ignored by data handling SW. Please note that a read action can deliver either a 0 or a 1 for these bits. It is recommended to treat them as "don't care". TRBSRL Transmit / Receive Buffer Status Reg. L (118H) 15 0 r 14 13 12 11 10 0 r 9 TB ERI rwh 8 ST BI rwh 7 0 r 6 5 4 T T T FUL EMP BUS L TY rh rh rh Reset Value: 0808H 3 2 1 RB ERI rwh 0 SR BI rwh R R R AR FUL EMP BI BUS L TY rh rh rh rwh Field SRBI Bits 0 Type Description rwh Standard Receive Buffer Event This bit indicates that a standard receive buffer event has been detected. It is cleared by writing TRBSCR.CSRBI = 1. If enabled by RBCTRH.SRBIEN, the service request output SRx selected by RBCTRH.SRBINP becomes activated if a standard receive buffer event is detected. 0B A standard receive buffer event has not been detected. 1B A standard receive buffer event has been detected. User's Manual USIC, UM_V0.2D5 19-94 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field RBERI Bits 1 Type Description rwh Receive Buffer Error Event This bit indicates that a receive buffer error event has been detected. It is cleared by writing TRBSCR.CRBERI = 1. If enabled by RBCTRH.RBERIEN, the service request output SRx selected by RBCTRH.ARBINP becomes activated if a receive buffer error event is detected. A receive buffer error event has not been 0B detected. 1B A receive buffer error event has been detected. Alternative Receive Buffer Event This bit indicates that an alternative receive buffer event has been detected. It is cleared by writing TRBSCR.CARBI = 1. If enabled by RBCTRH.ARBIEN, the service request output SRx selected by RBCTRH.ARBINP becomes activated if an alternative receive buffer event is detected. 0B An alternative receive buffer event has not been detected. 1B An alternative receive buffer event has been detected. Receive Buffer Empty This bit indicates whether the receive buffer is empty. 0B The receive buffer is not empty. 1B The receive buffer is empty. Receive Buffer Full This bit indicates whether the receive buffer is full. 0B The receive buffer is not full. 1B The receive buffer is full. Universal Serial Interface Channel ARBI 2 rwh REMPTY 3 rh RFULL 4 rh User's Manual USIC, UM_V0.2D5 19-95 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field RBUS Bits 5 Type Description rh Receive Buffer Busy This bit indicates whether the receive buffer is currently updated by the FIFO handler. 0B The receive buffer information has been completely updated. 1B The OUTRL/H update from the FIFO memory is ongoing. A read from OUTRL/H will be delayed. FIFO pointers from the previous read are not yet updated. Standard Transmit Buffer Event This bit indicates that a standard transmit buffer event has been detected. It is cleared by writing TRBSCR.CSTBI = 1. If enabled by TBCTRH.STBIEN, the service request output SRx selected by TBCTRH.STBINP becomes activated if a standard transmit buffer event is detected. 0B A standard transmit buffer event has not been detected. 1B A standard transmit buffer event has been detected. Transmit Buffer Error Event This bit indicates that a transmit buffer error event has been detected. It is cleared by writing TRBSCR.CTBERI = 1. If enabled by TBCTRH.TBERIEN, the service request output SRx selected by TBCTRH.ATBINP becomes activated if a transmit buffer error event is detected. A transmit buffer error event has not been 0B detected. 1B A transmit buffer error event has been detected. Transmit Buffer Empty This bit indicates whether the transmit buffer is empty. The transmit buffer is not empty. 0B 1B The transmit buffer is empty. Universal Serial Interface Channel STBI 8 rwh TBERI 9 rwh TEMPTY 11 rh User's Manual USIC, UM_V0.2D5 19-96 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field TFULL Bits 12 Type Description rh Transmit Buffer Full This bit indicates whether the transmit buffer is full. 0B The transmit buffer is not full. The transmit buffer is full. 1B Transmit Buffer Busy This bit indicates whether the transmit buffer is currently updated by the FIFO handler. The transmit buffer information has been 0B completely updated. 1B The FIFO memory update after write to INx is ongoing. A write to INx will be delayed. FIFO pointers from the previous INx write are not yet updated. Reserved read as 0; should be written with 0. Universal Serial Interface Channel TBUS 13 rh 0 [7:6], [15:14] r TRBSRH Transmit / Receive Buffer Status Reg H (11AH) 15 0 r 14 13 12 11 TBFLVL rh 10 9 8 7 0 r 6 5 4 Reset Value: 0000H 3 RBFLVL rh 2 1 0 Field RBFLVL Bits [6:0] Type Description rh Receive Buffer Filling Level This bit field indicates the filling level of the receive buffer, starting with 0 for an empty buffer. Transmit Buffer Filling Level This bit field indicates the filling level of the transmit buffer, starting with 0 for an empty buffer. Reserved read as 0; should be written with 0. TBFLVL [14:8] rh 0 7, 15 r User's Manual USIC, UM_V0.2D5 19-97 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel The bits in register TRBSCR are used to clear the notification bits in register TRBSRL or to clear the FIFO mechanism for the transmit or receive buffer. A read action always delivers 0. TRBSCR Transmit / Receive Buffer Status Clear Reg (11CH) 15 14 13 12 0 r 11 10 9 8 C ST BI w 7 6 5 0 r 4 FLU FLU SH SH TB RB w w C C TB BDV ERI w w Reset Value: 0000H 3 2 C AR BI w 1 C RB ERI w 0 C SR BI w Field CSRBI Bits 0 Type Description w Clear Standard Receive Buffer Event 0B No effect. 1B Clear TRBSRL.SRBI. Clear Receive Buffer Error Event 0B No effect. 1B Clear TRBSRL.RBERI. Clear Alternative Receive Buffer Event 0B No effect. 1B Clear TRBSRL.ARBI. Clear Standard Transmit Buffer Event 0B No effect. Clear TRBSRL.STBI. 1B Clear Transmit Buffer Error Event 0B No effect. 1B Clear TRBSRL.TBERI. Clear Bypass Data Valid 0B No effect. 1B Clear BYPCRL.BDV. Flush Receive Buffer 0B No effect. 1B The receive FIFO buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the FIFO buffer is not taking part in data traffic. CRBERI 1 w CARBI 2 w CSTBI 8 w CTBERI 9 w CBDV 10 w FLUSHRB 14 w User's Manual USIC, UM_V0.2D5 19-98 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field FLUSHTB Bits 15 Type Description w Flush Transmit Buffer 0B No effect. 1B The transmit FIFO buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the FIFO buffer is not taking part in data traffic. Reserved read as 0; should be written with 0. Universal Serial Interface Channel 0 [7:3], [13:11] r User's Manual USIC, UM_V0.2D5 19-99 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.2.14.3 Transmit FIFO Buffer Control Registers The transmit FIFO buffer is controlled by registers TBCTRL and TBCTRH. These registers can only by written if the transmit buffer functionality is enabled by CCFG.TB = 1, otherwise write accesses are ignored. TBCTRL Transmitter Buffer Control Reg. L 15 0 r 14 13 12 11 10 9 (110H) 8 7 0 r 6 5 4 Reset Value: 0000H 3 2 1 0 LIMIT rw DPTR w Field DPTR Bits [5:0] Type Description w Data Pointer This bit field defines the start value for the transmit buffer pointers when assigning the FIFO entries to the transmit FIFO buffer. A read always delivers 0. When writing DPTR while SIZE = 0, both internal pointers are updated with the written value and the buffer is considered as empty. A write access to DPTR while SIZE > 0 is ignored and does not modify the pointers. Limit For Interrupt Generation This bit field defines the target filling level of the transmit FIFO buffer that is used for the standard transmit buffer event detection. Reserved read as 0; should be written with 0. LIMIT [13:8] rw 0 [7:6], [15:14] r TBCTRH Transmitter Buffer Control Reg. H 15 TB ERI EN rw 14 ST BI EN rw 13 0 r 12 LOF rw 11 0 r 10 9 SIZE rw (112H) 8 7 6 0 r 5 4 Reset Value: 0000H 3 2 0 r 1 0 ATBINP rw STBINP rw User's Manual USIC, UM_V0.2D5 19-100 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel Field STBINP Bits [1:0] Type Description rw Standard Transmit Buffer Interrupt Node Pointer This bit field defines which service request output SRx will be activated in case of a standard transmit buffer event. 00B Output SR0 will be activated. 01B Output SR1 will be activated. 10B Output SR2 will be activated. 11B Output SR3 will be activated. Alternative Transmit Buffer Interrupt Node Pointer This bit field define which service request output SRx will be activated in case of a transmit buffer error event. 00B Output SR0 will be activated. 01B Output SR1 will be activated. 10B Output SR2 will be activated. 11B Output SR3 will be activated. Buffer Size This bit field defines the number of FIFO entries assigned to the transmit FIFO buffer. 000B The FIFO mechanism is disabled. The buffer does not accept any request for data. 001B The FIFO buffer contains 2 entries. 010B The FIFO buffer contains 4 entries. 011B The FIFO buffer contains 8 entries. 100B The FIFO buffer contains 16 entries. 101B The FIFO buffer contains 32 entries. 110B The FIFO buffer contains 64 entries. 111B reserved ATBINP [4:3] rw SIZE [10:8] rw User's Manual USIC, UM_V0.2D5 19-101 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field LOF Bits 12 Type Description rw Buffer Event on Limit Overflow This bit defines which relation between filling level and programmed limit leads to a standard transmit buffer event. 0B A standard transmit buffer event occurs when the filling level equals the limit value and gets lower due to transmission of a data word. 1B A standard transmit buffer interrupt event occurs when the filling level equals the limit value and gets bigger due to a write access to a data input location INx. Standard Transmit Buffer Interrupt Enable This bit enables/disables the generation of a standard transmit buffer interrupt in case of a standard transmit buffer event. The standard transmit buffer interrupt 0B generation is disabled. 1B The standard transmit buffer interrupt generation is enabled. Transmit Buffer Error Interrupt Enable This bit enables/disables the generation of a transmit buffer error interrupt in case of a transmit buffer error event (SW writes to a full transmit buffer). 0B The transmit buffer error interrupt generation is disabled. 1B The transmit buffer error interrupt generation is enabled. Reserved read as 0; should be written with 0. Universal Serial Interface Channel STBIEN 14 rw TBERIEN 15 rw 0 2, [7:5], 11, 13 r User's Manual USIC, UM_V0.2D5 19-102 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.2.14.4 Receive FIFO Buffer Control Registers The receive FIFO buffer is controlled by registers RBCTRL and RBCTRH. These registers can only by written if the receive buffer functionality is enabled by CCFG.RB = 1, otherwise write accesses are ignored. RBCTRL Receiver Buffer Control Register L 15 0 r 14 13 12 11 10 9 (114H) 8 7 0 r 6 5 4 Reset Value: 0000H 3 2 1 0 LIMIT rw DPTR w Field DPTR Bits [5:0] Type Description w Data Pointer This bit field defines the start value for the receive buffer pointers when assigning the FIFO entries to the receive FIFO buffer. A read always delivers 0. When writing DPTR while SIZE = 0, both internal pointers are updated with the written value and the buffer is considered as empty. A write access to DPTR while SIZE > 0 is ignored and does not modify the pointers. Limit For Interrupt Generation This bit field defines the target filling level of the receive FIFO buffer that is used for the standard receive buffer event detection. Reserved read as 0; should be written with 0. LIMIT [13:8] rw 0 [7:6], [15:14] r RBCTRH Receiver Buffer Control Register H 15 RB ERI EN rw 14 SR BI EN rw 13 12 11 10 9 SIZE rw (116H) 8 7 6 5 0 r 4 Reset Value: 0000H 3 2 0 r 1 0 AR BI LOF RNM EN rw rw rw RCIM rw ARBINP rw SRBINP rw User's Manual USIC, UM_V0.2D5 19-103 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel Field SRBINP Bits [1:0] Type Description rw Standard Receive Buffer Interrupt Node Pointer This bit field defines which service request output SRx will be activated in case of a standard receive buffer event. 00B Output SR0 will be activated. 01B Output SR1 will be activated. 10B Output SR2 will be activated. 11B Output SR3 will be activated. Alternative Receive Buffer Interrupt Node Pointer This bit field defines which service request output SRx will be activated in case of an alternative receive buffer event or a receive buffer error event. 00B The output SR0 will be activated. 01B The output SR1 will be activated. 10B The output SR2 will be activated. 11B The output SR3 will be activated. Receiver Control Information Mode This bit field defines which information from the receiver status register RBUFSR is propagated as 5 bit receiver control information RCI[4:0] to the receive FIFO buffer and can be read out in registers OUT(D)RH. 00B RCI[4] = PERR, RCI[3:0] = WLEN 01B RCI[4] = SOF, RCI[3:0] = WLEN 10B RCI[4] = 0, RCI[3:0] = WLEN 11B RCI[4] = PERR, RCI[3] = PAR, RCI[2:1] = 00B, RCI[0] = SOF ARBINP [4:3] rw RCIM [7:6] rw User's Manual USIC, UM_V0.2D5 19-104 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field SIZE Bits [10:8] Type Description rw Buffer Size This bit field defines the number of FIFO entries assigned to the receive FIFO buffer. 000B The FIFO mechanism is disabled. The buffer does not accept any request for data. 001B The FIFO buffer contains 2 entries. 010B The FIFO buffer contains 4 entries. 011B The FIFO buffer contains 8 entries. 100B The FIFO buffer contains 16 entries. 101B The FIFO buffer contains 32 entries. 110B The FIFO buffer contains 64 entries. 111B reserved Receiver Notification Mode This bit defines the receive buffer event mode. The receive buffer error event is not affected by RNM. Filling level mode: 0B A standard receive buffer event occurs when the filling level equals the limit value and changes, either due to a read access from OUTRL (LOF = 0) or due to a new received data word (LOF = 1). 1B RCI mode: A standard receive buffer event occurs when register OUTRL is updated with a new value if the corresponding value in OUTRH.RCI[4] = 0. If OUTRH.RCI[4] = 1, an alternative receive buffer event occurs instead of the standard receive buffer event. Buffer Event on Limit Overflow This bit defines which relation between filling level and programmed limit leads to a standard receive buffer event in filling level mode (RNM = 0). In RCI mode (RNM = 1), bit fields LIMIT and LOF are ignored. 0B A standard receive buffer event occurs when the filling level equals the limit value and gets lower due to a read access from OUTRL. 1B A standard receive buffer event occurs when the filling level equals the limit value and gets bigger due to the reception of a new data word. Universal Serial Interface Channel RNM 11 rw LOF 12 rw User's Manual USIC, UM_V0.2D5 19-105 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field ARBIEN Bits 13 Type Description rw Alternative Receive Buffer Interrupt Enable This bit enables/disables the generation of an alternative receive buffer interrupt in case of an alternative receive buffer event. 0B The alternative receive buffer interrupt generation is disabled. 1B The alternative receive buffer interrupt generation is enabled. Standard Receive Buffer Interrupt Enable This bit enables/disables the generation of a standard receive buffer interrupt in case of a standard receive buffer event. 0B The standard receive buffer interrupt generation is disabled. 1B The standard receive buffer interrupt generation is enabled. Receive Buffer Error Interrupt Enable This bit enables/disables the generation of a receive buffer error interrupt in case of a receive buffer error event (the SW reads from an empty receive buffer). The receive buffer error interrupt generation is 0B disabled. 1B The receive buffer error interrupt generation is enabled. Reserved read as 0; should be written with 0. Universal Serial Interface Channel SRBIEN 14 rw RBERIEN 15 rw 0 2, 5 r User's Manual USIC, UM_V0.2D5 19-106 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.2.14.5 FIFO Buffer Data Registers The 32 independent data input locations IN00 to IN31 are addresses that can be used as data entry locations for the transmit FIFO buffer. Data written to one of these locations will be stored in the transmit buffer FIFO. Additionally, the 5 bit coding of the number [31:0] of the addressed data input location represents the transmit control information TCI. If the FIFO is already full and new data is written to it, the write access is ignored and a transmit buffer error event is signaled. INx (x = 00-31) Transmit FIFO Buffer Input Location x(180H + x *4) 15 14 13 12 11 10 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 TDATA w Field TDATA Bits [15:0] Type Description w Transmit Data This bit field contains the data to be transmitted (write view), read actions deliver 0. A write action to at least the low byte of TDATA triggers the data storage in the FIFO. User's Manual USIC, UM_V0.2D5 19-107 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel The receiver FIFO buffer output register OUTRL shows the oldest received data word in the FIFO buffer. A read action from this address location delivers the received data. With a read access of at least the low byte, the data is declared to be read and the next entry becomes visible. Register OUTRH contains the receiver control information RCI containing the information selected by RBCTRH.RCIM. Write accesses are ignored. OUTRL Receiver Buffer Output Register L 15 14 13 12 11 10 9 (120H) 8 DSR rh 7 6 5 4 Reset Value: 0000H 3 2 1 0 Field DSR Bits [15:0] Type Description rh Received Data This bit field monitors the content of the oldest data word in the receive FIFO. Reading at least the low byte releases the buffer entry currently shown in DSR. OUTRH Receiver Buffer Output Register H 15 14 13 12 11 10 0 r 9 (122H) 8 7 6 5 4 Reset Value: 0000H 3 2 RCI rh 1 0 Field RCI Bits [4:0] Type Description rh Receiver Control Information This bit field monitors the receiver control information associated to DSR. The bit structure of RCI depends on bit field RBCTRH.RCIM. Reserved read as 0; should be written with 0. 0 [15:5] r User's Manual USIC, UM_V0.2D5 19-108 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel If a debugger should be used to monitor the received data in the FIFO buffer, the FIFO mechanism must not be activated in order to guaranty data consistency. Therefore, a second address set is available, named OUTDRL/H (D like debugger), having the same bit fields like the original buffer output register OUTRL/H, but without the FIFO mechanism. A debugger can read here (in order to monitor the receive data flow) without the risk of data corruption. Write accesses are ignored. OUTDRL Receiver Buffer Output Register L for Debugger (124H) 15 14 13 12 11 10 9 8 DSR rh 7 6 5 4 Reset Value: 0000H 3 2 1 0 Field DSR Bits [15:0] Type Description rh Data from Shift Register Same as OUTRL.DSR, but without releasing the buffer after a read action. OUTDRH Receiver Buffer Output Register H for Debugger (126H) 15 14 13 12 11 10 0 r 9 8 7 6 5 4 Reset Value: 0000H 3 2 RCI rh 1 0 Field RCI 0 Bits [4:0] [15:5] Type Description rh r Receive Control Information from Shift Register Same as OUTRH.RCI. Reserved read as 0; should be written with 0. User's Manual USIC, UM_V0.2D5 19-109 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.2.14.6 FIFO Buffer Pointer Registers The pointers for FIFO handling of the transmit and receive FIFO buffers are located in registers TRBPTRL (for the transmit buffer) and TRBPTRH (for the receive buffer). The pointers are automatically handled by the FIFO buffer mechanism and do not need to be modified by SW. As a consequence, these registers can only be read by SW (e.g. for verification purposes), whereas write accesses are ignored. TRBPTRL Transmit / Receive Buffer Pointer Reg L (108H) 15 0 r 14 13 12 11 10 9 8 7 0 r 6 5 4 Reset Value: 0000H 3 2 1 0 TDOPTR rh TDIPTR rh Field TDIPTR Bits [5:0] Type Description rh Transmitter Data Input Pointer This bit field indicates the buffer entry that will be used for the next transmit data coming from the INx addresses. Transmitter Data Input Pointer This bit field indicates the buffer entry that will be used for the next transmit data to be output to TBUF. Reserved read as 0; should be written with 0. TDOPTR [13:8] rh 0 [7:6], [15:14] r TRBPTRH Transmit / Receive Buffer Pointer Reg H (10AH) 15 0 r 14 13 12 11 10 9 8 7 0 r 6 5 4 Reset Value: 0000H 3 2 1 0 RDOPTR rh RDIPTR rh Field RDIPTR Bits [5:0] Type Description rh Receiver Data Input Pointer This bit field indicates the buffer entry that will be used for the next receive data coming from RBUF. 19-110 V1.0, 2007-06 User's Manual USIC, UM_V0.2D5 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field RDOPTR Bits [13:8] Type Description rh Receiver Data Input Pointer This bit field indicates the buffer entry that will be used for the next receive data to be output at the OUT(D)RL addresses. Reserved read as 0; should be written with 0. Universal Serial Interface Channel 0 [7:6], [15:14] r User's Manual USIC, UM_V0.2D5 19-111 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.3 Asynchronous Serial Channel (ASC = UART) The asynchronous serial channel ASC covers the reception and the transmission of asynchronous data frames and provides a hardware LIN support. The receiver and transmitter being independent, frames can start at different points in time for transmission and reception. The ASC mode is selected by CCR.MODE = 0010B with CCFG.ASC = 1 (ASC mode available). This chapter contains the following sections: * * * * * * Signal description (see Section 19.2.5) Frame format (see Section 19.3.2) Bit timing (see Section 19.3.3.1) Operating the ASC (see Section 19.3.3) Protocol registers (see Section 19.3.4) Hardware LIN support (see Section 19.3.5) 19.3.1 Signal Description An ASC connection is characterized by the use of a single connection line between a transmitter and a receiver. The receiver input RxD signal is handled by the input stage DX0. ASC module A RBUF DX0 DIN RxD RxD DIN ASC module B DX0 RBUF DOUT TBUF TxD TxD DOUT TBUF transfer control fsys (ASC A) baud rate generator transfer control baud rate generator fsys (ASC B) ASC_signals_fd Figure 19-24 ASC Signal Connections for Full-Duplex Communication For full-duplex communication, an independent communication line is needed for each transfer direction. Figure 19-24 shows an example with a point-to-point full-duplex User's Manual USIC, UM_V0.2D5 19-112 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel connection between two communication partners ASC A and ASC B. For half-duplex or multi-transmitter communication, a single communication line is shared between the communication partners. Figure 19-25 shows an example with a point-to-point half-duplex connection between ASC A and ASC B. In this case, the user has to take care that only one transmitter is active at a time. In order to support transmitter collision detection, the input stage DX1 can be used to monitor the level of the transmit line and to check if the line is in the idle state or if a collision occurred. There are two possibilities to connect the receiver input DIN to the transmitter output DOUT. Communication partner ASC A uses an internal connection with only the transmit pin TxD, that is delivering its input value as RxD to the DX0 input stage for reception and to DX1 to check for transmitter collisions. Communication partner ASC B uses an external connection between the two pins TxD and RxD. ASC module A RBUF DX0 DIN RxD DIN ASC module B DX0 RBUF TBUF DOUT DX1 transfer control TxD TxD DOUT DX1 transfer control baud rate generator TBUF fsys (ASC A) baud rate generator fsys (ASC B) ASC_signals_hd Figure 19-25 ASC Signal Connections for Half-Duplex Communication 19.3.2 * * * * * Frame Format A standard ASC frame is shown in Figure 19-26. It consists of: An idle time with the signal level 1. One start of frame bit (SOF) with the signal level 0. A data field containing a programmable number of data bits (1-63). A parity bit (P), programmable for either even or odd parity. It is optionally possible to handle frames without parity bit. One or two stop bits with the signal level 1. User's Manual USIC, UM_V0.2D5 19-113 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 1 idle 0 SOF 1 bit data 1-63 bits P stop idle 0-1 bit 1-2 bits ASC_frame_format Figure 19-26 Standard ASC Frame Format The protocol specific bits (SOF, P, stop) are automatically handled by the ASC protocol state machine and do not appear in the data flow via the receive and transmit buffers. 19.3.2.1 Idle Time The receiver and the transmitter independently check the respective data input lines (DX0, DX1) for being idle. The idle detection ensures that an SOF bit of a recently enabled ASC module does not collide with an already running frame of another ASC module. In order to start the idle detection, the user SW has to clear bits PSR.RXIDLE and/or PSR.TXIDLE, e.g. before selecting the ASC mode or during operation. If a bit is cleared by SW while a data transfer is in progress, the currently running frame transfer is finished normally before starting the idle detection again. Frame reception is only possible if PSR.RXIDLE = 1 and frame transmission is only possible if PSR.TXIDLE = 1. The duration of the idle detection depends on the setting of bit PCRL.IDM. In the case that a collision is not possible, the duration can be shortened and the bus can be declared as being idle by setting PCRL.IDM = 0. In the case that the complete idle detection is enabled by PCRL.IDM = 1, the data input of DX0 is considered as idle (PSR.RXIDLE becomes set) if a certain number of consecutive passive bit times has been detected. The same scheme applies for the transmitter's data input of DX1. Here, bit PSR.TXIDLE becomes set if the idle condition of this input signal has been detected. The duration of the complete idle detection is given by the number of programmed data bits per frame plus 2 (in the case without parity) or plus 3 (in the case with parity). The counting of consecutive bit times with 1 level restarts from the beginning each time an edge is found, after leaving a stop mode or if ASC mode becomes enabled. If the idle detection bits PSR.RXIDLE and/or TXIDLE are cleared by SW, the counting scheme is not stopped (no re-start from the beginning). As a result, the cleared bit(s) can become set immediately again if the respective input line still meets the idle criterion. Please note that the idle time check is based on bit times, so the maximum time can be up to 1 bit time more than programmed value (but not less). User's Manual USIC, UM_V0.2D5 19-114 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.3.2.2 Start Bit Detection The receiver input signal DIN (selected signal of input stage DX0) is checked for a falling edge. An SOF bit is detected if a falling edge occurs while the receiver is idle or after the sampling point of the last stop bit. To increase noise immunity, the SOF bit timing starts with the first falling edge that is detected. If the sampled bit value of the SOF is 1, the previous falling edge is considered to be due to noise and the receiver is considered to be idle again. 19.3.2.3 Data Field The length of the data field (number of data bits) can be programmed by bit field SCTRH.FLE. It can vary between 1 and 63 data bits, corresponding to values of SCTRH.FLE = 0 to 62 (the value of 63 is reserved and must not be programmed in ASC mode). The data field can consist of several data words, e.g. a transfer of 12 data bits can be composed of two 8 bit words, with the 12 bits being split into 8 bits of the first word and 4 bits of the second word. The user SW has to take care that the transmit data is available in-time, once a frame has been started. If the transmit buffer runs empty during a running data frame, the passive data level (SCTRL.PDL) is sent out. The shift direction can be programmed by SCTRL.SDIR. The standard setting for ASC frames with LSB first is achieved with the default setting SDIR = 0. 19.3.2.4 Parity Bit The ASC allows parity generation for transmission and parity check for reception on frame base. The type of parity can be selected by bit field CCR.PM, common for transmission and reception (no parity, even or odd parity). If the parity handling is disabled, the ASC frame does not contain any parity bit. For consistency reasons, all communication partners have to be programmed to the same parity mode. After the last data bit of the data field, the transmitter automatically sends out its calculated parity bit if parity generation has been enabled. The receiver interprets this bit as received parity and compares it to its internally calculated one. The received parity bit value and the result of the parity check are monitored in the receiver buffer status registers as receiver buffer status information. These registers contain bits to monitor a protocol-related argument (PAR) and protocol-related error indication (PERR). 19.3.2.5 Stop Bit(s) Each ASC frame is completed by 1 or 2 of stop bits with the signal level 1 (same level as the idle level). The number of stop bits is programmable by bit PSR.STPB. A new start bit can transferred directly after the last stop bit. User's Manual USIC, UM_V0.2D5 19-115 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.3.3 * Operating the ASC In order to operate the ASC protocol, the following issues have to be considered: Select ASC mode: It is recommended to configure all parameters of the ASC that do not change during run time while CCR.MODE = 0000B. Bit field SCTRL.TRM = 01B has to be programmed. The configuration of the input stages has to be done while CCR.MODE = 0000B to avoid unintended edges of the input signals and the ASC mode can be enabled by CCR.MODE = 0010B afterwards. Pin connections: Establish a connection of input stage DX0 with the selected receive data input pin (signal DIN) with DX0CR.INSW = 0 and configure a transmit data output pin (signal DOUT). For collision or idle detection of the transmitter, the input stage DX1 has to be connected to the selected transmit output pin, also with DX1CR.INSW = 0. Additionally, program DX2CR.INSW = 0. Due to the handling of the input data stream by the synchronous protocol handler, the propagation delay of the synchronization in the input stage has to be considered. Bit timing configuration: The desired baud rate setting has to be selected, comprising the fractional divider, the baud rate generator and the bit timing. Please note that not all feature combinations can be supported by the application at the same time, e.g. due to propagation delays. For example, the length of a frame is limited by the frequency difference of the transmitter and the receiver device. Furthermore, in order to use the average of samples (SMD = 1), the sampling point has to be chosen to respect the signal settling and data propagation times. Data format configuration: The word length, the frame length, and the shift direction have to be set up according to the application requirements by programming the registers SCTRL and SCTRH. If required by the application, the data input and output signals can be inverted. Additionally, the parity mode has to be configured (CCR.PM). * * * User's Manual USIC, UM_V0.2D5 19-116 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.3.3.1 Bit Timing In ASC mode, each bit (incl. protocol bits) is divided into time quanta in order to provide granularity in the sub-bit range to adjust the sample point to the application requirements. The number of time quanta per bit is defined by bit fields BRGL.DCTQ and the length of a time quantum is given by BRGL.PCTQ. In the example given in Figure 19-27, one bit time is composed of 16 time quanta (BRGL.DCTQ = 15). It is not recommended to program less than 4 time quanta per bit time. Bit field PCRL.SP determines the position of the sampling point for the bit value. The value of PCRL.SP must not be set to a value greater than BRGL.DCTQ. It is possible to sample the bit value only once per bit time or to take the average of samples. Depending on bit PCRL.SMD, either the current input value is directly sampled as bit value, or a majority decision over the input values sampled at the latest three time quanta is taken into account. The standard ASC bit timing consists of 16 time quanta with sampling after 8 or 9 time quanta with majority decision. The bit timing setup (number of time quanta and the sampling point definition) is common for the transmitter and the receiver. Due two independent bit timing blocks, the receiver and the transmitter can be in different time quanta or bit positions inside their frames. The transmission of a frame is aligned to the time quanta generation. 1 bit time PCRL.SP = 15 PCRL.SP = 8 time quanta 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 = sample taken if SMD = 0 Figure 19-27 ASC Bit Timing = samples taken if SMD = 1 ASC_bit_timing The sample point setting has to be adjusted carefully if collision or idle detection is enabled (via DX1 input signal), because the driver delay and some external delays have to be taken into account. The sample point for the transmit line has to be set to a value where the bit level is stable enough to be evaluated. If the sample point is located late in the bit time, the signal itself has more time to become stable, but the robustness against differences in the clock frequency of transmitter and receiver decreases. User's Manual USIC, UM_V0.2D5 19-117 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.3.3.2 Baud Rate Generation The baud rate fASC in ASC mode depends on the number of time quanta per bit time and their timing. The baud rate setting should only be changed while the transmitter and the receiver are idle. The bits in register BRGL define the baud rate setting: * * * BRGL.CTQSEL to define the input frequency fCTQIN for the time quanta generation BRGL.PCTQ to define the length of a time quantum (division of fCTQIN by 1, 2, 3, or 4) BRGL.DCTQ to define the number of time quanta per bit time The standard setting is given by CTQSEL = 00B (fCTQIN = fPDIV) and PPPEN = 0 (fPPP = fPIN). Under these conditions, the baud rate is given by: (19.6) 1 1 1 f ASC = f PIN x ----------------------- x ------------------------ x ------------------------PDIV + 1 PCTQ + 1 DCTQ + 1 In order to generate slower frequencies, two additional divide-by-2 stages can be selected by CTQSEL = 10B (fCTQIN = fSCLK) and PPPEN = 1 (fPPP = fMCLK), leading to: (19.7) f ASC f PIN 1 1 1 = ----------- x ----------------------- x ------------------------- x -------------------------2 x 2 PDIV + 1 PCTQ + 1 DCTQ + 1 19.3.3.3 Noise Detection The ASC receiver permanently checks the data input line of the DX0 stage for noise (the check is independent from the setting of bit PCRL.SMD). Bit PSR.RNS (receiver noise) becomes set if the three input samples of the majority decision are not identical at the sample point for the bit value. The information about receiver noise gets accumulated over several bits in bit PSR.RNS (it has to be cleared by SW) and can trigger a protocol interrupt each time noise is detected if enabled by PCRL.RNIEN. 19.3.3.4 Collision Detection In some applications, such as data transfer over a single data line shared by several sending devices (see Figure 19-25), several transmitters have the possibility to send on the same data output line TxD. In order to avoid collisions of transmitters being active at the same time or to allow a kind of arbitration, a collision detection has been implemented. The data value read at the TxD input at the DX1 stage and the transmitted data bit value are compared after the sampling of each bit value. If enabled by PCRL.CDEN = 1 and a bit sent is not equal to the bit read back, a collision is detected and bit PSR.COL is set. User's Manual USIC, UM_V0.2D5 19-118 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel If enabled, bit PSR.COL = 1 disables the transmitter (the data output lines become 1) and generates a protocol interrupt. The content of the transmit shift register is considered as invalid, so the transmit buffer has to be programmed again. 19.3.3.5 Pulse Shaping For some applications, the 0 level of transmitted bits with the bit value 0 is not applied at the transmit output during the complete bit time. Instead of driving the original 0 level, only a 0 pulse is generated and the remaining time quanta of the bit time are driven with 1 level. The length of a bit time is not changed by the pulse shaping, only the signalling is changed. In the standard ASC signalling scheme, the 0 level is signalled during the complete bit time with bit value 0 (ensured by programming PCRH.PL = 000B). In the case PCRH.PL > 000B, the transmit output signal becomes 0 for the number of time quanta defined by PCRH.PL. In order to support correct reception with pulse shaping by the transmitter, the sample point has to be adjusted in the receiver according to the applied pulse length. 0 pulse for PL = 001B 0 pulse for PL = 010B 0 pulse for PL = 111B 0 pulse for PL = 000B time quanta 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 Figure 19-28 Transmitter Pulse Length Control Figure 19-29 shows an example for the transmission of an 8 bit data word with LSB first and one stop bit (e.g. like for IrDA). The polarity of the transmit output signal has been inverted by SCTRL.DOCFG = 01B. User's Manual USIC, UM_V0.2D5 19-119 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel ASC frame STOP SOF D0 D1 D2 D3 D4 D5 D6 D7 idle bit value DOUT pulse idle 1 0 1 0 ASC_pulse_out Figure 19-29 Pulse Output Example 19.3.3.6 Automatic Shadow Mechanism The contents of the protocol control registers PCRL and PCRH, as well as bit field SCTRH.FLE are internally kept constant while a data frame is transferred by an automatic shadow mechanism (shadowing takes place with each frame start). The registers can be programmed all the time with new settings that are taken into account for the next data frame. During a data frame, the applied (shadowed) setting is not changed, although new values have been written after the start of the data frame. Bit fields SCTRH.WLE and SCTRL.SDIR are shadowed automatically with the start of each data word. As a result, a data frame can consist of data words with a different length. It is recommended to change SCTRL.SDIR only when no data frame is running to avoid interference between HW and SW. Please note that the starting point of a data word can be different for a transmitter and a receiver. In order to ensure correct handling, it is recommended to modify SCTRH.WLE only while transmitter and receiver are both idle. If the transmitter and the receiver are referring to the same data signal (e.g. in a LIN bus system), SCTRH.WLE can be modified while a data transfer is in progress after the RSI event has been detected. 19.3.3.7 End of Frame Control The number of bits per ASC frame is defined by bit field SCTRH.FLE. In order to support different frame length settings for consecutively transmitted frames, this bit field can be modified by HW. The automatic update mechanism is enabled by TCSRL.FLEMD = 1 (in this case, bits TCSRL.WLEMD, SELMD, and WAMD have to be cleared). If enabled, the transmit control information TCI automatically overwrites the bit field TCSRL.FLEMD when the ASC frame is started (leading to frames with 1 to 32 data bits). The TCI value represents the written address location of TBUFxx (without additional data buffer) or INxx (with additional data buffer). With this mechanism, an ASC with 8 data bits is generated by writing a data word to TBUF07 (IN07, respectively). User's Manual USIC, UM_V0.2D5 19-120 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.3.3.8 Mode Control Behavior In ASC mode, the following kernel modes are supported: * * Run Mode 0/1: Behavior as programmed, no impact on data transfers. Stop Mode 0: Bit PSR.TXIDLE is cleared. A new transmission is not started. A current transmission is finished normally. Bit PSR.RXIDLE is not modified. Reception is still possible. When leaving stop mode 0, bit TXIDLE is set according to PCR.IDM. Stop Mode 1: Bit PSR.TXIDLE is cleared. A new transmission is not started. A current transmission is finished normally. Bit PSR.RXIDLE is cleared. A new reception is not possible. A current reception is finished normally. When leaving stop mode 1, bits TXIDLE and RXIDLE are set according to PCR.IDM. * 19.3.3.9 Disabling ASC Mode In order to switch off ASC mode without any data corruption, the receiver and the transmitter have to be both idle. This is ensured by requesting Stop Mode 1 in register KSCFG. After waiting for the end of the frame, the ASC mode can be disabled. 19.3.3.10 Protocol Interrupt Events The following protocol-related events are generated in ASC mode and can lead to a protocol interrupt. The collision detection and the transmitter frame finished events are related to the transmitter, whereas the receiver events are given by the synchronization break detection, the receiver noise detection, the format error checks and the end of the received frame. Please note that the bits in register PSR are not automatically cleared by HW and have to be cleared by SW in order to monitor new incoming events. * Collision detection: This interrupt indicates that the transmitted value (DOUT) does not match with the input value of the DX1 input stage at the sample point of a bit. For more details refer to Section 19.3.3.4. Transmitter frame finished: This interrupt indicates that the transmitter has completely finished a frame. Bit PSR.TFF becomes set at the end of the last stop bit. The DOUT signal assignment to port pins can be changed while no transmission is in progress. Receiver frame finished: This interrupt indicates that the receiver has completely finished a frame. Bit PSR.RFF becomes set at the end of the last stop bit. The DIN signal assignment to port pins can be changed while no reception is in progress. * * User's Manual USIC, UM_V0.2D5 19-121 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary * Universal Serial Interface Channel * * Synchronization break detection: This interrupt can be used in LIN networks to indicate the reception of the synchronization break symbol (at the beginning of a LIN frame). Receiver noise detection: This interrupt indicates that the input value at the sample point of a bit and at the two time quanta before are not identical. Format error: The bit value of the stop bit(s) is defined as 1 level for the ASC protocol. A format error is signalled if the sampled bit value of a stop bit is 0. 19.3.3.11 Data Transfer Interrupt Handling The data transfer interrupts indicate events related to ASC frame handling. * Transmit buffer interrupt TBI: Bit PSR.TBIF is set after the start of first data bit of a data word. This is the earliest point in time when a new data word can be written to TBUF. With this event, bit TCSRL.TDV is cleared and new data can be loaded to the transmit buffer. Transmit shift interrupt TSI: Bit PSR.TSIF is set after the start of the last data bit of a data word. Receiver start interrupt RSI: Bit PSR.RSIF is set after the sample point of the first data bit of a data word. Receiver interrupt RI and alternative interrupt AI: Bit PSR.RIF is set after the sampling point of the last data bit of a data word if this data word is not directly followed by a parity bit (parity generation disabled or not the last word of a data frame). If the data word is directly followed by a parity bit (last data word of a data frame and parity generation enabled), bit PSR.RIF is set after the sampling point of the parity bit if no parity error has been detected. If a parity error has been detected, bit PSR.AIF is set instead of bit PSR.RIF. The first data word of a data frame is indicated by RBUFSR.SOF = 1 for the received word. * * * 19.3.3.12 Protocol-Related Argument and Error The protocol-related argument (RBUFSR.PAR) and the protocol-related error (RBUFSR.PERR) are two flags that are assigned to each received data word in the corresponding receiver buffer status registers. In ASC mode, the received parity bit is monitored by the protocol-related argument and the result of the parity check by the protocol-related error indication (0 = received parity bit equal to calculated parity value). This information being elaborated only for the last received data word of each data frame, both bit positions are 0 for data words that are not the last data word of a data frame or if the parity generation is disabled. User's Manual USIC, UM_V0.2D5 19-122 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.3.3.13 Receive Buffer Handling If a receive FIFO buffer is available (CCFG.RB = 1) and enabled for data handling (RBCTRH.SIZE > 0), it is recommended to set RBCTRH.RCIM = 11B in ASC mode. This leads to an indication that the data word has been the first data word of a new data frame if bit OUTRH.RCI[0] = 1, a parity error is indicated by OUTRH.RCI[4] = 1, and the received parity bit value is given by OUTRH.RCI[3]. The standard receive buffer event and the alternative receive buffer event can be used for the following operations in RCI mode (RBCTRH.RNM = 1): * * A standard receive buffer event indicates that a data word can be read from OUTRL that has been received without parity error. An alternative receive buffer event indicates that a data word can be read from OUTRL that has been received with parity error. 19.3.3.14 Sync-Break Detection The receiver permanently checks the DIN signal for a certain number of consecutive bit times with 0 level. The number is given by the number of programmed bits per frame (SCTRH.FLE) plus 2 (in the case without parity) or plus 3 (in the case with parity). If a 0 level is detected at a sample point of a bit after this event has been found, bit PSR.SBD is set and additionally, a protocol interrupt can be generated (if enabled by PCRL.SBD = 1). The counting restarts from 0 each time a falling edge is found at input DIN. This feature can be used for the detection of a synchronization break for slave devices in a LIN bus system (the master doesn't check for sync break). For example, in a configuration for 8 data bits without parity generation, bit PCRL.SBD is set after at the next sample point at 0 level after 10 complete bit times have elapsed (representing the sample point of the 11th bit time since the first falling edge). User's Manual USIC, UM_V0.2D5 19-123 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.3.4 ASC Protocol Registers In ASC mode, the registers PCRH, PCRL and PSR handle ASC related information. 19.3.4.1 Protocol Control Registers The following PCRL/PCRH control bits or bit fields are available in ASC mode. Table 19-16 Signification of PCRL/PCRH Bits for ASC Bit CTR[0] Alias SMD Description Sample Mode This bit field defines the sample mode of the ASC receiver. The selected data input signal can be sampled only once per bit time or three times (in consecutive time quanta). When sampling three times, the bit value shifted in the receiver shift register is given by a majority decision among the three sampled values. 0B Only one sample is taken per bit time. The current input value is sampled. 1B Three samples are taken per bit time and a majority decision is made. Stop Bits This bit defines the number of stop bits in an ASC frame. 0B The number of stop bits is 1. The number of stop bits is 2. 1B Idle Detection Mode This bit defines if the idle detection is switched off or based on the frame length. 0B The bus idle detection is switched off and bits PSR.TXIDLE and PSR.RXIDLE are set automatically to enable data transfers without checking the inputs before. 1B The bus is considered as idle after a number of consecutive passive bit times defined by SCTRH.FLE plus 2 (in the case without parity bit) or plus 3 (in the case with parity bit). Synchronization Break Interrupt Enable This bit enables the generation of a protocol interrupt if a synchronization break is detected. The automatic detection is always active, so bit SBD can be set independently of SBIEN. The interrupt generation is disabled. 0B 1B The interrupt generation is enabled. CTR[1] STPB CTR[2] IDM CTR[3] SBIEN User's Manual USIC, UM_V0.2D5 19-124 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel Table 19-16 Signification of PCRL/PCRH Bits for ASC (cont'd) Bit CTR[4] Alias CDEN Description Collision Detection Enable This bit enables the reaction of a transmitter to the collision detection. 0B The collision detection is disabled. 1B If a collision is detected, the transmitter stops its data transmission, outputs a 1, sets bit PSR.COL and generates a protocol interrupt. In order to allow data transmission again, PSR.COL has to be cleared by SW. Receiver Noise Detection Interrupt Enable This bit enables the generation of a protocol interrupt if receiver noise is detected. The automatic detection is always active, so bit PSR.RNS can be set independently of PCRL.RNIEN. 0B The interrupt generation is disabled. The interrupt generation is enabled. 1B Format Error Interrupt Enable This bit enables the generation of a protocol interrupt if a format error is detected. The automatic detection is always active, so bits PSR.FER0/FER1 can be set independently of PCRL.FEIEN. 0B The interrupt generation is disabled. 1B The interrupt generation is enabled. Frame Finished Interrupt Enable This bit enables the generation of a protocol interrupt if the receiver or the transmitter reach the end of a frame. The automatic detection is always active, so bits PSR.RFF or PSR.TFF can be set independently of PCRL.FFIEN. 0B The interrupt generation is disabled. 1B The interrupt generation is enabled. Sample Point This bit field defines the sample point of the bit value. The sample point must not be located outside the programmed bit timing (PCRL.SP BRGL.DCTQ). CTR[5] RNIEN CTR[6] FEIEN CTR[7] FFIEN CTR [12:8] SP User's Manual USIC, UM_V0.2D5 19-125 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel Table 19-16 Signification of PCRL/PCRH Bits for ASC (cont'd) Bit CTR [15:13] Alias PL Description Pulse Length This bit field defines the length of a 0 data bit, counted in time quanta, starting with the time quantum 0 of each bit time. Each bit value that is a 0 can lead to a 0 pulse that is shorter than a bit time, e.g. for IrDA applications. The length of a bit time is not changed by PL, only the length of the 0 at the output signal. The pulse length must not be longer than the programmed bit timing (PCRH.PL BRGL.DCTQ). This bit field is only taken into account by the transmitter and is ignored by the receiver. 000B The pulse length is equal to the bit length (no shortened 0). 001B The pulse length of a 0 bit is 2 time quanta. 010B The pulse length of a 0 bit is 3 time quanta. ... 111B The pulse length of a 0 bit is 8 time quanta. Master Clock Enable This bit enables the generation of the master clock MCLK. 0B The MCLK generation is disabled and the MCLK signal is 0. 1B The MCLK generation is enabled. Reserved returns 0 if read; should be written with 0; CTR[31] MCLK other CTR[x] User's Manual USIC, UM_V0.2D5 19-126 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.3.4.2 Protocol Status Register PSR The following PSR status bits or bit fields are available in ASC mode. Please note that the bits in register PSR are not cleared by HW. The row marked PI indicates which status bit can generate a protocol interrupt. The general interrupt status flags are described in the general interrupt chapter. Table 19-17 Signification of PSR Bits for ASC Bit ST[0] Alias TXIDLE Description Transmission Idle This bit shows if the transmit line (DX1) has been idle. A frame transmission can only be started if TXIDLE is set. 0B The transmitter line has not yet been idle. 1B The transmitter line has been idle and frame transmission is possible. PI? n ST[1] RXIDLE Reception Idle n This bit shows if the receive line (DX0) has been idle. A frame reception can only be started if RXIDLE is set. 0B The receiver line has not yet been idle. 1B The receiver line has been idle and frame reception is possible. SBD Synchronization Break Detected y This bit is set if a programmed number of consecutive bit values with level 0 has been detected (called synchronization break, e.g. in a LIN bus system). A synchronization break has not yet been detected. 0B 1B A synchronization break has been detected. Collision Detected y This bit is set if a collision has been detected (with PCRL.CDEN = 1). 0B A collision has not yet been detected and frame transmission is possible. 1B A collision has been detected and frame transmission is not possible. Receiver Noise Detected This bit is set if receiver noise has been detected. 0B Receiver noise has not been detected. 1B Receiver noise has been detected. y ST[2] ST[3] COL ST[4] RNS User's Manual USIC, UM_V0.2D5 19-127 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel Table 19-17 Signification of PSR Bits for ASC (cont'd) Bit ST[5] Alias FER0 Description PI? Format Error in Stop Bit 0 y This bit is set if a 0 has been sampled in the stop bit 0 (called format error 0). 0B A format error 0 has not been detected. 1B A format error 0 has been detected. Format Error in Stop Bit 1 y This bit is set if a 0 has been sampled in the stop bit 1 (called format error 1). A format error 1 has not been detected. 0B 1B A format error 1 has been detected. Receive Frame Finished This bit is set if the receiver has finished the last stop bit. 0B The received frame is not yet finished. 1B The received frame is finished. Transmitter Frame Finished This bit is set if the transmitter has finished the last stop bit. 0B The transmitter frame is not yet finished. 1B The transmitter frame is finished. General Interrupt Flags y ST[6] FER1 ST[7] RFF ST[8] TFF y PSR [15:10] n User's Manual USIC, UM_V0.2D5 19-128 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.3.5 Hardware LIN Support The Local Interconnect Network (LIN) data exchange protocol contains several symbols that can all be handled in ASC mode. Each single LIN symbol represents a complete ASC frame. The LIN bus is a master-slave bus system with a single master and multiple slaves (for the exact definition please refer to the official LIN specification). In order to support the LIN protocol, bit TCSRL.FLEMD = 1 should be set for the master. For slave devices, it can be cleared and the fixed number of 8 data bits has to be set (SCTRH.FLE = 7). For both, master and slave devices, the parity generation has to be switched off (CCR.PM = 00B) and transfers take place with LSB first (SCTRL.SDIR = 0) and 1 stop bit (PCRL.STPB = 0). A complete LIN frame contains the following symbols: * Synchronization break: The master sends a synchronization break to signal the beginning of a new frame. It contains at least 13 consecutive bit times at 0 level, followed by at least one bit time at 1 level (corresponding to 1 stop bit). Therefore, TBUF11 (or IN11) has to be written with 0 (leading to a frame with SOF followed by 12 data bits at 0 level). A slave device shall detect 11 consecutive bit times at 0 level, which done by the synchronization break detection. Bit PSR.SBD is set if such an event is detected and a protocol interrupt can be generated. Additionally, the received data value of 0 appears in the receive buffer and a format error is signaled. If the baud rate of the slave has to be adapted to the master, the baud rate measurement has to be enabled for falling edges by setting BRGL.TMEN = 1, DX0CR.CM = 10H and DX1CR.CM = 00H before the next symbol starts. Synchronization byte: The master sends this symbol after writing the data value 55H to TBUF07 (or IN07). A slave device can either receive this symbol without any further action (and can discard it) or it can use the falling edges for baud rate measurement. Bit PSR.TSIF = 1 (with optionally the corresponding interrupt) indicates the detection of a falling edge and the capturing of the elapsed time since the last falling edge in BRGH.PDIV. Valid captured values can be read out after the second, third, fourth and fifth activation of TSIF. After the fifth activation of TSIF within this symbol, the baud rate detection has to be disabled (BRGL.TMEN = 0) and BRGH.PDIV can be programmed with the formerly captured value divided by twice the number of time quanta per bit (assuming BRGL.PCTQ = 00B). Other symbols: The other symbols of a LIN frame can be handled with ASC data frames without specific actions. * * If LIN frames should be sent out on a frame base by the LIN master, the input DX2 can be connected to external timers to trigger the transmit actions (e.g. the synchronization break symbol has been prepared but is started if a trigger occurs). Please note that during the baud rate measurement of the ASC receiver, no transmission can take place by the ASC transmitter of the same USIC channel. User's Manual USIC, UM_V0.2D5 19-129 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.4 Synchronous Serial Channel (SSC) The synchronous serial channel SSC covers the data transfer function of an SPI-like module. It can handle reception and transmission of synchronous data frames between a device operating in master mode and at least one device in slave mode. The SSC mode is selected by CCR.MODE = 0001B with CCFG.SSC = 1 (SSC mode is available). This chapter contains the following sections: * * * * * * Signal description (see Section 19.4.1) General SSC issues (see Section 19.4.2) Master mode operation (see Section 19.4.3) Slave mode operation (see Section 19.4.4) Protocol registers (see Section 19.4.5) Timing considerations (see Section 19.4.6) 19.4.1 Signal Description A synchronous SSC data transfer is characterized by a simultaneous transfer of a shift clock signal together with the transmit and/or receive data signal(s) to determine when the data is valid (definition of transmit and sample point). SSC communication master DOUT TBUF DIN RBUF baud rate generator SELOx slave sel. generator slave select DX0 SCLKOUT shift clock master transmit slave receive master receive slave transmit SSC communication slave DIN DX0 DOUT TBUF SCLKIN DX1 SELIN DX2 RBUF fsys (master) Figure 19-30 SSC Signals for Full-Duplex Communication fsys (slave) SSC_signals User's Manual USIC, UM_V0.2D5 19-130 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel In order to explicitly indicate the start and the end of a data transfer and to address more than one slave devices individually, the SSC module supports the handling of slave select signals. They are optional and are not necessarily needed for SSC data transfers. The SSC module supports up to 8 different slave select output signals for master mode operation (named SELOx, with x = 0-7) and 1 slave select input SELIN for slave mode. In most applications, the slave select signals are active low. A device operating in master mode controls the start and end of a data frame, as well as the generation of the shift clock and slave select signals. This comprises the baud rate setting for the shift clock and the delays between the shift clock and the slave select output signals. If several SSC modules are connected together, there can be only one SSC master at a time, but several slaves. Slave devices receive the shift clock and optionally a slave select signal(s). For the programming of the input stages DX0, DX1, and DX2 please refer to Section 19.2.5. Table 19-18 SSC Communication Signals SSC Mode master Receive Data Transmit Data Shift Clock output SCLKOUT Slave Select(s) output(s) SELOx MRST1), MTSR2), input DIN, output DOUT handled by DX0 MTSR, MRST, input DIN, output DOUT handled by DX0 slave input SCLKIN, input SELIN, handled by DX1 handled by DX2 1) 2) MRST = master receive slave transmit, also known as MISO = master in slave out MTSR = master transmit slave receive, also known as MOSI = master out slave in shift clock transmit data receive data slave select D0 D1 Dn D0 D1 Dn D0 D1 Dn D0 D1 Dn data word 0 data frame data word x SSC_standard Figure 19-31 4-Wire SSC Standard Communication Signals User's Manual USIC, UM_V0.2D5 19-131 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.4.1.1 Transmit and Receive Data Signals In half-duplex mode, a single data line is used, either for data transfer from the master to a slave or from a slave to the master. In this case, MRST and MTSR are connected together, one signal as input, the other one as output, depending on the data direction. The user SW has to take care about the data direction to avoid data collision (e.g. by preparing dummy data of all 1s for transmission in case of a wired AND connection with open-drain drivers or by enabling/disabling push/pull output drivers). In full-duplex mode, data transfers take place in parallel between the master device and a slave device via two independent data signals MTSR and MRST, as shown in Figure 19-30. The receive data input signal DIN is handled by the input stage DX0. In master mode (referring to MRST) as well as in slave mode (referring to MTSR), the data input signal DIN is taken from an input pin. The signal polarity of DOUT (data output) with respect to the data bit value can be configured in block DOCFG (data output configuration) by bit field SCTRL.DOCFG. MRST master mode DIN MTSR slave mode data shift unit DOCFG SSC_datasignals MTSR master mode input stage DX0 DOUT MRST slave mode Figure 19-32 SSC Data Signals User's Manual USIC, UM_V0.2D5 19-132 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.4.1.2 Shift Clock Signals The shift clock signal is handled by the input stage DX1. In slave mode, the signal SCLKIN is received from an external master, so the DX1 stage has to be connected to an input pin. The input stage can invert the received input signal to adapt to the polarity of SCLKIN to the function of the data shift unit (data transmission on rising edges, data reception on falling edges). In master mode, the shift clock is generated by the internal baud rate generator. The output signal SCLK of the baud rate generator is taken as shift clock input for the data shift unit. The internal signal SCLK is made available for external slave devices by signal SCLKOUT. used in SSC slave mode SCLKIN used in SSC master mode delay of 1/2 bit time SCLKOUT SCLKCFG input stage DX1 SCLK data shift unit transfer control logic baud rate generator SSC_shiftclock Figure 19-33 SSC Shift Clock Signals Due to the multitude of different SSC applications, in master mode, there are different ways to configure the shift clock output signal SCLKOUT with respect to SCLK. This is done in the block SCLKCFG (shift clock configuration) by bit field BRGH.SCLKCFG, allowing 4 possible settings, as shown in Figure 19-34. * No delay, no polarity inversion (SCLKCFG = 00B, SCLKOUT equals SCLK): The inactive level of SCLKOUT is 0, while no data frame is transferred. The first data bit of a new data frame is transmitted with the first rising edge of SCLKOUT and the first data bit is received in with the first falling edge of SCLKOUT. The last data bit of a data frame is transmitted with the last rising clock edge of SCLKOUT and the last data bit is received in with the last falling edge of SCLKOUT. This setting can be used in master and in slave mode. It corresponds to the behavior of the internal data shift unit. No delay, polarity inversion (SCLKCFG = 01B): The inactive level of SCLKOUT is 1, while no data frame is transferred. The first data 19-133 V1.0, 2007-06 * User's Manual USIC, UM_V0.2D5 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel * * bit of a new data frame is transmitted with the first falling clock edge of SCLKOUT and the first data bit is received with the first rising edge of SCLKOUT. The last data bit of a data frame is transmitted with the last falling edge of SCLKOUT and the last data bit is received with the last rising edge of SCLKOUT. This setting can be used in master and in slave mode. SCLKOUT is delayed by 1/2 shift clock period, no polarity inversion (SCLKCFG = 10B): The inactive level of SCLKOUT is 0, while no data frame is transferred. The first data bit of a new data frame is transmitted 1/2 shift clock period before the first rising clock edge of SCLKOUT. Due to the delay, the next data bits seem to be transmitted with the falling edges of SCLKOUT. The last data bit of a data frame is transmitted 1/2 period of SCLKOUT before the last rising clock edge of SCLKOUT. The first data bit is received 1/2 shift clock period before the first falling edge of SCLKOUT. Due to the delay, the next data bits seem to be received with the rising edges of SCLKOUT. The last data bit is received 1/2 period of SCLKOUT before the last falling clock edge of SCLKOUT. This setting can be used only in master mode and not in slave mode (the connected slave has to provide the first data bit before the first SCLKOUT edge, e.g. as soon as it is addressed by its slave select). SCLKOUT is delayed by 1/2 shift clock period, polarity inversion (SCLKCFG = 11B): The inactive level of SCLKOUT is 1, while no data frame is transferred. The first data bit of a new data frame is transmitted 1/2 shift clock period before the first falling clock edge of SCLKOUT. Due to the delay, the next data bits seem to be transmitted with the rising edges of SCLKOUT. The last data bit of a data frame is transmitted 1/2 period of SCLKOUT before the last falling clock edge of SCLKOUT. The first data bit is received 1/2 shift clock period before the first rising edge of SCLKOUT. Due to the delay, the next data bits seem to be received with the falling edges of SCLKOUT. The last data bit is received 1/2 period of SCLKOUT before the last rising clock edge of SCLKOUT. This setting can be used only in master mode and not in slave mode (the connected slave has to provide the first data bit before the first SCLKOUT edge, e.g. as soon as it is addressed by its slave select). User's Manual USIC, UM_V0.2D5 19-134 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel data bit x transmitted x = 1..n 1 2 n bit 1 SCLKCFG = 00 SCLKCFG = 01 SCLKCFG = 10 SCLKCFG = 11 bit n data bit x received x = 1..n 1 2 n SSC_SCLKCFG Figure 19-34 SCLKOUT Configuration in SSC Master Mode Note: If a configuration with delay is selected and a slave select line is used, the slave select delays have to be set up accordingly. User's Manual USIC, UM_V0.2D5 19-135 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.4.1.3 Slave Select Signals The slave select signal is handled by the input stage DX2. In slave mode, the input signal SELIN is received from an external master via an input pin. The input stage can invert the received input signal to adapt the polarity of signal SELIN to the function of the data shift unit (the module internal signals are considered as high active, so a data transfer is only possible while the slave select input of the data shift unit is at 1-level, otherwise, shift clock pulses are ignored and do not lead to data transfers). If an input signal SELIN is low active, it should be inverted in the DX2 input stage. In master mode, a master slave select signal MSLS is generated by the internal slave select generator. In order to address different external slave devices independently, the internal MSLS signal is made available externally via up to 8 SELOx output signals that can be configured by the block SELCFG (select configuration). used in SSC slave mode SELIN used in SSC master mode SELOx x = 0..7 ... SELCFG input stage DX2 MSLS data shift unit transfer control logic slave select generator SSC_slaveselect Figure 19-35 SSC Slave Select Signals The control of the SELCFG block is based on protocol specific bits and bit fields in the protocol control register parts PCRL and PCRH. For the generation of the MSLS signal please refer to Section 19.4.3.2. * * * * PCRL.SELCTR to chose between direct and coded select mode PCRL.SELINV to invert the SELOx outputs PCRH.SELO[7:0] as individual value for each SELOx line Direct Select Mode (SELCTR = 1): Each SELOx line (with x = 0-7) can be directly connected to an external slave device. If bit x in bit field SELO is 0, the SELOx output is permanently inactive. A SELOx output becomes active while the internal signal MSLS is active (see Section 19.4.3.2) and bit x in bit field SELO is 1. Several external slave devices can 19-136 V1.0, 2007-06 The SELCFG block supports the following configurations of the SELOx output signals: User's Manual USIC, UM_V0.2D5 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel * be addressed in parallel if more than one bit in bit field SELO are set during a data frame. The number of external slave devices that can be addressed individually is limited to the number of available SELOx outputs. Coded Select Mode (SELCTR = 0): The SELOx lines (with x = 1-7) can be used as addresses for an external address decoder to increase the number of external slave devices. These lines only change with the start of a new data frame and have no other relation to MSLS. Signal SELO0 can be used as enable signal for the external address decoder. It is active while MSLS is active (during a data frame) and bit 0 in bit field SELO is 1. Furthermore, in coded select mode, this output line is delayed by one cycle of fSYS compared to MSLS to allow the other SELOx lines to stabilize before enabling the address decoder. User's Manual USIC, UM_V0.2D5 19-137 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.4.2 Operating the SSC This chapter contains SSC issues, that are of general interest and not directly linked to either master mode or slave mode. 19.4.2.1 Automatic Shadow Mechanism The contents of the baud rate control registers BRGL and BRGH, bit field SCTRH.FLE as well as the protocol control registers PCRL and PCRH are internally kept constant while a data frame is transferred (= while MSLS is active) by an automatic shadow mechanism. The registers can be programmed all the time with new settings that are taken into account for the next data frame. During a data frame, the applied (shadowed) setting is not changed, although new values have been written after the start of the data frame. Bit fields SCTRH.WLE and SCTRL.SDIR are shadowed automatically with the start of each data word. As a result, a data frame can consist of data words with a different length. It is recommended to change SCTRL.SDIR only when no data frame is running to avoid interference between HW and SW. Please note that the starting point of a data word are different for a transmitter (first bit transmitted) and a receiver (first bit received). In order to ensure correct handling, it is recommended to refer to the receive start interrupt RSI before modifying SCTRL.WLE. If TCSRL.WLEMD = 1, it is recommended to update TCSRL and TBUFxx after the receiver start interrupt has been generated. 19.4.2.2 Mode Control Behavior In SSC mode, the following kernel modes are supported: * * Run Mode 0/1: Behavior as programmed, no impact on data transfers. Stop Mode 0/1: The contents of the transmit buffer is considered as not valid for transmission. Although being considered as 0, bit TCSRL.TDV it is not modified by the stop mode condition. In master mode, a currently running word transfer is finished normally, but no new data word is started (the stop condition is not considered as end-of-frame condition). In slave mode, a currently running word transfer is finished normally. Passive data will be sent out instead of a valid data word if a data word transfer is started by the external master while the slave device is in stop mode. In order to avoid passive slave transmit data, it is recommended not to program stop mode for an SSC slave device if the master device does not respect the slave device's stop mode. User's Manual USIC, UM_V0.2D5 19-138 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.4.2.3 Disabling SSC Mode In order to disable SSC mode without any data corruption, the receiver and the transmitter have to be both idle. This is ensured by requesting Stop Mode 1 in register KSCFG. After Stop Mode 1 has been acknowledged by KSCFG.ACK = 1, the SSC mode can be disabled. 19.4.2.4 Data Frame Control An SSC data frame can consist of several consecutive data words that may be separated by an inter-word delay. Without inter-word delay, the data words seem to form a longer data word, being equivalent to a data frame. The length of the data words are most commonly identical within a data frame, but may also differ from one word to another. The data word length information (defined by SCTRH.WLE) is evaluated for each new data word, whereas the frame length information (defined by SCTRH.FLE) is evaluated at the beginning at each start of a new frame. The length of an SSC data frame can be defined in two different ways: * By the number of bits per frame: If the number of bits per data frame is defined (frame length FLE), a slave select signal is not necessarily required to indicate the start and the end of a data frame. If the programmed number of bits per frame is reached within a data word, the frame is considered as finished and remaining data bits in the last data word are ignored and are not transferred. This method can be applied for data frames with up to 63 data bits. By the slave select signal: If the number of bits per data frame is not known, the start/end information of a data frame is given by a slave select signal. If a deactivation of the slave select signal is detected within a data word, the frame is considered as finished and remaining data bits in the last data word are ignored and are not transferred. This method has to be applied for frames with more than 63 data bits (programming limit of FLE). The advantage of slave select signals is the clearly defined start and end condition of data frames in a data stream. Furthermore, slave select signals allow to address slave devices individually. * 19.4.2.5 Parity Mode Parity generation is not supported in SSC mode and bit field CCR.PM = 00B has to be programmed. 19.4.2.6 Transfer Mode In SSC mode, bit field SCTRL.TRM = 01B has to be programmed to allow data transfers. Setting SCTRL.TRM = 00B disables and stops the data transfer immediately. User's Manual USIC, UM_V0.2D5 19-139 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.4.2.7 Data Transfer Interrupt Handling The data transfer interrupts indicate events related to SSC frame handling. * * * Transmit buffer interrupt TBI: Bit PSR.TBIF is set after the start of first data bit of a data word. Transmit shift interrupt TSI: Bit PSR.TSIF is set after the start of the last data bit of a data word. Receiver start interrupt RSI: Bit PSR.RSIF is set after the reception of the first data bit of a data word. With this event, bit TCSRL.TDV is cleared and new data can be loaded to the transmit buffer. Receiver interrupt RI: Bit PSR.RIF is set at after the reception of the last data bit of a data word. Bit RBUFSR.SOF indicates whether the received data word has been the first data word of a new data frame. Alternative interrupt AI: In SSC mode, this interrupt is not used. * * 19.4.2.8 Protocol-Related Argument and Error The protocol-related argument (PAR) and the protocol-related error (PERR) are two flags that are assigned to each received data word in the corresponding receiver buffer status registers. In SSC mode, these flags are always 0 (parity handling must be disabled). 19.4.2.9 Receive Buffer Handling If a receive FIFO buffer is available (CCFG.RB = 1) and enabled for data handling (RBCTRH.SIZE > 0), it is recommended to set RBCTRH.RCIM = 01B in SSC mode. This leads to an indication that the data word has been the first data word of a new data frame if bit OUTRH.RCI[4] = 1, and the word length of the received data is given by OUTRH.RCI[3:0]. The standard receive buffer event and the alternative receive buffer event can be used for the following operation in RCI mode (RBCTRH.RNM = 1): * * A standard receive buffer event indicates that a data word can be read from OUTRL that has not been the first word of a data frame. An alternative receive buffer event indicates that the first data word of a new data frame can be read from OUTRL. User's Manual USIC, UM_V0.2D5 19-140 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.4.3 * Operating the SSC in Master Mode In order to operate the SSC in master mode, the following issues have to be considered: Select SSC mode: It is recommended to configure all parameters of the SSC that do not change during run time while CCR.MODE = 0000B. Bit field SCTRL.TRM = 01B has to be programmed. The configuration of the input stages has to be done while CCR.MODE = 0000B to avoid unintended edges of the input signals and the SSC mode can be enabled by CCR.MODE = 0001B afterwards. Pin connections: Establish a connection of input stage DX0 with the selected receive data input pin (DIN) with DX0CR.INSW = 1 and configure a transmit data output pin (DOUT). Baud rate generation: The desired baud rate setting has to be selected, comprising the fractional divider and the baud rate generator. Bit DX1CR.INSW = 0 has to be programmed to use the baud rate generator output SCLK directly as input for the data shift unit. Configure a shift clock output pin (signal SCLKOUT). Slave select generation: The slave select delay generation has to be enabled by setting PCRL.MSLSEN = 1 and the programming of the time quanta counter setting. Bit DX2CR.INSW = 0 has to be programmed to use the slave select generator output MSLS as input for the data shift unit. Configure slave select output pins (signals SELOx) if needed. Data format configuration: The word length, the frame length, and the shift direction have to be set up according to the application requirements by programming the registers SCTRL and SCTRH. * * * * Note: The USIC can only receive in master mode if it is transmitting, because the master frame handling refers to bit TDV of the transmitter part. 19.4.3.1 Baud Rate Generation The baud rate (determining the length of one data bit) of the SSC is defined by the frequency of the SCLK signal (one period of fSCLK represents one data bit). The SSC baud rate generation does not imply any time quanta counter. In a standard SSC application, the phase relation between the optional MCLK output signal and SCLK is not relevant and can be disabled (BRGL.PPPEN = 0). In this case, the SCLK signal directly derives from the protocol input frequency fPIN. In the exceptional case that a fixed phase relation between the MCLK signal and SCLK is required (e.g. when using MCLK as clock reference for external devices), the additional divider by 2 stage has to be taken into account (BRGL.PPPEN = 1). User's Manual USIC, UM_V0.2D5 19-141 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel The adjustable divider factor is defined by bit field BRGH.PDIV. (19.8) f 1 PIN --------- x ----------------------PDIV + 1 2 = f PIN 1 ----------- x ---------------------- 2 x 2 PDIV + 1 if if PPPEN = 0 PPPEN = 1 f SCLK 19.4.3.2 MSLS Generation The slave select signals indicate the start and the end of a data frame and are also used by the communication master to individually select the desired slave device. A slave select output of the communication master becomes active a programmable time before a data part of the frame is started (leading delay Tld), necessary to prepare the slave device for the following communication. After the transfer of a data part of the frame, it becomes inactive again a programmable time after the end of the last bit (trailing delay Ttd) to respect the slave hold time requirements. If data frames are transferred back-toback one after the other, the minimum time between the deactivation of the slave select and the next activation of a slave select is programmable (next-frame delay Tnf). If a data frame consists of more than one data word, an optional delay between the data words can also be programmed (inter-word delay Tiw). data word 0 SCLK transmit data receive data Tld active data frame data word 1 D0 D1 Dn D0 D1 Dn D0 D1 Dn Tiw D0 D1 Dn Ttd Tnf MSLS inactive SSC_MSLS Figure 19-36 MSLS Generation in SSC Master Mode User's Manual USIC, UM_V0.2D5 19-142 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel In SSC master mode, the slave select delays are defined as follows: * Leading delay Tld: The leading delay starts if valid data is available for transmission. The internal signal MSLS becomes active with the start of the leading delay. The first shift clock edge (rising edge) of SCLK is generated by the baud rate generator after the leading delay has elapsed. Trailing delay Ttd The trailing delay starts at the end of the last SCLK cycle of a data frame. The internal signal MSLS becomes inactive with the end of the trailing delay. Inter-word delay Tiw: This delay is optional and can be enabled/disabled by PCRH.TIWEN. If the interword delay is disabled (TIWEN = 0), the last data bit of a data word is directly followed by the first data bit of the next data word of the same data frame. If enabled (TIWEN = 1), the inter-word delay starts at the end of the last SCLK cycle of a data word. The first SCLK cycle of the following data word of the same data frame is started when the inter-word delay has elapsed. During this time, no shift clock pulses are generated and signal MSLS stays active. The communication partner has time to "digest" the previous data word or to prepare for the next one. Next-frame delay Tnf: The next-frame delay starts at the end of the trailing delay. During this time, no shift clock pulses are generated and signal MSLS stays inactive. A frame is considered as finished after the next-frame delay has elapsed. * * * 19.4.3.3 Automatic Slave Select Update If the number of bits per SSC frame and the word length are defined by bit fields SCTRH.FLE and SCTRH.WLE, the transmit control information TCI can be used to update the slave select setting PCRH.CTR[23:16] to control the SELOx select outputs. The automatic update mechanism is enabled by TCSRL.SELMD = 1 (bits TCSRL.WLEMD, FLEMD, and WAMD have to be cleared). In this case, the TCI of the first data word of a frame defines the slave select setting of the complete frame due to the automatic shadow mechanism (see Section 19.3.3.6). User's Manual USIC, UM_V0.2D5 19-143 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.4.3.4 Slave Select Delay Generation The slave select delay generation is based on time quanta. The length of a time quantum (defined by the period of the fCTQIN) and the number of time quanta per delay can be programmed. In standard SSC applications, the leading delay Tld and the trailing delay Ttd are mainly used to ensure stability on the input and output lines as well as to respect setup and hold times of the input stages. These two delays have the same length (in most cases shorter than a bit time) and can be programmed with the same set of bit fields. * * * BRGL.CTQSEL to define the input frequency fCTQIN for the time quanta generation for Tld and Ttd BRGL.PCTQ to define the length of a time quantum (division of fCTQIN by 1, 2, 3, or 4) for Tld and Ttd BRGL.DCTQ to define the number of time quanta for the delay generation for Tld and Ttd The inter-word delay Tiw and the next-frame delay Tnf are used to handle received data or to prepare data for the next word or frame. These two delays have the same length (in most cases in the bit time range) and can be programmed with a second, independent set of bit fields. * * PCRL.CTQSEL1 to define the input frequency fCTQIN for the time quanta generation for Tnf and Tiw PCRL.PCTQ1 to define the length of a time quantum (division of fCTQIN by 1, 2, 3, or 4) for Tnf and Tiw PCRL.DCTQ1 to define the number of time quanta for the delay generation for Tnf and Tiw PCRH.TIWEN to enable/disable the inter-word delay Tiw * * Each delay depends on the length of a time quantum and the programmed number of time quanta given by the bit fields CTQSEL/CTQSEL1, PCTQ/DCTQ and PCTQ1/ DCTQ1 (the coding of CTQSEL1 is similar to CTQSEL, etc.). To provide a high flexibility in programming the delay length, the input frequencies can be selected between several possibilities (e.g. based on bit times or on the faster inputs of the protocol-related divider). The delay times are defined as follows: ( PCTQ + 1 ) x ( DCTQ + 1 ) T ld = T td = ------------------------------------------------------------------f CTQIN ( PCTQ1 + 1 ) x ( DCTQ1 + 1 ) T iw = T nf = -------------------------------------------------------------------------f CTQIN (19.9) User's Manual USIC, UM_V0.2D5 19-144 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.4.3.5 Protocol Interrupt Events The following protocol-related events generated in SSC mode and can lead to a protocol interrupt. They are related to the start and the end of a data frame. After the start of a data frame a new setting could be programmed for the next data frame and after the end of a data frame the SSC connections to pins can be changed. Please note that the bits in register PSR are not all automatically cleared by HW and have to be cleared by SW in order to monitor new incoming events. * MSLS Interrupt: This interrupt indicates in master mode (MSLS generation enabled) that a data frame has started (activation of MSLS) and has been finished (deactivation of MSLS). Any change of the internal MSLS signal sets bit PSR.MSLSEV and additionally, a protocol interrupt can be generated if PCRL.MSLSIEN = 1. The actual state of the internal MSLS signal can be read out at PSR.MSLS to take appropriate actions when this interrupt has been detected. DX2T Interrupt: This interrupt monitors edges of the input signal of the DX2 stage (although this signal is not used as slave select input for data transfers). A programmable edge detection for the DX2 input signal sets bit PSR.DX2TEV and additionally, a protocol interrupt can be generated if PCRL.DX2TIEN = 1. The actual state of the selected input signal can be read out at PSR.DX2S to take appropriate actions when this interrupt has been detected. * User's Manual USIC, UM_V0.2D5 19-145 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.4.3.6 End of Frame Control The information about the frame length is required for the MSLS generator of the master device. In addition to the mechanism based on the number of bits per frame (selected with SCTRH.FLE<63), the following alternative mechanisms for end of frame handling are supported. It is recommended to set SCTRH.FLE = 63 (if several end of frame mechanisms are activated in parallel, the first end condition being found finishes the frame). * SW-based start of frame indication TCSRL.SOF: This mechanism can be used if SW handles the TBUF data without data FIFO. If bit SOF is set, a valid contents of TBUF is considered as first word of a new frame. Bit SOF has to be set before the content of TBUF is transferred to the transmit shift register, so it is recommended to write it before writing data to TBUF. A current data word transfer is finished completely and the slave select delays Ttd and Tnf are applied before starting a new data frame with Tld and the contents of TBUF. For SW-handling of bit SOF, bit TCSRL.WLEMD = 0 has to be programmed. In this case, all TBUF[31:0] address locations show an identical behavior (TCI not taken into account for data handling). SW-based end of frame indication TCSRL.EOF: This mechanism can be used if SW handles the TBUF data without data FIFO. If bit EOF is set, a valid contents of TBUF is considered as last word of a new frame. Bit EOF has to be set before the content of TBUF is transferred to the transmit shift register, so it is recommended to write it before writing data to TBUF. The data word in TBUF is sent out completely and the slave select delays Ttd and Tnf are applied. A new data frame can start with Tld with the next valid TBUF value. For SW-handling of bit EOF, bit TCSRL.WLEMD = 0 has to be programmed. In this case, all TBUF[31:0] address locations show an identical behavior (TCI not taken into account for data handling). SW-based address related end of frame handling: This mechanism can be used if SW handles the TBUF data without data FIFO. If bit TCSRL.WLEMD = 1, the address of the written TBUF[31:0] is used as transmit control information TCI[4:0] to update SCTRH.WLE (= TCI[3:0]) and TCSRL.EOF (= TCI[4]) for each data word. The written TBUF[31:0] address location defines the word length and the end of a frame (locations TBUF[31:16] lead to a frame end). For example, writing transmit data to TBUF[07] results in a data word of 8 bit length without finishing the frame, whereas writing transmit data to TBUF[31] leads to a data word length of 16 bits, followed by Ttd, the deactivation of MSLS and Tnf. If TCSRL.WLEMD = 1, bits TCSRL.EOF and SOF, as well as SCTRH.WLE must not be written by SW after writing data to a TBUF location. Furthermore, it is recommended to clear bits TCSRL.SELMD, FLEMD and WAMD. FIFO-based address related end of frame handling: This mechanism can be used if a data FIFO is used to store the transmit data. The general behavior is similar to the SW-based address related end of frame handling, 19-146 V1.0, 2007-06 * * * User's Manual USIC, UM_V0.2D5 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel * * except that transmit data is not written to the locations TBUF[31:0], but to the FIFO input locations IN[31:0] instead. In this case, SW must not write to any of the TBUF locations. TBUF related end of frame handling: If bit PCRL.FEM = 0, an end of frame is assumed if the transmit buffer TBUF does not contain valid transmit data at the end of a data word transmission (TCSRL.TDV = 0 or in Stop Mode). In this case, the SW has to take care that TBUF does not run empty during a data frame in Run Mode. If bit PCRL.FEM = 1, signal MSLS stays active while the transmit buffer is waiting for new data (TCSRL.TDV = 1 again) or until Stop Mode is left. Explicit end of frame by SW: The SW can explicitly stop a frame by clearing bit PSR.MSLS by writing a 1 to the related bit position in register PSCR. This write action immediately clears bit PSR.MSLS, whereas the internal MSLS signal becomes inactive after finishing a currently running word transfer and respecting the slave select delays Ttd and Tnf. User's Manual USIC, UM_V0.2D5 19-147 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.4.4 * Operating the SSC in Slave Mode In order to operate the SSC in slave mode, the following issues have to be considered: Select SSC mode: It is recommended to configure all parameters of the SSC that do not change during run time while CCR.MODE = 0000B. Bit field SCTRL.TRM = 01B has to be programmed. The configuration of the input stages has to be done while CCR.MODE = 0000B to avoid unintended edges of the input signals and the SSC mode can be enabled afterwards by CCR.MODE = 0001B. Pin connections: Establish a connection of input stage DX0 with the selected receive data input pin (signal DIN) with DX0CR.INSW = 1 and configure a transmit data output pin (signal DOUT). Establish a connection of input stage DX1 with the selected shift clock input pin (signal SCLKIN) with DX1CR.INSW = 1. Establish a connection of input stage DX2 with the selected slave select input pin (signal SELIN) with DX2CR.INSW = 1. If no slave select input signal is used, the DX2 stage has to deliver a 1-level to the data shift unit to allow data reception and transmission. If a slave device is not selected (DX2 stage delivers a 0 to the data shift unit) and a shift clock pulse are received, the incoming data is not received and the DOUT signal outputs the passive data level defined by SCTRL.PDL. Baud rate generation: The baud rate generator is not needed and can be switched off by the fractional divider. Slave select generation: The slave select delay generation is not needed and can be switched off. The bits and bit fields MSLSEN, SELCTR, SELINV, CTQSEL1, PCTQ1, DCTQ1, MSLSIEN, SELO[7:0], and TIWEN in registers PCRL/PCRH are not necessary and can be programmed to 0. * * * 19.4.4.1 Protocol Interrupts The following protocol-related events generated in SSC mode and can lead to a protocol interrupt. They are related to the start and the end of a data frame. After the start of a data frame a new setting could be programmed for the next data frame and after the end of a data frame the SSC connections to pins can be changed. Please note that the bits in register PSR are not all automatically cleared by HW and have to be cleared by SW in order to monitor new incoming events. * * MSLS event: The MSLS generation being switched off, this event is not available. DX2T event: The slave select input signal SELIN is handled by the DX2 stage and the edges of the selected signal can generate a protocol interrupt. This interrupt allows to indicate 19-148 V1.0, 2007-06 User's Manual USIC, UM_V0.2D5 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel that a data frame has started and/or that a data frame has been completely finished. A programmable edge detection for the DX2 input signal activates DX2T, sets bit PSR.DX2TEV and additionally, a protocol interrupt can be generated if PCRL.DX2TIEN = 1. The actual state of the selected input signal can be read out at PSR.DX2S to take appropriate actions when this interrupt has been detected. 19.4.4.2 End of Frame Control In slave mode, the following possibilities exist to determine the frame length. The slave device either has to refer to an external slave select signal, or to the number of received data bits. * Frame length known in advance by the slave device, no slave select: In this case bit field SCTRH.FLE can be programmed to the known value (if it does not exceed 63 bits). A currently running data word transfer is considered as finished if the programmed frame length is reached. Frame length not known by the slave, no slave select: In this case, the slave device's SW has to decide on data word base if a frame is finished. Bit field SCTRH.FLE can be either programmed to the word length SCTRH.WLE, or to its maximum value to disable the slave internal frame length evaluation by counting received bits. Slave device addressed via slave select signal SELIN: If the slave device is addressed by a slave select signal delivered by the communication master, the frame start and end information are given by this signal. In this case, bit field SCTRH.FLE should be programmed to its maximum value to disable the slave internal frame length evaluation. * * User's Manual USIC, UM_V0.2D5 19-149 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.4.5 SSC Protocol Registers In SSC mode, the bits in the registers PCRL, PCRH and PSR handle SSC related information. 19.4.5.1 Protocol Control Registers The following PCRL/PCRH control bits or bit fields are available in SSC mode. Table 19-19 Signification of PCRL/PCRH Bits for SSC Field CTR[0] Alias Description MSLSEN MSLS Enable This bit enables/disables the generation of the master slave select signal MSLS. If the SSC is a transfer slave, the SLS information is read from a pin and the internal generation is not needed. If the SSC is a transfer master, it has to provide the MSLS signal. 0B The MSLS generation is disabled (MSLS = 0). This is the setting for SSC slave mode. 1B The MSLS generation is enabled. This is the setting for SSC master mode. SELCTR Select Control This bit selects the operating mode for the SELO[7:0] outputs. The coded select mode is enabled. 0B 1B The direct select mode is enabled. SELINV Select Inversion This bit defines if the polarity of the SELO[7:0] outputs in relation to the master slave select signal MSLS. 0B The SELO outputs have the same polarity as the MSLS signal (active high). The SELO outputs have the inverted polarity to the MSLS 1B signal (active low). CTR[1] CTR[2] User's Manual USIC, UM_V0.2D5 19-150 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel Table 19-19 Signification of PCRL/PCRH Bits for SSC (cont'd) Field CTR[3] Alias FEM Description Frame End Mode This bit defines if a transmit buffer content that is not valid for transmission is considered as an end of frame condition for the slave select generation. 0B The current data frame is considered as finished when the last bit of a data word has been sent out and the transmit buffer TBUF does not contain new data (TDV = 0). 1B The MSLS signal is kept active also while no new data is available and no other end of frame condition is reached. In this case, the SW can accept delays in delivering the data without automatic deactivation of MSLS in multi-word data frames. Input Frequency Selection This bit field defines the input frequency fCTQIN for the generation of the slave select delays Tiw and Tnf. 00B fCTQIN = fPDIV 01B fCTQIN = fPPP 10B fCTQIN = fSCLK 11B fCTQIN = fMCLK Divider Factor PCTQ1 for Tiw and Tnf This bit field represents the divider factor PCTQ1 (range = 0 - 3) for the generation of the inter-word delay and the next-frame delay. Tiw = Tnf = 1/fCTQIN * (PCTQ1 + 1) * (DCTQ1 + 1) Divider Factor DCTQ1 for Tiw and Tnf This bit field represents the divider factor DCTQ1 (range = 0 31) for the generation of the inter-word delay and the next-frame delay. Tiw = Tnf = 1/fCTQIN * (PCTQ1 + 1) * (DCTQ1 + 1) MSLS Interrupt Enable This bit enables/disables the generation of a protocol interrupt if the state of the MSLS signal changes (indicated by PSR.MSLSEV = 1). 0B A protocol interrupt is not generated if a change of signal MSLS is detected. 1B A protocol interrupt is generated if a change of signal MSLS is detected. CTR [5:4] CTQ SEL1 CTR [7:6] PCTQ1 CTR [12:8] DCTQ1 CTR[14] MSLS IEN User's Manual USIC, UM_V0.2D5 19-151 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel Table 19-19 Signification of PCRL/PCRH Bits for SSC (cont'd) Field CTR[15] Alias DX2T IEN Description DX2T Interrupt Enable This bit enables/disables the generation of a protocol interrupt if the DX2T signal becomes activated (indicated by PSR.DX2TEV = 1). 0B A protocol interrupt is not generated if DX2T is activated. 1B A protocol interrupt is generated if DX2T is activated. Select Output This bit field defines the setting of the SELO[7:0] output lines. The corresponding SELOx line can not be activated. 0B 1B The corresponding SELOx line can be activated (according to the mode selected by SELCTR). Enable Inter-Word Delay Tiw This bit enables/disables the inter-word delay Tiw after the transmission of a data word. 0B No delay between data words of the same frame. 1B The inter-word delay Tiw is enabled and introduced between data words of the same frame. Master Clock Enable This bit enables/disables the generation of the master clock output signal MCLK, independent from master or slave mode. 0B The MCLK generation is disabled and output MCLK = 0. 1B The MCLK generation is enabled. Reserved returns 0 if read; should be written with 0; CTR [23:16] SELO [7:0] CTR[24] TIWEN CTR[31] MCLK other CTR[x] User's Manual USIC, UM_V0.2D5 19-152 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.4.5.2 Protocol Status Register PSR The following PSR status bits or bit fields are available in SSC mode. Please note that the bits in register PSR are not cleared by HW. The row marked PI indicates which status bit can generate a protocol interrupt in SSC mode. The general interrupt status flags are described in the general interrupt chapter. Table 19-20 Signification of PSR Bits for SSC Bit ST[0] Alias MSLS Description MSLS Status This bit indicates the current status of the MSLS signal. It be cleared by SW to stop a running frame. 0 The internal signal MSLS is inactive (0). 1 The internal signal MSLS is active (1). DX2S Status This bit indicates the current status of the DX2S signal that can be used as slave select input SELIN. 0 DX2S is 0. 1 DX2S is 1. PI - ST[1] DX2S - ST[2] MSLS EV MSLS Event Detected y This bit indicates that the MSLS signal has changed its state since MSLSEV has been cleared. Together with the MSLS status bit, the activation/deactivation of the MSLS signal can be monitored. 0 The MSLS signal has not changed its state. 1 The MSLS signal has changed its state. DX2T Event Detected This bit indicates that the DX2T trigger signal has been activated since DX2TEV has been cleared. 0 The DX2T signal has not been activated. 1 The DX2T signal has been activated. Reserved returns 0 if read; not modified in SSC mode General Interrupt Flags y ST[3] DX2T EV other ST[x] PSR [15:10] y - User's Manual USIC, UM_V0.2D5 19-153 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.4.6 SSC Timing Considerations The input and output signals have to respect certain timings in order to ensure correct data reception and transmission. In addition to module internal timings (due to input filters, reaction times on events, etc.), also the timings from the input pin via the input stage (Tin) to the module and from the module via the output driver stage to the pin (Tout), as well as the signal propagation on the wires (Tprop) have to be taken into account. Please note that there might by additional delays in the DXn input stages, because the digital filter and the synchronization stages lead to systematic delays, that have to be considered if these functions are used. 19.4.6.1 Closed-loop Delay A system-inherent limiting factor for the baud rate of an SSC connection is the closedloop delay. In a typical application setup, a communication master device is connected to a slave device in full-duplex mode with independent lines for transmit and receive data. In a general case, all transmitters refer to one shift clock edge for transmission and all receivers refer to the other shift clock edge for reception. The master device's SSC module sends out the transmit data, the shift clock and optionally the slave select signal. Therefore, the baud rate generation (BRG) and slave select generation (SSG) are part of the master device. The frame control is similar for SSC modules in master and slave mode, the main difference is the fact which module generates the shift clock and optionally, the slave select signals. SSC master module TBUF RBUF frame control Tout Tin Tprop MTSR Tprop MRST Tin Tout SSC slave module RBUF TBUF frame control Tout BRG Tout SSG SSC master device Figure 19-37 SSC Closed-loop Delay Tprop shift clock Tprop slave select Tin Tin SSC slave device SSC_closed_loop User's Manual USIC, UM_V0.2D5 19-154 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel The signal path between the SSC modules of the master and the slave device includes the master's output driver, the wiring to the slave device and the slave device's input stage. With the received shift clock edges, the slave device receives the master's transmit data and transmits its own data back to the master device, passing by a similar signal path in the other direction. The master module receives the slave's transmit data related to its internal shift clock edges. In order to ensure correct data reception in the master device, the slave's transmit data has to be stable (respecting setup and hold times) as master receive data with the next shift clock edge of the master (generally 1/2 shift clock period). To avoid data corruption, the accumulated delays of the input and output stages, the signal propagation on the wiring and the reaction times of the transmitter/receiver have to be carefully considered, especially at high baud rates. In the given example, the time between the generation of the shift clock signal and the evaluation of the receive data by the master SSC module is given by the sum of Tout_master + 2*Tprop + Tin_slave + Tout_slave + Tin_master + module reaction times + input setup times. The input path is characterized by an input delay depending mainly on the input stage characteristics of the pads. The output path delay is determined by the output driver delay and its slew rate, the external load and current capability of the driver. The device specific values for the input/output driver are given in the AC/DC chapter. 19.4.6.2 Delay Compensation in Master Mode A higher baud rate can be reached by delay compensation in master mode. This compensation is possible if (at least) the shift clock pin is bidirectional. User's Manual USIC, UM_V0.2D5 19-155 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel SSC master module TBUF RBUF frame control Tout Tin Tprop MTSR Tprop MRST Tin Tout SSC slave module RBUF TBUF frame control Tprop BRG SSG SSC master device shift clock Tprop slave select Tin Tin SSC slave device SSC_delay_comp Figure 19-38 SSC Master Mode with Delay Compensation If the shift clock signal in master mode is directly taken from the input function in parallel to the output signal, the output delay of the master device's shift clock output is compensated and only the difference between the input delays of the master and the slave devices have to be taken into account instead of the complete master's output delay and the slave's input delay of the shift clock path. In the given example, the time between the evaluation of the shift clock signal and the receive data by the master SSC module is reduced by Tin_master + Tout_master. Although being a master mode, the shift clock input and optionally the slave select signal are not directly connected internally to the data shift unit, but are taken as external signals from input pins (DXnCTR.INSW = 1). The delay compensation does not lead to additional pins for the SSC communication if the shift clock output pin (slave select output pin, respectively) is/are bidirectional. In this case, the input signal is decoupled from other internal signals, because it is related to the signal level at the pin itself. 19.4.6.3 SSC Timing Values Figure 19-39 shows an example for SSC signal timings on module level. It does not imply the input/output driver delays that have to be additionally taken into consideration. User's Manual USIC, UM_V0.2D5 19-156 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary active inactive Universal Serial Interface Channel slave select transmit data shift clock receive data tSSU tTDTC tSHD tTDVL tINAC transmit edge first bit tTDHD receive edge tRDSU last bit tRDHD Figure 19-39 SSC Signal Timings Table 19-21 SSC Signal Timings Timing Relation slave select setup time (slave select active before first shift clock edge) slave select hold time (slave select active after last shift clock edge) slave select inactive time (slave select inactive to slave select active) Symbol Min. tSSU tSHD tINAC 10 10 2 0 0 0 10 10 SSC_timings Max. 10 10 10 - Unit ns ns tSYS = 1 / fSYS ns ns ns ns ns Transmit data valid (transmit data stable after tTDVL slave select active) Transmit data to clock (transmit data valid after transmit clock edge) tTDTC Transmit data hold (transmit data stable after tTDHD slave select inactive) Receive data setup (receive data stable before receive clock edge) Receive data hold (receive data stable after receive clock edge) tRDSU tRDHD User's Manual USIC, UM_V0.2D5 19-157 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.5 Inter-IC Bus Protocol (IIC) The IIC protocol of the USIC refers to the IIC bus specification version 2.1, january 2000 from Philips Semiconductors. Contrary to that specification, the USIC device assumes rise/fall times of the bus signals of max. 300 ns in all modes. Please refer to the pad characteristics in the AC/DC chapter for the driver capability. CBUS mode and HS mode are not supported. The IIC mode is selected by CCR.MODE = 0100B with CCFG.IIC = 1 (IIC mode available). This chapter contains the following sections: * * * * * Introduction (see Section 19.5.1) Operating the IIC protocol (see Section 19.5.2) Symbol timing and programming (see Section 19.5.3) Data flow handling (see Section 19.5.4) IIC protocol registers (see Section 19.5.5) 19.5.1 * * * * * * Introduction USIC IIC Features: Two-wire interface, with one line for shift clock transfer and synchronization (shift clock SCL), the other one for the data transfer (shift data SDA) Communication in standard mode (100 kBit/s) or in fast mode (up to 400 kBit/s) Support of 7-bit addressing, as well as 10-bit addressing Master mode operation, where the IIC controls the bus transactions and provides the clock signal. Slave mode operation, where an external master controls the bus transactions and provides the clock signal. Multi-master mode operation, where several masters can be connected to the bus and bus arbitration can take place, i.e. the IIC module can be master or slave. The master/slave operation of an IIC bus participant can change from frame to frame. Efficient frame handling (low SW effort), also allowing PEC transfers Powerful interrupt handling due to multitude of indication flags Compensation support for input delays * * * User's Manual USIC, UM_V0.2D5 19-158 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.5.1.1 Signal Description An IIC connection is characterized by two wires (SDA and SCL). The output drivers for these signals must have open-drain characteristics to allow the wired-AND connection of all SDA lines together and all SCL lines together to form the IIC bus system. Due to this structure, a high level driven by an output stage does not necessarily lead immediately to a high level at the corresponding input. Therefore, each SDA or SCL connection has to be input and output at the same time, because the input function always monitors the level of the signal, also while sending. * * Shift data SDA: input handled by DX0 stage, output signal DOUT Shift clock SCL: input handled by DX1 stage, output signal SCLKOUT Figure 19-24 shows a connection of two IIC bus participants (modules IIC A and IIC B) using the USIC. In this example, the pin assignment of module IIC A shows separate pins for the input and output signals for SDA and SCL. This assignment can be used if the application does not provide pins having DOUT and a DX0 stage input for the same pin (similar for SCLKOUT and DX1). The pin assignment of module IIC B shows the connection of DOUT and a DX0 input at the same pin, also for SCLKOUT and a DX1 input. module IIC A TBUF RBUF SCLKOUT + 3.3 V module IIC B TBUF SCLKOUT RBUF transfer control PPP IIC DX1 SCLKIN DOUT SCL + 3.3 V DX1 SCLKIN DOUT transfer control PPP IIC DX0 DIN baud rate generator fsys (IIC A) SDA DX0 DIN fsys (IIC B) baud rate generator IIC_signals Figure 19-40 IIC Signal Connections User's Manual USIC, UM_V0.2D5 19-159 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.5.1.2 Symbols A symbol is a sequence of edges on the lines SDA and SCL. Symbols contain 10 or 25 time quanta tq, depending on the selected baud rate. The baud rate generator determines the length of the time quanta tq, the sequence of edges in a symbol is handled by the IIC protocol pre-processor, and the sequence of symbols can be programmed by the user according to the application needs. The following symbols are defined: * * Bus idle: SDA and SCL are high. No data transfer takes place currently. Data bit symbol: SDA stable during the high phase of SCL. SDA then represents the transferred bit value. There is one clock pulse on SCL for each transferred bit of data. During data transfers SDA may only change while SCL is low. Start symbol: Signal SDA being high followed by a falling edge of SDA while SCL is high indicates a start condition. This start condition initiates a data transfer over the IIC bus after the bus has been idle. Repeated start symbol: This start condition initiates a data transfer over the bus after a data symbol when the bus has not been idle. Therefore, SDA is set high and SCL low, followed by a start symbol. Stop symbol: A rising edge on SDA while SCL is high indicates a stop condition. This stop condition terminates a data transfer to release the bus to idle state. Between a start condition and a stop condition an arbitrary number of bytes may be transferred. * * * User's Manual USIC, UM_V0.2D5 19-160 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.5.1.3 Frame Format Data is transferred by the 2-line IIC bus (SDA, SCL) using a protocol that ensures reliable and efficient transfers. The sender of a (data) byte receives and checks the value of the following acknowledge field. The IIC being a wired-AND bus system, a 0 of at least one device leads to a 0 on the bus, which is received by all devices. A data word consists of 8 data bit symbols for the data value, followed by another data bit symbol for the acknowledge bit. The data word can be interpreted as address information (after a start symbol) or as transferred data (after the address). In order to be able to receive an acknowledge signal, the sender of the data bits has to release the SDA line by sending a 1 as acknowledge value. Depending on the internal state of the receiver, the acknowledge bit is either sent active or passive. SDA master SCL master SDA slave SCL slave start 1 D7 D6 Dx D0 0 1 1 2 8 9 0 1 0 1 0 data word ack stop IIC_frame Figure 19-41 IIC Frame Example (simplified) User's Manual USIC, UM_V0.2D5 19-161 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.5.2 * Operating the IIC In order to operate the IIC protocol, the following issues have to be considered: Select IIC mode: It is recommended to configure all parameters of the IIC that do not change during run time while CCR.MODE = 0000B. Bit field SCTRL.TRM = 11B should to be programmed. The configuration of the input stages has to be done while CCR.MODE = 0000B to avoid unintended edges of the input signals and the IIC mode can be enabled by CCR.MODE = 0100B afterwards. Pin connections: Establish a connection of input stage DX0 (with DX0CR.DPOL = 0) to the selected shift data pin SDA (signal DIN) with DX0CR.INSW = 0 and configure the transmit data output signal DOUT (with SCTRL.DOCFG = 00B) to the same pin. If available, this can be the same pin for input and output, or connect the selected input pin and the output pin to form the SDA line. The same mechanism applies for the shift clock line SCL. Here, signal SCLKOUT (with BRGH.SCLKCFG = 00B) and an input of the DX1 stage have to be connected (with DX1CR.DPOL = 0). The input stage DX2 is not used for the IIC protocol. If the digital input filters are enabled in the DX0/1 stages, their delays have to be taken into account for correct calculation of the signal timings. The pins used for SDA and SCL have to be set to open-drain mode to support the wired-AND structure of the IIC bus lines. Bit timing configuration: In standard mode (100 kBit/s) a minimum module frequency of 2 MHz is necessary, whereas in fast mode (400 kBit/s) a minimum of 10 MHz is required. Additionally, if the digital filter stage should be used to eliminate spikes up to 50 ns, a filter frequency of 20 MHz is necessary. There could be an uncertainty in the SCL high phase timing of maximum 1/ fPPP if another IIC participant lengthens the SCL low phase on the bus. More details are given in Section 19.5.3. Data format configuration: The data format has to be configured for 8 data bits (SCTRH.WLE = 7), unlimited data flow (SCTRH.FLE = 3FFH), and MSB shifted first (SCTRL.SDIR = 1). The parity generation has to be disabled (CCR.PM = 00B). General hints: The IIC slave module becomes active (for reception or transmission) if it is selected by the address sent by the master. In the case that the slave sends data to the master, it uses the transmit path. So a master must not request to read data from the slave address defined for its own channel in order to avoid collisions. The built-in error detection mechanisms are only activated while the IIC module is taking part in IIC bus traffic. If the slave can not deal with too high frequencies, it can lengthen the low phase of 19-162 V1.0, 2007-06 * * * * User's Manual USIC, UM_V0.2D5 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel the SCL signal. For data transfers according to the IIC specification, the shift data line SDA shall only change while SCL = 0 (defined by IIC bus specification). 19.5.2.1 Transmission Chain The IIC bus protocol requiring a kind of in-bit-response during the arbitration phase and while a slave is transmitting, the resulting loop delay of the transmission chain can limit the reachable maximal baud rate, strongly depending on the bus characteristics (bus load, module frequency, etc.). Figure 19-24 shows the general signal path and the delays in the case of a slave transmission. The shift clock SCL is generated by the master device, output on the wire, then it passes through the input stage and the input filter. Now, the edges can be detected and the SDA data signal can be generated accordingly. The SDA signal passes through the output stage and the wire to the master receiver part. There, it passes through the input stage and the input filter before it is sampled. This complete loop has to be finished (including all settling times to obtain stable signal levels) before the SCL signal changes again. The delays in this path have to be taken into account for the calculation of the baud rate as a function of fSYS and fPPP. 19.5.2.2 Byte Stretching If a device is selected as transceiver and should transmit a data byte but the transmit buffer TBUF does not contain valid data to be transmitted, the device ties down SCL = 0 at the end of the previous acknowledge bit. The waiting period is finished if new valid data has been detected in TBUF. 19.5.2.3 Baud Rate Update The baud rate setting can be changed from frame to frame. The BRGL/H register setting and PCR.STIM are sampled (shadowed) while the IIC bus is idle. A new setting of these bits can be programmed while a frame is running. The new setting will be taken into account with the start of the next frame. In order to minimize the risk of inconsistencies when changing baud rate setting (several registers have to be updated), it is recommended to avoid baud rate changes while the IIC protocol is enabled, especially for slave devices. 19.5.2.4 Master Arbitration During the address and data transmission, the master transmitter checks at the rising edge of SCL for each data bit if the value it is sending is equal to the value read on the SDA line. If yes, the next data bit values can be 0. If this is not the case (transmitted value = 1, value read = 0), the master has lost the transmit arbitration. This is indicated by status flag PSR.ARL and can generate a protocol interrupt if enabled by User's Manual USIC, UM_V0.2D5 19-163 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel PCRH.ARLIEN. When the transmit arbitration has been lost, the SW has to initialize the complete frame again, starting with the first address byte together with the start condition for a new master transmit attempt. Arbitration also takes place for the ACK bit. 19.5.2.5 Release of TBUF In case of a non-acknowledge or an error, the content of TBUF becomes invalid. In both cases, the SW has to flush the transmit buffer and to set it up again with appropriate values to react on the previous event. 19.5.2.6 Mode Control Behavior In multi-master mode, only run mode 0 and stop mode 0 are supported, the other modes must not be programmed. * Run Mode 0: Behavior as programmed. If TCSRL.TDV = 0 (no new valid TBUF entry found) when a new TBUF entry needs to be processed, the IIC module waits for TDV becoming set to continue operation. Run Mode 1: Behavior as programmed. If in master mode, TCSRL.TDV = 0 (no new valid TBUF entry found) when a new TBUF entry needs to be processed, the IIC module sends a stop condition to finish the frame. In slave mode, no difference to run mode 0. Stop Mode 0: Bit TCSRL.TDV is internally considered as 0 (the bit itself is not modified by the stop mode). A currently running word is finished normally, but no new word is started in case of master mode (wait for TDV active). Bit TDV being considered as 0 for master and slave, the slave will force a wait state on the bus if read by an external master, too. Additionally, it is not possible to force the generation of a STOP condition out of the wait state. The reason is, that a master read transfer must be finished with a notacknowledged followed by a STOP condition to allow the slave to release his SDA line. Otherwise the slave may force the SDA line to 0 (first data bit of next byte) making it impossible to generate the STOP condition (rising edge on SDA). To continue operation, the mode must be switched to run mode 0 Stop Mode 1: Same as stop mode 0, but additionally, a master sends a STOP condition to finish the frame. If stop mode 1 is requested for a master device after the first byte of a 10 bit address, a stop condition will be sent out. In this case, a slave device will issue an error interrupt. * * * User's Manual USIC, UM_V0.2D5 19-164 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.5.2.7 IIC Protocol Interrupt Events The following protocol-related events are generated in IIC mode and can lead to a protocol interrupt. Please note that the bits in register PSR are not all automatically cleared by HW and have to be cleared by SW in order to monitor new incoming events. * Transmit buffer event: The transmit buffer event indication flag PSR.TBIF is set when the content of the transmit buffer TBUF has been loaded to the transmit shift register, indicating that the action requested by the TBUF entry has started. With this event, bit TCSRL.TDV is cleared. This interrupt can be used to write the next TBUF entry while the last one is in progress (handled by the transmitter part). Receive event: This receive event indication flag PSR.RIF indicates that a new data byte has been written to the receive buffer RBUF0/1 (except for the first address byte of a new frame, that is indicated by an alternative receive interrupt). The flag becomes set when the data byte is received (after the falling edge of SCL). This interrupt can be used to read out the received data while a new data byte can be in progress (handled by the receiver part). Alternate receive event: The alternative receive event indication flag AIF is based on bit RBUFSR[9] (same as RBUF[9]), indicating that the received byte is the first byte of a frame. Protocol interrupt events: The IIC protocol related interrupt events are either indicating the reception of symbols or the detection of frame errors (common indication PSR.ERR) or unexpected/wrong TDF codes (common indication PSR.WTDF). - start condition received at a correct position in a frame (PSR.SCR) - repeated start condition received at a correct position in a frame (PSR.RSCR) - stop condition transferred at a correct position in a frame (PSR.PCR) - master arbitration lost (PSR.ARL) - slave read requested (PSR.SRR) - non-acknowledge received (PSR.NACK) - start condition not at the expected position in a frame (PSR.ERR) - stop condition not at the expected position in a frame (PSR.ERR) - 10-bit address interrupted by a stop condition after the first address byte (PSR.ERR) - TDF slave code in master mode (PSR.WTDF) - TDF master code in slave mode (PSR.WTDF) - Reserved TDF code found (PSR.WDTF) - Start condition code during a running frame in master mode (PSR.WTDF) - Data byte transmission code after transfer direction has been changed to reception (master read) in master mode (PSR.WTDF) * * * User's Manual USIC, UM_V0.2D5 19-165 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel If a wrong TDF code is found in TBUF, the error event is active until the TDF value is either corrected or invalidated. If the related interrupt is enabled, the interrupt handler should check PSR.WDTF first and correct or invalidate TBUF, before dealing with the other possible interrupt events. 19.5.2.8 Receiver Address Acknowledge After a (repeated) start condition, the master sends a slave address to identify the target device of the communication. The start address can comprise one or two address bytes (for 7 bit or for 10 bit addressing schemes). After an address byte, a slave sensitive to the transmitted address has to acknowledge the reception. Therefore, the slave's address can be programmed in the device, where it is compared to the received address. In case of a match, the slave answers with an acknowledge (SDA = 0). Slaves that are not targeted answer with an non-acknowledge (SDA = 1). In addition to the match of the programmed address, an other address byte value has to be answered with an acknowledge if the slave is capable to handle the corresponding requests. The address byte 00H indicates a general call address, that can be acknowledged. The value 01H stands for a start byte generation, that is not acknowledged (details see IIC specification, chapter 10). In order to allow selective acknowledges for the different values of the address byte(s), the following control mechanism is implemented: * * * The address byte 00H is acknowledged if bit PCRH.ACK00 is set. The address byte 01H is not acknowledged. The first 7 bits of a received first address byte are compared to the programmed slave address (PCR.SLAD[15:9]). If these bits match, the slave sends an acknowledge. In addition to this, if the slave address is programmed to 1111 0XXB, the slave device waits for a second address byte and compares it also to PCR.SLAD[7:0] and sends an acknowledge accordingly to cover the 10 bit addressing mode. The user has to take care about reserved addresses (refer to IIC specification for more detailed description). Only the address 1111 0XXB is supported. Under each of these conditions, bit PSR.SLSEL will be set when the addressing delivered a match. This bit is cleared automatically by a (repeated) start condition. 19.5.2.9 Receiver Handling A selected slave receiver always acknowledges a received data byte. If the receive buffers RBUF0/1 are already full and can not accept more data, the respective register is overwritten (PSR.DLI becomes set in this case and a protocol interrupt can be generated). An address reception also uses the registers RBUF0/1 to store the address before checking if the device is selected. The received addresses do not set RDV0/1, so the addresses are not handled like received data. User's Manual USIC, UM_V0.2D5 19-166 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.5.2.10 Receiver Status Information In addition to the received data byte, some IIC protocol related information is stored in the 16 bit data word of the receive buffer. The received data byte is available at the bit positions RBUF[7:0], whereas the additional information is monitored at the bit positions RBUF[12:8]. This structure allows to identify the meaning of each received data byte without reading additional registers, also when using a FIFO data buffer. * RBUF[8]: Value of the received acknowledge bit. This information is also available in RBUFSR[8] as protocol argument. RBUF[9]: A 1 at this bit position indicates that the data byte has been the first byte of a new frame (address) after a (repeated) start condition. A 0 at this bit position indicates further data bytes. This information is also available in RBUFSR[9], allowing different interrupt routines for the address and data handling. RBUF[10]: A 1 at this bit position indicates that the data byte has been received when the device has been in slave mode, whereas a 1 indicates a reception in master mode. RBUF[11]: A 1 at this bit position indicates an incomplete/erroneous data byte in the receive buffer caused by a wrong position of a START or STOP condition in the frame. The bit is not identical to the frame error status bit in PSR, because the bit in the PSR has to be cleared by software ("sticky" bit), whereas RBUF[11] is evaluated data byte by data byte. If RBUF[11] = 0, the received data byte has been correct, independent of former errors. RBUF[12]: A 0 at this bit position indicates that the programmed address has been received. A 1 indicates a general call address. * * * * User's Manual USIC, UM_V0.2D5 19-167 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.5.3 Symbol Timing The symbol timing of the IIC is determined by the master stimulating the shift clock line SCL. It is different for standard and fast IIC mode. * 100 kBaud standard mode (PCRH.STIM = 0): The symbol timing is based on 10 time quanta tq per symbol. A minimum module clock frequency fSYS = 2 MHz is required. 400 kBaud standard mode (PCRH.STIM = 1): The symbol timing is based on 25 time quanta tq per symbol. A minimum module clock frequency fSYS = 10 MHz is required. * The baud rate setting should only be changed while the transmitter and the receiver are idle or CCR.MODE = 0. The bits in register BRGL define the length of a time quantum tq that is given by one period of fPCTQ. * * * BRGL.CTQSEL to define the input frequency fCTQIN for the time quanta generation BRGL.PCTQ to define the length of a time quantum (division of fCTQIN by 1, 2, 3, or 4) BRGL.DCTQ to define the number of time quanta per symbol (number of tq = DCTQ + 1) The standard setting is given by CTQSEL = 00B (fCTQIN = fPDIV) and PPPEN = 0 (fPPP = fPIN). Under these conditions, the frequency fPCTQ is given by: (19.10) 1 1 f PCTQ = f PIN x ----------------------- x ------------------------PDIV + 1 PCTQ + 1 To respect the specified SDA hold time of 300 ns after a falling edge of signal SCL, a hold delay tHDEL has been introduced. It also prevents an erroneous detection of a start or a stop condition. The length of this delay can be programmed by bit field PCRH.HDEL. If the HDEL value is programmed to 0, a delay of one period of fSYS is introduced. Taking into account the input sampling and output update, bit field HDEL can be programmed according to: (19.11) f PPP HDEL 300ns f PPP - 3 ---------- + 1 f SYS If the digital input filter is used, HDEL compensates the filter delay of 2 filter periods (fPPP should be used) in case of a spike on the input signal. This ensures that a data bit on the SDA line changing just before the rising edge or behind the falling edge of SCL won't be treated as a start or stop condition. User's Manual USIC, UM_V0.2D5 19-168 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.5.3.1 Start Symbol Figure 19-42 shows the general start symbol timing. bus idle SDA SCL standard mode fast mode X X 0 0 ... ... start symbol 45 15 16 ... ... 9X tq 24 X IIC_start_timing Figure 19-42 Start Symbol Timing 19.5.3.2 Repeated Start Symbol During the first part of a repeated start symbol, an SCL low value is driven for the specified number of time quanta. Then a high value is output. After the detection of a rising edge at the SCL input, a normal start symbol is generated, as shown in Figure 19-43. repeated start symbol start symbol SDA SCL standard mode fast mode X X tHDEL 0 0 ... ... 40 15 0 ... ... 45 15 16 ... ... 9X tq 24 X IIC_rep_start_timing Figure 19-43 Repeated Start Symbol Timing User's Manual USIC, UM_V0.2D5 19-169 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.5.3.3 Stop Symbol Figure 19-44 shows the stop symbol timing. stop symbol SDA SCL standard mode fast mode tHDEL bus idle X X 0 0 ... ... 45 15 16 ... ... 9X tq 24 X IIC_stop_timing Figure 19-44 Stop Symbol Timing 19.5.3.4 Data Bit Symbol Figure 19-45 shows the general data bit symbol timing. data bit symbol SDA SCL standard mode fast mode X X tHDEL 0 0 ... ... 45 15 16 ... ... 9X tq 24 X IIC_data_bit_timing Figure 19-45 Data Bit Symbol Output SDA changes after the time tHDEL defined by PCRH.HDEL has elapsed if a falling edge is detected at the SCL input to respect the SDA hold time. The value of PCRH.HDEL allows compensation of the delay of the SCL input path (sampling, User's Manual USIC, UM_V0.2D5 19-170 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel filtering). In the case of an acknowledge transmission, the USIC IIC waits for the receiver indicating that a complete byte has been received. This adds an additional delay of 3 periods of fSYS to the path. The minimum module input frequency has to be selected properly to ensure the SDA setup time to SCL rising edge. 19.5.4 Data Flow Handling The handling of the data flow and the sequence of the symbols in an IIC frame is controlled by the IIC transmitter part of the USIC communication channel. The IIC bus protocol is byte-oriented, whereas a USIC data buffer word can contain up to 16 data bits. In addition to the data byte to be transmitted (located at TBUF[7:0]), bit field TDF (transmit data format) to control the IIC sequence is located at the bit positions TBUF[10:8]. The TDF code defines for each data byte how it should be transmitted (IIC master or IIC slave), and controls the transmission of (repeated) start and stop symbols. This structure allows the definition of a complete IIC frame for an IIC master device only by writing to TBUFx or by using a FIFO data buffer mechanism, because no other control registers have to be accessed. If a wrong or unexpected TDF code is encountered (e.g. due to a SW error during setup of the transmit buffer), a stop condition will be sent out by the master. This leads to an abort of the currently running frame. A slave module waits for a valid TDF code and sets SCL = 0. The SW then has to invalidate the unexpected TDF code and write a valid one. Please note that during an arbitration phase in multi-master bus systems an unpredictable bus behavior may occur due to an unexpected stop condition. 19.5.4.1 Transmit Data Formats The following transmit data formats are available in master mode: * Send data byte as master (TDF = 000B): This format is used to transmit a data byte from the master to a slave. The transmitter sends its data byte (TBUF[7:0]), receives and checks the acknowledge bit sent by the slave. Receive data byte and send acknowledge 0 (TDF = 010B): This format is used by the master to read a data byte from a slave. The master acknowledges the transfer with a 0-level to continue the transfer. The content of TBUF[7:0] is ignored. Receive data byte and send acknowledge 1 (TDF = 011B): This format is used by the master to read a data byte from a slave. The master does not acknowledge the transfer with a 1-level to finish the transfer. The content of TBUF[7:0] is ignored. Send start condition (TDF = 100B): If TBUF contains this entry while the bus is idle, a start condition will be generated. * * * User's Manual USIC, UM_V0.2D5 19-171 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel * * * The content of TBUF[7:0] is taken as first address byte for the transmission (bits TBUF[7:1] are the address, the LSB is the read/write control). Send repeated start condition (TDF = 101B): If TBUF contains this entry and SCL = 0 and a byte transfer is not in progress, a repeated start condition will be sent out if the device is the current master. The current master is defined as the device that has set the start condition (and also won the master arbitration) for the current message. The content of TBUF[7:0] is taken as first address byte for the transmission (bits TBUF[7:1] are the address, the LSB is the read/write control). Send stop condition (TDF = 110B): If the current master has finished its last byte transfer (including acknowledge), it sends a stop condition if this format is in TBUF. The content of TBUF[7:0] is ignored. TDF = 111B: Reserved and must not be programmed. No additional action except releasing the TBUF entry and setting the error bit in PSR (that can lead to a protocol interrupt). The following transmit data format is available in slave mode (the symbols in a frame are controlled by the master and the slave only has to send data if it has been "asked" by the master): * Send data byte as slave (TDF = 001B): This format is used to transmit a data byte from a slave to the master. The transmitter sends its data byte (TBUF[7:0]) plus the acknowledge bit as a 1. User's Manual USIC, UM_V0.2D5 19-172 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.5.4.2 Valid Master Transmit Data Formats Due to the IIC frame formats1), only some specific sequences of TDF codes are possible and valid. If the USIC IIC module detects a wrong TDF code in a running frame, the transfer is aborted and flag PCR.WTDF is set. Additionally, an interrupt can be generated if enabled by the user. In case of a wrong TDF code, the frame will be aborted immediately with a STOP condition if the USIC IIC master still owns the SDA line. But if the accessed slave owns the SDA line (read transfer), the master must perform a dummy read with a non-acknowledge so that the slave releases the SDA line before a STOP condition can be sent. The received data byte of the dummy read will be stored in RBUF0/1, but RDV0/1 won't be set. Therefore the dummy read won't generate a receive interrupt and the data byte won't be stored into the receive FIFO. If the transfer direction has changed in the current frame (master read access), the transmit data request (TDF = 000B) is not possible and won't be accepted (leading to a wrong TDF Code indication). Table 19-22 Valid TDF Codes Overview Frame Position first TDF code (master idle) Valid TDF Codes start (100B) read transfer: second TDF code (after start receive with acknowledge (010B) or or repeated start) receive with not-acknowledge (011B) write transfer: second TDF code (after start transmit (000B), repeated start (101B), or or repeated start) stop (110B) read transfer: third and subsequent TDF code after acknowledge read transfer: third and subsequent TDF code after not-acknowledge write transfer: third and subsequent TDF code * receive with acknowledge (010B) or receive with not-acknowledge (011B) repeated start (101B) or stop (110B) transmit (000B), repeated start (101B), or stop (110B) * First TDF code: A master transfer starts with the TDF start code (100B). All other codes are ignored, but no WTDF error will be indicated. TDF code after a start (100B) or repeated start code (101B) in case of a read access: If a master-read transfer is started (determined by the LSB of the address byte = 1), the transfer direction of SDA changes and the slave will actively drive the data line. In this case, only the codes 010B and 011B are valid. To abort the transfer in case of 1) Phillips IIC Spec V2.1, chapters 9 and 14.2 User's Manual USIC, UM_V0.2D5 19-173 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel * * * * * a wrong code, a dummy read must be performed by the master before the STOP condition can be generated. TDF code after a start (100B) or repeated start code (101B) in case of a write access: If a master-write transfer is started (determined by the LSB of the address byte = 0), the master still owns the SDA line. In this case, the transmit (000B), repeated start (101B) and stop (110B) codes are valid. The other codes are considered as wrong. To abort the transfer in case of a wrong code, the STOP condition is generated immediately. TDF code of the third and subsequent command in case of a read access with acknowledged previous data byte: If a master-read transfer is started (determined by the LSB of the address byte), the transfer direction of SDA changes and the slave will actively drive the data line. To force the slave to release the SDA line, the master has to not-acknowledge a byte transfer. In this case, only the receive codes 010B and 011B are valid. To abort the transfer in case of a wrong code, a dummy read must be performed by the master before the STOP condition can be generated. TDF code of the third and subsequent command in case of a read access with a notacknowledged previous data byte: If a master-read transfer is started (determined by the LSB of the address byte), the transfer direction of SDA changes and the slave will actively drive the data line. To force the slave to release the SDA line, the master has to not-acknowledge a byte transfer. In this case, only the restart (101B) and stop code (110B) are valid. To abort the transfer in case of a wrong code, the STOP condition is generated immediately. TDF code of the third and subsequent command in case of a write access: If a master-write transfer is started (determined by the LSB of the address byte), the master still owns the SDA line. In this case, the transmit (000B), repeated start (101B) and stop (110B) codes are valid. The other codes are considered as wrong. To abort the transfer in case of a wrong code, the STOP condition is generated immediately. After a master device has received a non-acknowledge from a slave device, a stop condition will be sent out automatically, except if the following TDF code requests a repeated start condition. In this case, the TDF code is taken into account, whereas all other TDF codes are ignored. User's Manual USIC, UM_V0.2D5 19-174 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel n send start condition n y bus idle ? y TDF = 100 ? indicate arb. loss and release bus y send TBUF[7:0] with ACK = 1 arbitration lost ? n send all 1s with ACK = 0 get new valid TBUF value transmit (t) receive (r) r send all 1s with ACK = 1 t TDF = 000 ? y TDF = 010 ? y TDF = 011 ? y n n n send rep. start condition TDF = 101 ? TDF = 110 ? y n n y send stop condition indicate error ignore TBUF IIC_master_tr_flow Figure 19-46 IIC Master Transmission User's Manual USIC, UM_V0.2D5 19-175 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.5.5 IIC Protocol Registers In IIC mode, the registers PCRH, PCRL and PSR handle IIC related information. 19.5.5.1 Protocol Control Registers The following control bits or bit fields are available in the IIC mode. Table 19-23 Signification of PCRL/H Bits for IIC Bit CTR [15:0] Alias SLAD [15:0] Description Slave Address This bit field contains the programmed slave address. The corresponding bits in the first received address byte are compared to the bits SLAD[15:9] to check for address match. If SLAD[15:11] = 11110B, then the second address byte is also compared to SLAD[7:0]. Acknowledge 00H This bit defines if a slave device should be sensitive to the slave address 00H. 0B The slave device is not sensitive to this address. 1B The slave device is sensitive to this address. Symbol Timing This bit defines how many time quanta are used in a symbol. 0B A symbol contains 10 time quanta. The timing is adapted for standard mode (100 kBaud). 1B A symbol contains 25 time quanta. The timing is adapted for fast mode (400 kBaud). Start Condition Received Interrupt Enable This bit enables the generation of a protocol interrupt if a start condition is detected. 0B The start condition interrupt is disabled. 1B The start condition interrupt is enabled. Repeated Start Condition Received Interrupt Enable This bit enables the generation of a protocol interrupt if a repeated start condition is detected. 0B The repeated start condition interrupt is disabled. 1B The repeated start condition interrupt is enabled. CTR[16] ACK00 CTR[17] STIM CTR[18] SCR IEN CTR[19] RSCR IEN User's Manual USIC, UM_V0.2D5 19-176 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel Table 19-23 Signification of PCRL/H Bits for IIC (cont'd) Bit CTR[20] Alias PCR IEN Description Stop Condition Received Interrupt Enable This bit enables the generation of a protocol interrupt if a stop condition is detected. 0B The stop condition interrupt is disabled. 1B The stop condition interrupt is enabled. Non-Acknowledge Interrupt Enable This bit enables the generation of a protocol interrupt if a nonacknowledge is detected by a master. The non-acknowledge interrupt is disabled. 0B 1B The non-acknowledge interrupt is enabled. Arbitration Lost Interrupt Enable This bit enables the generation of a protocol interrupt if an arbitration lost event is detected. 0B The arbitration lost interrupt is disabled. 1B The arbitration lost interrupt is enabled. Slave Read Request Interrupt Enable This bit enables the generation of a protocol interrupt if a slave read request is detected. 0B The slave read request interrupt is disabled. 1B The slave read request interrupt is enabled. Error Interrupt Enable This bit enables the generation of a protocol interrupt if an IIC error condition is detected (indicated by PSR.ERR or PSR.WTDF). 0B The error interrupt is disabled. 1B The error interrupt is enabled. CTR[21] NACK IEN CTR[22] ARL IEN CTR[23] SRR IEN CTR[24] ERR IEN User's Manual USIC, UM_V0.2D5 19-177 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel Table 19-23 Signification of PCRL/H Bits for IIC (cont'd) Bit CTR[25] Alias S ACK DIS Description Slave Acknowledge Disable This bit disables the generation of an active acknowledge signal for a slave device (active acknowledge = 0 level). Once set by SW, it is automatically cleared with each (repeated) start condition. If this bit is set after a byte has been received (indicated by an interrupt) but before the next acknowledge bit has started, the next acknowledge bit will be sent with passive level. This would indicate that the receiver does not accept more bytes. As a result, a minimum of 2 bytes will be received if the first receive interrupt is used to set this bit. 0B The generation of an active slave acknowledge is enabled (slave acknowledge with 0 level = more bytes can be received). 1B The generation of an active slave acknowledge is disabled (slave acknowledge with 1 level = reception stopped). Hardware Delay This bit field defines the delay used to compensate the internal treatment of the SCL signal (see Section 19.5.3) in order to respect the SDA hold time specified for the IIC protocol. Master Clock Enable This bit enables generation of the master clock MCLK (not directly used for IIC protocol, can be used as general frequency output). 0B The MCLK generation is disabled and MCLK is 0. 1B The MCLK generation is enabled. Reserved returns 0 if read; should be written with 0; CTR [29:26] HDEL CTR[31] MCLK others User's Manual USIC, UM_V0.2D5 19-178 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.5.5.2 Protocol Status Register The following PSR status bits or bit fields are available in IIC mode. Please note that the bits in register PSR are not cleared by HW. The row marked PI indicates which status bit can generate a protocol interrupt. The general interrupt status flags are described in the general interrupt chapter. Table 19-24 Signification of PSR Bits for IIC Bit ST[0] Alias SLSEL Description PI? Slave Select This bit indicates that this device has been selected as slave. 0B The device is not selected as slave. 1B The device is selected as slave. Wrong TDF Code Found This bit indicates that an unexpected/wrong TDF code has been found. A protocol interrupt can be generated if PCRH.ERRIEN = 1. 0B A wrong TDF code has not been found. 1B A wrong TDF code has been found. Start Condition Received This bit indicates that a start condition has been detected on the IIC bus lines. A protocol interrupt can be generated if PCRH.SCRIEN = 1. 0B A start condition has not yet been detected. 1B A start condition has been detected. y ST[1] WTDF ST[2] SCR y ST[3] RSCR y Repeated Start Condition Received This bit indicates that a repeated start condition has been detected on the IIC bus lines. A protocol interrupt can be generated if PCRH.RSCRIEN = 1. A repeated start condition has not yet been detected. 0B 1B A repeated start condition has been detected. Stop Condition Received This bit indicates that a stop condition has been detected on the IIC bus lines. A protocol interrupt can be generated if PCRH.PCRIEN = 1. 0B A stop condition has not yet been detected. 1B A stop condition has been detected. y ST[4] PCR User's Manual USIC, UM_V0.2D5 19-179 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel Table 19-24 Signification of PSR Bits for IIC (cont'd) Bit ST[5] Alias NACK Description PI? Non-Acknowledge Received y This bit indicates that a non-acknowledge has been received in master mode. This bit is not set in slave mode. A protocol interrupt can be generated if PCRH.NACKIEN = 1. 0B A non-acknowledge has not been received. 1B A non-acknowledge has been received. Arbitration Lost This bit indicates that an arbitration has been lost. A protocol interrupt can be generated if PCRH.ARLIEN = 1. 0B An arbitration has not been lost. 1B An arbitration has been lost. y ST[6] ARL ST[7] SRR Slave Read Request y This bit indicates that a slave read request has been detected. It becomes active to request the first data byte to be made available in the transmit buffer. For further consecutive data bytes, the transmit buffer issues more interrupts. For the end of the transfer, the master transmitter sends a stop condition. A protocol interrupt can be generated if PCRH.SRRIEN = 1. 0B A slave read request has not been detected. 1B A slave read request has been detected. Error y This bit indicates that an IIC error (frame format or TDF code) has been detected. A protocol interrupt can be generated if PCRH.ERRIEN = 1. 0B An IIC error has not been detected. 1B An IIC error has been detected. Reserved returns 0 if read; should be written with 0; - ST[8] ERR others User's Manual USIC, UM_V0.2D5 19-180 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.6 IIS Protocol This chapter describes how the USIC module handles the IIS protocol. This serial protocol can handle reception and transmission of synchronous data frames between a device operating in master mode and a device in slave mode. An IIS connection based on a USIC communication channel supports half-duplex and full-duplex data transfers. The IIS mode is selected by CCR.MODE = 0011B with CCFG.IIS = 1 (IIS mode is available). This chapter contains the following sections: * * * * * Introduction (see Section 19.6.1) General IIS issues (see Section 19.6.2) Master mode operation (see Section 19.6.3) Slave mode operation (see Section 19.6.4) Protocol registers (see Chapter 19.6.5) 19.6.1 Introduction The IIS protocol is a synchronous serial communication protocol mainly for audio and infotainment applications and refers to the Philips specification, 1986, revised June 5, 1996. 19.6.1.1 Signal Description A connection between an IIS master and an IIS slave is based on the following signals: * A shift clock signal SCK, generated by the transfer master. It is permanently generated while an IIS connection is established, also while no valid data bits are transferred. A word address signal WA (also named WS), generated by the transfer master. It indicates the beginning of a new data word and the targeted audio channel (e.g. left/ right). The word address output signal WA is available on all SELOx outputs if the WA generation is enabled (by PCR.WAGEN = 1 for the transfer master). The WA signal changes synchronously to the falling edges of the shift clock. If the transmitter is the IIS master device, it generates a master transmit slave receive data signal. The data changes synchronously to the falling edges of the shift clock. If the transmitter is the IIS slave device, it generates a master receive slave transmit data signal. The data changes synchronously to the falling edges of the shift clock. * * * The transmitter part and the receiver part of the USIC communication channel can be used together to establish a full-duplex data connection between an IIS master and a slave device. User's Manual USIC, UM_V0.2D5 19-181 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Table 19-25 IIS IO Signals IIS Mode master slave Receive Data Transmit Data Shift Clock output SCLKOUT Word Address output(s) SELOx input DIN, output DOUT handled by DX0 input DIN, output DOUT handled by DX0 Universal Serial Interface Channel input SCLKIN, input SELIN, handled by DX1 handled by DX2 USIC IIS communication master DOUT TBUF DIN RBUF WA generator SCLKOUT baud rate generator MCLKOUT DX0 SELOx master transmit slave receive master receive slave transmit word address (word select) shift clock USIC IIS communication slave DIN DX0 DOUT TBUF SELIN DX2 SCLKIN DX1 fsys (slave) RBUF master clock output synchronization clock input SCLKIN DX1 fsys (master) Figure 19-47 IIS Signals IIS_signals Two additional signals are available for the USIC IIS communication master: * A master clock output signal MCLKOUT with a fixed phase relation to the shift clock to support oversampling for audio components. It can also be used as master clock output of a communication network with synchronized IIS connections. A synchronization clock input SCLKIN for synchronization of the shift clock generation to an external frequency to support audio frequencies that can not be directly derived from the system clock fSYS of the communication master. It can be 19-182 V1.0, 2007-06 * User's Manual USIC, UM_V0.2D5 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel used as master clock input of a communication network with synchronized IIS connections. 19.6.1.2 Protocol Overview An IIS connection supports transfers for two different data frames via the same data line, e.g. a data frames for the left audio channel and a data frame for the right audio channel. The word address signal WA is used to distinguish between the different data frames. Each data frame can consist of several data words. In a USIC communication channel, data words are tagged for being transmitted for the left or for the right channel. Also the received data words contain a tag identifying the WA state when the data has been received. WA (WS) right channel left channel SCK MSB LSB MSB LSB DOUT 0 right data frame MSB LSB 0 left data frame MSB LSB 0 DIN X right data frame X left data frame X IIS_prot Figure 19-48 Protocol Overview 19.6.1.3 Transfer Delay The transfer delay feature allows the transfer of data (transmission and reception) with a programmable delay (counted in shift clock periods). SCK WA DATA without delay with delay 1 IIS_transfer_delay Figure 19-49 Transfer Delay for IIS User's Manual USIC, UM_V0.2D5 19-183 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.6.1.4 Connection of External Audio Components The IIS signals can be used to communicate with external audio devices (such as Codecs) or other audio data sources/destinations. USIC IIS MCLKOUT SCLKOUT WA DIN DOUT Audio-ADC MCLK_IN SCK_IN WA_IN SD_OUT R L Analog Inputs Audio-DAC MCLK_IN SCK_IN WA_IN SD_IN R L Analog Outputs IIS_Ext_Codecs Figure 19-50 Connection of External Audio Devices In some applications, especially for Audio-ADCs or Audio-DACs, a master clock signal is required with a fixed phase relation to the shift clock signal. The frequency of MCLKOUT is a multiple of the shift frequency SCLKOUT. This factor defines the oversampling factor of the external device (commonly used values: 256 or 384). User's Manual USIC, UM_V0.2D5 19-184 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.6.2 Operating the IIS This chapter contains IIS issues, that are of general interest and not directly linked to master mode or slave mode. 19.6.2.1 Frame Length and Word Length Configuration After each change of the WA signal, a complete data frame is intended to be transferred (frame length system word length). The number of data bits transferred after a change of signal WA is defined by SCTRH.FLE. A data frame can consist of several data words with a data word length defined by SCTRH.WLE. The changes of signal WA define the system word length as the number of SCLK cycles between two changes of WA (number of bits available for the right channel and same number available for the left channel). If the system word length is longer than the frame length defined by SCTRH.FLE, the additional bits are transmitted with passive data level (SCTRL.PDL). If the system word length is smaller than the device frame length, not all LSBs of the transmit data can be transferred. It is recommended to program bits WLEMD, FLEMD and SELMD in register TCSRL to 0. 19.6.2.2 Automatic Shadow Mechanism The baud rate and shift control setting are internally kept constant while a data frame is transferred by an automatic shadow mechanism. The registers can be programmed all the time with new settings that are taken into account for the next data frame. During a data frame, the applied (shadowed) setting is not changed, although new values have been written after the start of the data frame. The setting is internally "frozen" with the start of each data frame. Although this shadow mechanism being implemented, it is recommended to change the baud rate and shift control setting only while the IIS protocol is switched off. 19.6.2.3 Mode Control Behavior In IIS mode, the following kernel modes are supported: * * Run Mode 0/1: Behavior as programmed, no impact on data transfers. Stop Mode 0/1: Bit PCRL.WAGEN is internally considered as 0 (the bit itself is not changed). If WAGEN = 1, then the current system word cycle is finished and then the WA generation is stopped, but PSR.END is not set. The complete data frame is finished before entering stop mode, including a possible delay due to PCRH.TDEL. When leaving a stop mode with WAGEN = 1, the WA generation starts from the beginning. User's Manual USIC, UM_V0.2D5 19-185 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.6.2.4 Transfer Delay The transfer delay can be used to synchronize a data transfer to an event (e.g. a change of the WA signal). This event has to be synchronously generated to the falling edge of the shift clock SCK (like the change of the transmit data), because the input signal for the event is directly sampled in the receiver (as a result, the transmitter can use the detection information with its next edge). Event signals that are asynchronous to the shift clock while the shift clock is running must not be used. In the example in Figure 19-49, the event (change of signal WA) is generated by the transfer master and as a result, is synchronous to the shift clock SCK. With the rising edge of SCK, signal WA is sampled and checked for a change. If a change is detected, a transfer delay counter TDC is automatically loaded with its programmable reload value (PCRH.TDEL), otherwise it is decremented with each rising edge of SCK until it reaches 0, where it stops. The transfer itself is started if the value of TDC has become 0. This can happen under two conditions: * * TDC is reloaded with a PCRH.TDEL = 0 when the event is detected TDC has reached 0 while counting down The transfer delay counter is internal to the IIS protocol pre-processor and can not be observed by SW. The transfer delay in SCK cycles is given by PCRH.TDEL+1. In the example in Figure 19-51, the reload value PCRH.TDEL for TDC is 0. When the samples taken on receiver side show the change of the WA signal, the counter TDC is reloaded. If the reload value is 0, the data transfer starts with 1 shift clock cycle delay compared to the change of WA. SCK WA s s s s s s s TDC 0 0 0 DOUT x D0 D1 x D0 sampled DIN D0 s = sampling of WA signal D1 D0 IIS_transfer_delay_1 Figure 19-51 Transfer Delay with Delay 1 User's Manual USIC, UM_V0.2D5 19-186 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel The ideal case without any transfer delay is shown in Figure 19-52. The WA signal changes and the data output value become valid at the same time. This implies that the transmitter "knows" in advance that the event signal will change with the next rising edge of TCLK. This is achieved by delaying the data transmission after the previously detected WA change the system word length minus 1. SCK WA s s s s s s s TDC 1 0 n n-1 n-2 1 0 n DOUT x D0 D1 D2 x D0 D1 sampled DIN D0 D1 D0 D1 s = sampling of WA signal IIS_transfer_delay_0 Figure 19-52 Transfer Delay with 0 Delay If the end of the transfer delay is detected simultaneously to change of WA, the transfer is started and the delay counter is reloaded with PCRH.TDEL. This allows to run the USIC as IIS device without any delay. In this case, internally the delay from the previous event elapses just at the moment when a new event occurs. If PCRH.TDEL is set to a value bigger than the system word length, no transfer takes place. 19.6.2.5 Parity Mode Parity generation is not supported in IIS mode and bit field CCR.PM = 00B has to be programmed. 19.6.2.6 Transfer Mode In IIS mode, bit field SCTRL.TRM = 11B has to be programmed to allow data transfers. Setting SCTRL.TRM = 00B disables and stops the data transfer immediately. User's Manual USIC, UM_V0.2D5 19-187 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.6.2.7 Data Transfer Interrupt Handling The data transfer interrupts indicate events related to IIS frame handling. * * * Transmit buffer interrupt TBI: Bit PSR.TBIF is set after the start of first data bit of a data word. Transmit shift interrupt TSI: Bit PSR.TSIF is set after the start of the last data bit of a data word. Receiver start interrupt RSI: Bit PSR.RSIF is set after the reception of the first data bit of a data word. With this event, bit TCSRL.TDV is cleared and new data can be loaded to the transmit buffer. Receiver interrupt RI and alternative interrupt AI: Bit PSR.RIF is set at after the reception of the last data bit of a data word with WA = 0. Bit RBUFSR.SOF indicates whether the received data word has been the first data word of a new data frame. Alternative interrupt AI: Bit PSR.AIF is set at after the reception of the last data bit of a data word with WA = 1. Bit RBUFSR.SOF indicates whether the received data word has been the first data word of a new data frame. * * 19.6.2.8 Protocol-Related Argument and Error In order to distinguish between data words received for the left or the right channel, the IIS protocol pre-processor samples the level of the WA input (just after the WA transition) and propagates it as protocol-related error (although it is not an error, but an indication) to the receive buffer status register at the bit position RBUFSR[9]. This bit position defines if either a standard receive interrupt (if RBUFSR[9] = 0) or an alternative receive interrupt (if RBUFSR[9] = 1) becomes activated when a new data word has been received. Incoming data can be handled by different interrupts or DMA mechanisms for the left and the right channel if the corresponding events are directed to different interrupt nodes. Flag PAR is always 0. 19.6.2.9 Transmit Data Handling The IIS protocol pre-processor allows to distinguish between the left and the right channel for data transmission. Therefore, bit TCSRL.WA indicates on which channel the data in the buffer will be transmitted. If TCSRL.WA = 0, the data will be transmitted after a falling edge of WA. If TCSRL.WA = 1, the data will be transmitted after a rising edge of WA. The WA value sampled after the WA transition is considered to distinguish between both channels (referring to PSR.WA). Bit TCSRL.WA can be automatically updated by the transmit control information TCI[4] for each data word if TCSRL.WAMD = 1. In this case, data written to TBUF[15:0] (or IN[15:0] if a FIFO data buffer is used) is considered as left channel data, whereas data User's Manual USIC, UM_V0.2D5 19-188 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel written to TBUF[31:16] (or IN[31:16] if a FIFO data buffer is used) is considered as right channel data. 19.6.2.10 Receive Buffer Handling If a receive FIFO buffer is available (CCFG.RB = 1) and enabled for data handling (RBCTRH.SIZE > 0), it is recommended to set RBCTRH.RCIM = 11B in IIS mode. This leads to an indication that the data word has been the first data word of a new data frame if bit OUTRH.RCI[0] = 1, and the channel indication by the sampled WA value is given by OUTRH.RCI[4]. The standard receive buffer event and the alternative receive buffer event can be used for the following operation in RCI mode (RBCTRH.RNM = 1): * * A standard receive buffer event indicates that a data word can be read from OUTRL that belongs to a data frame started when WA = 0. An alternative receive buffer event indicates that a data word can be read from OUTRL that belongs to a data frame started when WA = 1. 19.6.2.11 Loop-Delay Compensation The synchronous signaling mechanism of the IIS protocol being similar to the one of the SSC protocol, the closed-loop delay has to be taken into account for the application setup. In IIS mode, loop-delay compensation in master mode is also possible to achieve higher baud rates. Please refer to the more detailed description in the SSC chapter. User's Manual USIC, UM_V0.2D5 19-189 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.6.3 * Operating the IIS in Master Mode In order to operate the IIS in master mode, the following issues have to be considered: Select IIS mode: It is recommended to configure all parameters of the IIS that do not change during run time while CCR.MODE = 0000B. Bit field SCTRL.TRM = 11B has to be programmed. The configuration of the input stages has to be done while CCR.MODE = 0000B to avoid unintended edges of the input signals and the IIS mode can be enabled by CCR.MODE = 0011B afterwards. Pin connection for data transfer: Establish a connection of input stage DX0 with the selected receive data input pin (DIN) with DX0CR.INSW = 1. Configure a transmit data output pin (DOUT) for a transmitter. The data shift unit allowing full-duplex data transfers based on the same WA signal, the values delivered by the DX0 stage are considered as data bits (receive function can not be disabled independently from the transmitter). To receive IIS data, the transmitter does not necessarily need to be configured (no assignment of DOUT signal to a pin). Baud rate generation: The desired baud rate setting has to be selected, comprising the fractional divider and the baud rate generator. Bit DX1CR.INSW = 0 has to be programmed to use the baud rate generator output SCLK directly as input for the data shift unit. Configure a shift clock output pin with the inverted signal SCLKOUT without additional delay (BRGH.SCLKCFG = 01B). Word address WA generation: The WA generation has to be enabled by setting PCRL.WAGEN = 1 and the programming of the number of shift clock cycles between the changes of WA. Bit DX2CR.INSW = 0 has to be programmed to use the WA generator as input for the data shift unit. Configure WA output pin for signal SELOx if needed. Data format configuration: The word length, the frame length, and the shift direction have to be set up according to the application requirements by programming the registers SCTRL and SCTRH. Generally, the MSB is shifted first (SCTRL.SDIR = 1). Bit TCSRL.WAMD can be set to use the transmit control information TCI[4] to distinguish the data words for transmission while WA = 0 or while WA = 1. * * * * 19.6.3.1 Baud Rate Generation The baud rate is defined by the frequency of the SCLK signal (one period of fSCLK represents one data bit). If the fractional divider mode is used to generate fPIN, there can be an uncertainty of one period of fSYS for fPIN. This uncertainty does not accumulate over several SCLK cycles. As a consequence, the average frequency is reached, whereas the duty cycle of 50% of User's Manual USIC, UM_V0.2D5 19-190 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel the SCLK and MCLK signals can vary by one period of fSYS. In IIS applications, where the phase relation between the optional MCLK output signal and SCLK is not relevant, SCLK can be based on the frequency fPIN (BRGL.PPPEN = 0). In the case that a fixed phase relation between the MCLK signal and SCLK is required (e.g. when using MCLK as clock reference for external devices), the additional divider by 2 stage has to be taken into account (BRGL.PPPEN = 1). This division is due to the fact that signal MCLK toggles with each cycle of fPIN. Signal SCLK is then based on signal MCLK, see Figure 19-53. The adjustable integer divider factor is defined by bit field BRGH.PDIV. (19.12) f 1 PIN --------- x ----------------------2 PDIV + 1 = f PIN 1 ----------- x ----------------------2 x 2 PDIV + 1 if if PPPEN = 0 PPPEN = 1 f SCLK Note: In the IIS protocol, the master (unit generating the shift clock and the WA signal) changes the status of its data and WA output line with the falling edge of SCK. The slave transmitter also has to transmit on falling edges. The sampling of the received data is done with the rising edges of SCLK. The input stage DX1 and the SCLKOUT have to be programmed to invert the shift clock signal to fit to the internal signals. 19.6.3.2 WA Generation The word address (or word select) line WA regularly toggles after N cycles of signal SCLK. The time between the changes of WA is called system word length and can be programmed by using the following bit fields. In IIS master mode, the system word length is defined by: * * * BRGL.CTQSEL = 10B to base the WA toggling on SCLK BRGL.PCTQ to define the number N of SCLK cycles per system word length BRGL.DCTQ to define the number N of SCLK cycles per system word length (19.13) N = ( PCTQ + 1 ) x ( DCTQ + 1 ) User's Manual USIC, UM_V0.2D5 19-191 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.6.3.3 Master Clock Output The master clock signal MCLK can be generated by the master of the IIS transfer (BRGL.PPPEN = 1). It is used especially to connect external Codec devices. It can be configured by bit BRGH.MCLKCFG in its polarity to become the output signal MCLKOUT. 1/2 * SCLK = PDIV * MCLK 1/2 * SCLK = PDIV * MCLK zoom in fPIN MCLK SCLK MCLK SCLK transmitter DOUT receiver sampled DIN D(n) D(n+1) D(n) 1 period of SCLK = 1 data bit length D(n+1) IIS_MCLK_SCLK Figure 19-53 MCLK and SCLK for IIS User's Manual USIC, UM_V0.2D5 19-192 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.6.3.4 Protocol Interrupt Events The following protocol-related events are generated in IIS mode and can lead to a protocol interrupt. Please note that the bits in register PSR are not all automatically cleared by HW and have to be cleared by SW in order to monitor new incoming events. * WA rising/falling edge events: The WA generation block indicates two events that are monitored in register PSR. Flag PSR.WAFE is set with the falling edge, flag PSR.WARE with the rising edge of the WA signal. A protocol interrupt can be generated if PCRL.WAFEIEN = 1 for the falling edge, similar for PCRL.WAREIEN = 1 for a rising edge. WA end event: The WA generation block also indicates when it has stopped the WA generation after it has been disabled by writing PCRL.WAGEN = 0. A protocol interrupt can be generated if PCRL.ENDIEN = 1. DX2T event: An activation of the trigger signal DX2T is indicated by PSR.DX2TEV = 1 and can generate a protocol interrupt if PCRL.DX2TIEN = 1. This event can be evaluated instead of the WA rising/falling events if a delay compensation like in SSC mode (for details, refer to corresponding SSC section) is used. * * User's Manual USIC, UM_V0.2D5 19-193 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.6.4 * Operating the IIS in Slave Mode In order to operate the IIS in slave mode, the following issues have to be considered: Select IIS mode: It is recommended to configure all parameters of the IIS that do not change during run time while CCR.MODE = 0000B. Bit field SCTRL.TRM = 11B has to be programmed. The configuration of the input stages has to be done while CCR.MODE = 0000B to avoid unintended edges of the input signals and the IIS mode can be enabled by CCR.MODE = 0011B afterwards. Pin connection for data transfer: Establish a connection of input stage DX0 with the selected receive data input pin (DIN) with DX0CR.INSW = 1. Configure a transmit data output pin (DOUT) for a transmitter. The data shift unit allowing full-duplex data transfers based on the same WA signal, the values delivered by the DX0 stage are considered as data bits (receive function can not be disabled independently from the transmitter). To receive IIS data, the transmitter does not necessarily need to be configured (no assignment of DOUT signal to a pin). Pin connection for shift clock: Establish a connection of input stage DX1 with the selected shift clock input pin (SCLKIN) with DX1CR.INSW = 1 and with inverted polarity (DX1CR.DPOL = 1). Pin connection for WA input: Establish a connection of input stage DX2 with the WA input pin (SELIN) with DX2CR.INSW = 1. Baud rate generation: The baud rate generator is not needed and can be switched off by the fractional divider. WA generation: The WA generation is not needed and can be switched off (PCRL.WAGEN = 0). * * * * * 19.6.4.1 Protocol Events and Interrupts The following protocol-related event is generated in IIS mode and can lead to a protocol interrupt. Please note that the bits in register PSR are not all automatically cleared by HW and have to be cleared by SW in order to monitor new incoming events. * * WA rising/falling/end events: The WA generation being switched off, these events are not available. DX2T event: An activation of the trigger signal DX2T is indicated by PSR.DX2TEV = 1 and can generate a protocol interrupt if PCRL.DX2TIEN = 1. User's Manual USIC, UM_V0.2D5 19-194 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.6.5 IIS Protocol Registers In IIS mode, the bits in the registers PCRL, PCRH and PSR handle IIS related information. 19.6.5.1 Protocol Control Registers The following PCRL/PCRH control bits or bit fields are available in IIS mode. Table 19-26 Signification of PCRL/H Bits for IIS Bit CTR[0] Alias WAGEN Description WA Generation Enable This bit enables/disables the generation of word address control output signal WA. 0B The IIS can be used as slave. The generation of the word address signal is disabled. The output signal WA is 0. The MCLKO signal generation depends on PCRH.MCLK. 1B The IIS can be used as master. The generation of the word address signal is enabled. The signal starts with a 0 after being enabled. The generation of MCLK is enabled, independent of PCRH.MCLK. After clearing WAGEN, the USIC module stops the generation of the WA signal within the next 4 WA periods. Data Transfers Enable This bit enables/disables the transfer of IIS frames as a reaction to changes of the input word address control line WA. 0B The changes of the WA input signal are ignored and no transfers take place. 1B Transfers are enabled. Select Inversion This bit defines if the polarity of the SELOx outputs in relation to the internally generated word address signal WA. 0B The SELOx outputs have the same polarity as the WA signal. 1B The SELOx outputs have the inverted polarity to the WA signal. CTR[1] DTEN CTR[2] SELINV User's Manual USIC, UM_V0.2D5 19-195 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel Table 19-26 Signification of PCRL/H Bits for IIS (cont'd) Bit CTR[4] Alias WAFE IEN Description WA Falling Edge Interrupt Enable This bit enables/disables the activation of a protocol interrupt when a falling edge of WA has been generated. 0B A protocol interrupt is not activated if a falling edge of WA is generated. 1B A protocol interrupt is activated if a falling edge of WA is generated. WA Rising Edge Interrupt Enable This bit enables/disables the activation of a protocol interrupt when a rising edge of WA has been generated. 0B A protocol interrupt is not activated if a rising edge of WA is generated. 1B A protocol interrupt is activated if a rising edge of WA is generated. END Interrupt Enable This bit enables/disables the activation of a protocol interrupt when the WA generation stops after clearing PCR.WAGEN (complete system word length is processed before stopping). 0B A protocol interrupt is not activated. 1B A protocol interrupt is activated. DX2T Interrupt Enable This bit enables/disables the generation of a protocol interrupt if the DX2T signal becomes activated (indicated by PSR.DX2TEV = 1). 0B A protocol interrupt is not generated if DX2T is active. 1B A protocol interrupt is generated if DX2T is active. Transfer Delay This bit field defines the transfer delay when an event is detected. If bit field TDEL = 0, the additional delay functionality is switched off and a delay of one shift clock cycle is introduced. Master Clock Enable This bit enables generation of the master clock MCLK. 0B The MCLK generation is disabled and MCLK is 0. 1B The MCLK generation is enabled. Reserved returns 0 if read; should be written with 0; CTR[5] WARE IEN CTR[6] END IEN CTR[15] DX2T IEN CTR [21:16] TDEL CTR[31] MCLK others User's Manual USIC, UM_V0.2D5 19-196 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.6.5.2 Protocol Status Register PSR The following PSR status bits or bit fields are available in IIS mode. Please note that the bits in register PSR are not cleared by HW. The row marked PI indicates which status bit can generate a protocol interrupt in IIS mode. The general interrupt status flags are described in the general interrupt chapter. Table 19-27 Signification of PSR Bits for IIS Bit ST[0] Alias WA Description PI? Word Address This bit indicates the status of the WA input signal, sampled after a transition of WA has been detected. This information is forwarded to the corresponding bit position RBUFSR[9] to distinguish between data received for the right and the left channel. 0B WA has been sampled 0. 1B WA has been sampled 1. DX2S Status This bit indicates the current status of the DX2S signal, which is used as word address signal WA. 0B DX2S is 0. 1B DX2S is 1. y DX2T Event Detected This bit indicates that the DX2T signal has been activated. In IIS slave mode, an activation of DX2T generates a protocol interrupt if PCRL.DX2TIEN = 1. 0B The DX2T signal has not been activated. The DX2T signal has been activated. 1B WA Falling Edge Event y This bit indicates that a falling edge of the WA output signal has been generated. This event generates a protocol interrupt if PCRL.WAFEIEN = 1. 0B A WA falling edge has not been generated. 1B A WA falling edge has been generated. WA Rising Edge Event y This bit indicates that a rising edge of the WA output signal has been generated. This event generates a protocol interrupt if PCRL.WAREIEN = 1. 0B A WA rising edge has not been generated. 1B A WA rising edge has been generated. ST[1] DX2S ST[3] DX2T EV ST[4] WAFE ST[5] WARE User's Manual USIC, UM_V0.2D5 19-197 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel Table 19-27 Signification of PSR Bits for IIS (cont'd) Bit ST[6] Alias END Description PI? WA Generation End y This bit indicates that the WA generation has ended after clearing PCRL.WAGEN. This bit should be cleared by SW before clearing WAGEN. 0B The WA generation has not yet ended (if it is running and WAGEN has been cleared). 1B The WA generation has ended (if it has been running). Reserved others User's Manual USIC, UM_V0.2D5 19-198 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.7 USIC Implementation in XC2000 This section describes the implementation of the USIC channels in the XC2000. It contains details about the: * * * * * * * * * * Implementation overview (see Section 19.7.1) Channel features (see Section 19.7.2) Address map (see Section 19.7.3) Interrupt control registers (see Section 19.7.4) Input and output signals of U0C0 (see Section 19.7.5.1) Input and output signals of U0C1 (see Section 19.7.5.2) Input and output signals of U1C0 (see Section 19.7.5.3) Input and output signals of U1C1 (see Section 19.7.5.4) Input and output signals of U2C0 (see Section 19.7.5.5) Input and output signals of U2C1 (see Section 19.7.5.6) 19.7.1 Implementation Overview The XC2000 device contains three identical USIC modules (USIC0, USIC1 and USIC2) with 2 communication channels each. The address range between 400H and 7FFH of each USIC module is reserved. USIC0 module base + 0x1F F bas e + 0x 200 base + 0x3F F bas e + 0x 000 bas e + 0x 000 USIC1 module base + 0x1F F bas e + 0x 200 base + 0x3F F bas e + 0x 000 USIC2 module base + 0x1F F bas e + 0x 200 base + 0x3F F channel U0C0 channel U0C1 channel U1C0 channel U1C1 channel U2C0 bus interface base = 0x 20 4000 bus interface base = 0x 20 4800 bus interface base = 0x 20 5000 LX Bus USIC_module_impl Figure 19-54 USIC Module Structure in XC2000 User's Manual USIC, UM_V0.2D5 19-199 V1.0, 2007-06 channel U2C1 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.7.2 Channel Features The USIC channels in the XC2000 support the following functionality: Table 19-28 USIC Module Feature Set Channel ASC LIN SSC IIC IIS FIFO Protocol Support Protocol Protocol Protocol Buffer Entries SELOx1) USIC Module 0 U0C0 U0C1 yes yes yes yes yes yes yes yes yes yes 64 shared 8 4 USIC Module 1 U1C0 U1C1 yes yes yes yes yes yes yes yes yes yes 64 shared 8 5 USIC Module 2 U2C0 U2C1 1) yes yes yes yes yes yes yes yes yes yes 64 shared 6 2 This number refers to the maximum number of signals available in the 144 pin package. 19.7.3 Address Map The registers of the USIC communication channels are available at the following base addresses. The exact register address is given by the relative address of the register (given in Table 19-3) plus the channel base address (given in Table 19-29). Table 19-29 Registers Address Space Module U0C0 U0C1 U1C0 U1C1 U2C0 U2C1 Base Address 20 4000H 20 4200H 20 4800H 20 4A00H 20 5000H 20 5200H End Address 20 41FFH 20 43FFH 20 49FFH 20 4BFFH 20 51FFH 20 53FFH Note User's Manual USIC, UM_V0.2D5 19-200 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.7.4 Interrupt Control Registers Each USIC channel provides 4 service request outputs SR[3:0] (not all of them are necessarily connected to independent interrupt registers UxCy_nIC). The table below shows the assignment of the interrupt control registers to the service request outputs. Each USIC communication channel is connected to 3 dedicated interrupt control registers (connected to UxCy_SR[2:0], e.g. one for transmission, one for reception, the third one for protocol or error handling, or for the alternative receive events). A fourth interrupt control register per communication channel (connected to UxCy_SR3) is shared with module CC2. The interrupt control registers are located in the SFR area. They are described in the general interrupt chapter. Table 19-30 USIC Interrupt Control Registers Short Name U0CO_0IC U0CO_1IC U0CO_2IC Description Interrupt Control Register for SR0 of USIC0 channel 0 Interrupt Control Register for SR1 of USIC0 channel 0 Interrupt Control Register for SR2 of USIC0 channel 0 Interrupt Control Register for SR3 of USIC0 channel 0, shared with CC2, see SCU_ISSR.4 U0C1_0IC U0C1_1IC U0C1_2IC Interrupt Control Register for SR0 of USIC0 channel 1 Interrupt Control Register for SR1 of USIC0 channel 1 Interrupt Control Register for SR2 of USIC0 channel 1 Interrupt Control Register for SR3 of USIC0 channel 1, shared with CC2, see SCU_ISSR.5 U1CO_0IC U1CO_1IC U1CO_2IC Interrupt Control Register for SR0 of USIC1 channel 0 Interrupt Control Register for SR1 of USIC1 channel 0 Interrupt Control Register for SR2 of USIC1 channel 0 Interrupt Control Register for SR3 of USIC1 channel 0, shared with CC2, see SCU_ISSR.6 U1C1_0IC U1C1_1IC U1C1_2IC Interrupt Control Register for SR0 of USIC1 channel 1 Interrupt Control Register for SR1 of USIC1 channel 1 Interrupt Control Register for SR2 of USIC1 channel 1 Interrupt Control Register for SR3 of USIC1 channel 1, shared with CC2, see SCU_ISSR.7 U2CO_0IC U2CO_1IC User's Manual USIC, UM_V0.2D5 Interrupt Control Register for SR0 of USIC2 channel 0 Interrupt Control Register for SR1 of USIC2 channel 0 19-201 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel Table 19-30 USIC Interrupt Control Registers (cont'd) Short Name U2CO_2IC Description Interrupt Control Register for SR2 of USIC2 channel 0 Interrupt Control Register for SR3 of USIC2 channel 1, shared with CC2, see SCU_ISSR.12 U2C1_0IC U2C1_1IC U2C1_2IC Interrupt Control Register for SR0 of USIC2 channel 1 Interrupt Control Register for SR1 of USIC2 channel 1 Interrupt Control Register for SR2 of USIC2 channel 1 Interrupt Control Register for SR3 of USIC2 channel 1, shared with CC2, see SCU_ISSR.13 User's Manual USIC, UM_V0.2D5 19-202 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.7.5 Input/Output Connections The following tables show the pin assignment of the USIC channels in the XC2000 device. Naming convention: UxCy refers to USIC module x channel y. The following sections refer to the communication signals, whereas the connections of the service request outputs SR[3:0] to the interrupt control registers of each communication channel to the interrupt control registers is given in Section 19.7.4. 19.7.5.1 USIC Module 0 Channel 0 The signals of USIC module 0 channel 0 have the prefix U0C0_. Table 19-31 USIC0 Channel 0 (U0C0) I/O Connections Signal Data Inputs DX0A DX0B DX0C DX0D DX0E DX0F DX0G Clock Inputs DX1A DX1B DX1C DX1D DX1E DX1F DX1G Control Inputs DX2A DX2B DX2C P10.3 P10.4 P10.10 I I I shift control input shift control input shift control input P10.1 P10.2 P10.8 0 0 0 U0C0_ SCLKOUT I I I I I I I shift clock input shift clock input shift clock input shift clock input shift clock input shift clock input loop back shift clock input P10.0 P10.1 P10.6 P7.4 P2.3 P2.4 U0C0_ DOUT I I I I I I I shift data input shift data input shift data input shift data input shift data input shift data input loop back data shift input from/to I/O1) Can be used to/as User's Manual USIC, UM_V0.2D5 19-203 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel Table 19-31 USIC0 Channel 0 (U0C0) I/O Connections (cont'd) Signal DX2D DX2E DX2F DX2G Data Outputs DOUT DOUT DOUT DOUT Clock Outputs MCLKOUT SCLKOUT SCLKOUT SELO0 SELO0 SELO1 SELO2 SELO3 SELO3 SELO4 SELO4 SELO4 SELO5 SELO6 SELO7 DX0INS DX0INS P10.8 P2.5 P10.2 P2.6 P10.10 P2.7 P2.11 P2.10 P10.4 P3.4 P10.9 P2.12 P3.5 P3.6 P3.7 ERU_0A2 O O O O O O O O O O O O O O O O master clock output, e.g. for IIS shift clock output shift clock output shift control output 0 shift control output 0 shift control output 1 shift control output 2 shift control output 3 shift control output 3 shift control output 4 shift control output 4 shift control output 4 shift control output 5 shift control output 6 shift control output 7 external interrupt input for ERU (SCU) single wire ASC collision detection 19-204 V1.0, 2007-06 from/to P2.6 CC2_8 CCU60_ T13_PM U0C0_ SELO0 P2.3 P7.3 P10.1 P10.6 I/O1) Can be used to/as I I I I shift control input input for transmit data validation input for transmit data validation loop back shift control input O O O O shift data output shift data output shift data output shift data output Control Outputs System Related Outputs U0C0_DX1F O User's Manual USIC, UM_V0.2D5 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel Table 19-31 USIC0 Channel 0 (U0C0) I/O Connections (cont'd) Signal DX1INS DX2INS DOUT SCLKOUT SELO0 1) from/to ERU_0A3 I/O1) Can be used to/as O O external interrupt input for ERU (SCU) loop back shift data output loop back shift clock output loop back shift control output U0C0 Loop Back Outputs U0C0_DX0G O U0C0_DX1G O U0C0_DX2G O Input/output for U0C0. User's Manual USIC, UM_V0.2D5 19-205 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.7.5.2 USIC Module 0 Channel 1 The signals of USIC module 0 channel 1 have the prefix U0C1_. Table 19-32 USIC0 Channel 1 (U0C1) I/O Connections Signal Data Inputs DX0A DX0B DX0C DX0D DX0E DX0F DX0G Clock Inputs DX1A DX1B DX1C DX1D DX1E DX1F DX1G Control Inputs DX2A DX2B DX2C DX2D DX2E DX2F DX2G P10.3 P10.4 P2.7 0 RTC_ T14INT CCU60_ T13_PM U0C1_ SELO0 I I I I I I I shift control input shift control input shift control input shift control input input for transmit data validation input for transmit data validation loop back shift control input P10.10 P10.5 P10.15 P2.8 0 0 U0C1_ SCLKOUT I I I I I I I shift clock input shift clock input shift clock input shift clock input shift clock input shift clock input loop back shift clock input P10.0 P10.7 P10.14 0 P2.10 P7.3 U0C1_ DOUT I I I I I I I shift data input shift data input shift data input shift data input shift data input shift data input loop back data shift input from/to I/O1) Can be used to/as User's Manual USIC, UM_V0.2D5 19-206 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel Table 19-32 USIC0 Channel 1 (U0C1) I/O Connections (cont'd) Signal Data Outputs DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT Clock Outputs MCLKOUT SCLKOUT SCLKOUT SCLKOUT SELO0 SELO0 SELO1 SELO2 SELO3 SELO4 SELO5 SELO6 SELO7 DX0INS DX0INS DX1INS DX2INS P10.9 P2.8 P7.4 P10.5 P2.7 P10.8 P2.6 P2.11 P2.12 ERU_0B2 ERU_0B3 O O O O O O O O O O O O O O O O external interrupt input for ERU (SCU) master clock output, e.g. for IIS shift clock output shift clock output shift clock output shift control output 0 shift control output 0 shift control output 1 shift control output 2 shift control output 3 shift control output 4 shift control output 5 shift control output 6 shift control output 7 external interrupt input for ERU (SCU) single wire ASC collision detection P2.9 P2.10 P7.3 P7.4 P10.0 P10.7 P10.14 P10.15 O O O O O O O O shift data output shift data output shift data output shift data output shift data output shift data output shift data output shift data output from/to I/O1) Can be used to/as Control Outputs System Related Outputs U0C1_DX1F O U0C1 Loop Back Outputs User's Manual USIC, UM_V0.2D5 19-207 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel Table 19-32 USIC0 Channel 1 (U0C1) I/O Connections (cont'd) Signal DOUT SCLKOUT SELO0 1) from/to I/O1) Can be used to/as loop back shift data output loop back shift clock output loop back shift control output U0C1_DX0G O U0C1_DX1G O U0C1_DX2G O Input/output for U0C1. User's Manual USIC, UM_V0.2D5 19-208 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.7.5.3 USIC Module 1 Channel 0 The signals of USIC module 1 channel 0 have the prefix U1C0_. Table 19-33 USIC1 Channel 0 (U1C0) I/O Connections Signal Data Inputs DX0A DX0B DX0C DX0D DX0E DX0F DX0G Clock Inputs DX1A DX1B DX1C DX1D DX1E DX1F DX1G Control Inputs DX2A DX2B DX2C DX2D DX2E DX2F DX2G Data Outputs User's Manual USIC, UM_V0.2D5 19-209 V1.0, 2007-06 from/to P0.0 P0.1 P10.12 P10.13 ESR0 ESR1 U1C0_ DOUT P0.1 P0.2 P0.5 P10.11 P10.12 0 U1C0_ SCLKOUT P0.3 ESR0 ESR1 P10.6 CC2_9 CCU61_ T13_PM U1C0_ SELO0 I/O1) Can be used to/as I I I I I I I shift data input shift data input shift data input shift data input shift data input shift data input loop back data shift input I I I I I I I shift clock input shift clock input shift clock input shift clock input shift clock input shift clock input loop back shift clock input I I I I I I I shift control input shift control input shift control input shift control input input for transmit data validation input for transmit data validation loop back shift control input XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel Table 19-33 USIC1 Channel 0 (U1C0) I/O Connections (cont'd) Signal DOUT DOUT DOUT DOUT DOUT Clock Outputs MCLKOUT SCLKOUT SCLKOUT SELO0 SELO0 SELO1 SELO1 SELO2 SELO2 SELO3 SELO3 SELO4 SELO5 SELO6 SELO7 DX0INS DX0INS DX1INS DX2INS DOUT P1.0 P0.2 P10.11 P0.3 P10.6 P0.4 P10.14 P0.5 P10.15 P0.7 P10.13 P1.0 P1.1 P1.2 P1.3 ERU_1A2 ERU_3B0 ERU_1A3 O O O O O O O O O O O O O O O O O O master clock output, e.g. for IIS shift clock output shift clock output shift control output 0 shift control output 0 shift control output 1 shift control output 1 shift control output 2 shift control output 2 shift control output 3 shift control output 3 shift control output 4 shift control output 5 shift control output 6 shift control output 7 external interrupt input for ERU (SCU) single wire ASC collision detection external interrupt input for ERU (SCU) external interrupt input for ERU (SCU) loop back shift data output from/to P0.0 P0.1 P10.12 P10.13 P10.15 I/O1) Can be used to/as O O O O O shift data output shift data output shift data output shift data output shift data output Control Outputs System Related Outputs U1C0_DX1F O U1C0 Loop Back Outputs U1C0_DX0G O User's Manual USIC, UM_V0.2D5 19-210 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel Table 19-33 USIC1 Channel 0 (U1C0) I/O Connections (cont'd) Signal SCLKOUT SELO0 1) from/to I/O1) Can be used to/as loop back shift clock output loop back shift control output U1C0_DX1G O U1C0_DX2G O Input/output for U1C0. User's Manual USIC, UM_V0.2D5 19-211 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.7.5.4 USIC Module 1 Channel 1 The signals of USIC module 1 channel 1 have the prefix U1C1_. Table 19-34 USIC1 Channel 1 (U1C1) I/O Connections Signal Data Inputs DX0A DX0B DX0C DX0D DX0E DX0F DX0G Clock Inputs DX1A DX1B DX1C DX1D DX1E DX1F DX1G Control Inputs DX2A DX2B DX2C DX2D DX2E DX2F DX2G P0.4 ESR1 ESR2 P6.3 RTC_ T14INT CCU61_ T13_PM U1C1_ SELO0 I I I I I I I shift control input shift control input shift control input shift control input input for transmit data validation input for transmit data validation loop back shift control input P0.5 P0.6 P6.2 0 0 0 U1C1_ SCLKOUT I I I I I I I shift clock input shift clock input shift clock input shift clock input shift clock input shift clock input loop back shift clock input P0.6 P0.7 ESR1 ESR2 P6.0 0 U1C1_ DOUT I I I I I I I shift data input shift data input shift data input shift data input shift data input shift data input loop back data shift input from/to I/O1) Can be used to/as User's Manual USIC, UM_V0.2D5 19-212 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel Table 19-34 USIC1 Channel 1 (U1C1) I/O Connections (cont'd) Signal Data Outputs DOUT DOUT DOUT Clock Outputs MCLKOUT SCLKOUT SCLKOUT SELO0 SELO0 SELO1 SELO2 SELO3 SELO4 SELO5 SELO6 SELO7 DX0INS DX0INS DX1INS DX2INS DOUT SCLKOUT SELO0 1) from/to P0.6 P0.7 P6.1 P1.7 P0.5 P6.2 P0.4 P6.3 P0.3 P1.6 P1.5 P1.4 ERU_1B2 ERU_1B3 I/O1) Can be used to/as O O O O O O O O O O O O O O O O O O external interrupt input for ERU (SCU) loop back shift data output loop back shift clock output loop back shift control output shift data output shift data output shift data output master clock output, e.g. for IIS shift clock output shift clock output shift control output 0 shift control output 0 shift control output 1 shift control output 2 shift control output 3 shift control output 4 shift control output 5 shift control output 6 shift control output 7 external interrupt input for ERU (SCU) single wire ASC collision detection Control Outputs System Related Outputs U1C1_DX1F O U1C1 Loop Back Outputs U1C1_DX0G O U1C1_DX1G O U1C1_DX2G O Input/output for U1C1. User's Manual USIC, UM_V0.2D5 19-213 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.7.5.5 USIC Module 2 Channel 0 The signals of USIC module 2 channel 0 have the prefix U2C0_. Table 19-35 USIC2 Channel 0 (U2C0) I/O Connections Signal Data Inputs DX0A DX0B DX0C DX0D DX0E DX0F DX0G Clock Inputs DX1A DX1B DX1C DX1D DX1E DX1F DX1G Control Inputs DX2A DX2B DX2C DX2D DX2E DX2F DX2G Data Outputs User's Manual USIC, UM_V0.2D5 19-214 V1.0, 2007-06 from/to P3.0 P3.1 P1.5 P1.6 P9.5 0 U2C0_ DOUT P3.0 P3.2 P1.7 P9.7 0 0 U2C0_ SCLKOUT P3.3 P1.4 0 0 CC2_10 CCU62_ T13_PM U2C0_ SELO0 I/O1) Can be used to/as I I I I I I I shift data input shift data input shift data input shift data input shift data input shift data input loop back data shift input I I I I I I I shift clock input shift clock input shift clock input shift clock input shift clock input shift clock input loop back shift clock input I I I I I I I shift control input shift control input shift control input shift control input input for transmit data validation input for transmit data validation loop back shift control input XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel Table 19-35 USIC2 Channel 0 (U2C0) I/O Connections (cont'd) Signal DOUT DOUT DOUT DOUT DOUT Clock Outputs MCLKOUT SCLKOUT SCLKOUT SELO0 SELO1 SELO2 SELO3 SELO4 SELO5 SELO6 SELO7 DX0INS DX0INS DX1INS DX2INS DOUT SCLKOUT SELO0 1) from/to P3.0 P3.1 P1.6 P9.4 P9.5 P3.2 P1.7 P3.3 P3.4 P3.5 P3.7 P1.3 P1.4 ERU_2A2 ERU_2B0 ERU_2A3 I/O1) Can be used to/as O O O O O O O O O O O O O O O O O O O shift data output shift data output shift data output shift data output shift data output master clock output, e.g. for IIS shift clock output shift clock output shift control output 0 shift control output 1 shift control output 2 shift control output 3 shift control output 4 shift control output 5 shift control output 6 shift control output 7 external interrupt input for ERU (SCU) single wire ASC collision detection external interrupt input for ERU (SCU) external interrupt input for ERU (SCU) loop back shift data output loop back shift clock output loop back shift control output Control Outputs System Related Outputs U2C0_DX1F O U2C0 Loop Back Outputs U2C0_DX0G O U2C0_DX1G O U2C0_DX2G O Input/output for U2C0. User's Manual USIC, UM_V0.2D5 19-215 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel 19.7.5.6 USIC Module 2 Channel 1 The signals of USIC module 2 channel 1 have the prefix U2C1_. Table 19-36 USIC2 Channel 1 (U2C1) I/O Connections Signal Data Inputs DX0A DX0B DX0C DX0D DX0E DX0F DX0G Clock Inputs DX1A DX1B DX1C DX1D DX1E DX1F DX1G Control Inputs DX2A DX2B DX2C DX2D DX2E DX2F DX2G P3.4 ESR2 ESR1 0 RTC_ T14INT CCU62_ T13_PM U2C1_ SELO0 I I I I I I I shift control input shift control input shift control input shift control input input for transmit data validation input for transmit data validation loop back shift control input P3.5 P3.6 P1.2 0 0 0 U2C1_ SCLKOUT I I I I I I I shift clock input shift clock input shift clock input shift clock input shift clock input shift clock input loop back shift clock input P3.6 P3.7 P1.1 P1.2 ESR2 0 U2C1_ DOUT I I I I I I I shift data input shift data input shift data input shift data input shift data input shift data input loop back data shift input from/to I/O1) Can be used to/as User's Manual USIC, UM_V0.2D5 19-216 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel Table 19-36 USIC2 Channel 1 (U2C1) I/O Connections (cont'd) Signal Data Outputs DOUT DOUT DOUT Clock Outputs MCLKOUT SCLKOUT SCLKOUT SELO0 SELO1 SELO2 SELO3 SELO4 SELO5 SELO6 SELO7 DX0INS DX0INS DX1INS DX2INS DOUT SCLKOUT SELO0 1) from/to P3.6 P3.7 P1.1 P3.5 P1.2 P3.4 P3.3 ERU_2B2 ERU_2B3 I/O1) Can be used to/as O O O O O O O O O O O O O O O O O external interrupt input for ERU (SCU) loop back shift data output loop back shift clock output loop back shift control output shift data output shift data output shift data output master clock output, e.g. for IIS shift clock output shift clock output shift control output 0 shift control output 1 shift control output 2 shift control output 3 shift control output 4 shift control output 5 shift control output 6 shift control output 7 external interrupt input for ERU (SCU) single wire ASC collision detection Control Outputs System Related Outputs U2C1_DX1F O U2C1 Loop Back Outputs U2C1_DX0G O U2C1_DX1G O U2C1_DX2G O Input/output for U2C1. User's Manual USIC, UM_V0.2D5 19-217 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Universal Serial Interface Channel User's Manual USIC, UM_V0.2D5 19-218 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller 20 Controller Area Network (MultiCAN) Controller This chapter describes the MultiCAN controller of the XC2000. It contains the following sections: * * * Overview of the MultiCAN Kernel (see Section 20.1) Functional description of the MultiCAN Kernel (see Section 20.2) XC2000 implementation specific details and registers of the MultiCAN controller (port connections and control, interrupt control, address decoding, clock control, see Section 20.4). Note: The MultiCAN kernel register names described in this chapter will be referenced in the XC2000 User's Manual by the module name prefix "CAN_". 20.1 MultiCAN Short Description This section describes the serial communication interfaces CAN (Controller Area Network) of the communication module MultiCAN of the XC2000. 20.1.1 Overview The MultiCAN module contains 5 independent CAN nodes, representing the communication interfaces. User's Manual MultiCAN, V1.7d2 20-1 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller MultiCAN Module Kernel fCAN Clock Control f CLC Message Object Buffer 128 Objects CAN Node n-1 . . . CAN Node 1 CAN Node 0 TXDC n-1 RXDCn-1 . . . TXDC1 RXDC1 TXDC0 RXDC0 Address Decoder Linked List Control Port Control . . . Interrupt Control CAN Control MultiCAN6_overview_NotSingle_noTT.vsd Figure 20-1 Overview of the MultiCAN Module 20.1.2 * * * * * * * CAN Features Several key features contribute to the high performance of the MultiCAN module: CAN functionality conforms to CAN specification V2.0 B active for each CAN node (compliant to ISO 11898) 5 independent CAN nodes available 128 independent message objects (shared by the CAN nodes) Dedicated control registers for each CAN node Data transfer rate up to 1MBaud, individually programmable for each node Flexible and powerful message transfer control and error handling capabilities Full-CAN functionality: message objects can be individually - Assigned to one of the 5 CAN nodes - Configured as transmit or receive object - Participate in a message buffer with FIFO algorithm - Set up to handle frames with 11-bit or 29-bit identifiers - Provided with programmable acceptance mask register for filtering - Monitored via a frame counter - Configured to Remote Monitoring Mode Automatic gateway mode support 20-2 V1.0, 2007-06 * User's Manual MultiCAN, V1.7d2 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary * * * Controller Area Network (MultiCAN) Controller 16 individually programmable interrupt outputs CAN Analyzer Mode for bus monitoring SRAMs in MultiCAN module optionally parity error protected User's Manual MultiCAN, V1.7d2 20-3 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller 20.2 CAN Functional Description This section describes the core features of the CAN module. 20.2.1 Conventions and Definitions Table 20-1 defines constants that are used throughout the MultiCAN specification. These are fixed values for a given MultiCAN implementation. Table 20-1 Constant n_objects Fixed Module Constants Value 128 Description Number of Message Objects n_objects denotes the total amount of message objects available. Number of Interrupt Output Lines n_interrupts denotes the total number of interrupt outputs available. Number of Message Pending Bits n_pendings denotes the number of message pending bits available. The number of message pending registers is given by n_pendings/32. Number of Lists n_lists denotes the total number of lists available for allocation of message number. Number of CAN Nodes Available n_nodes denotes the total number of CAN nodes available. As each CAN node has it's own list in addition to the list of un-allocated elements, the relation n_nodes < n_lists is true. n_interrupts 16 n_pendings 256 n_lists 8 n_nodes 5 20.2.2 Introduction The MultiCAN module contains 5 Full-CAN nodes operating independently or exchanging data and remote frames via a gateway function.Transmission and reception of CAN frames is handled in accordance to CAN specification V2.0part B (active). Each CAN node can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. 20.2.2.1 Feature Overview All CAN nodes share a common set of message objects, where each message object may be individually allocated to one of the CAN nodes. Besides serving as a storage User's Manual MultiCAN, V1.7d2 20-4 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller container for incoming and outgoing frames, message objects may be combined to build gateways between the CAN nodes or to setup a FIFO buffer. The message objects are organized in double chained lists, where each CAN node has it's own list of message objects. A CAN node stores frames only into message objects that are allocated to the list of the CAN node. It only transmits messages from objects of this list. A powerful, command driven list controller performs all list operations. The bit timings for the CAN nodes are derived from the peripheral clock (fCAN) and are programmable up to a data rate of 1 MBaud. A pair of receive and transmit pins connects each CAN node to a bus transceiver. Features * * * * * * * Compliant to ISO 11898. CAN functionality according to CAN specification V2.0 B active. Dedicated control registers are provided for each CAN node. A data transfer rate up to 1 MBaud is supported. Flexible and powerful message transfer control and error handling capabilities are implemented. Advanced CAN bus bit timing analysis and baud rate detection can be performed for each CAN node via the frame counter. Full-CAN functionality: A set of 128 message objects can be individually - allocated (assigned) to any CAN node - configured as transmit or receive object - setup to handle frames with 11-bit or 29-bit identifier - counted or assigned a timestamp via a frame counter - configured to remote monitoring mode Advanced Acceptance Filtering: - Each message object provides an individual acceptance mask to filter incoming frames. - A message object can be configured to accept only standard or only extended frames or to accept both standard and extended frames. - Message objects can be grouped into 4 priority classes. - The selection of the message to be transmitted first can be performed on the basis of frame identifier, IDE bit and RTR bit according to CAN arbitration rules. Advanced Message Object Functionality: - Message Objects can be combined to build FIFO message buffers of arbitrary size, which is only limited by the total number of message objects. - Message objects can be linked to form a gateway to automatically transfer frames between 2 different CAN buses. A single gateway can link any two CAN nodes. An arbitrary number of gateways may be defined. Advanced Data Management: * * * User's Manual MultiCAN, V1.7d2 20-5 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller * - The Message objects are organized in double chained lists. - List reorganizations may be performed any time, even during full operation of the CAN nodes. - A powerful, command driven list controller manages the organization of the list structure and ensures consistency of the list. - Message FIFOs are based on the list structure and can easily be scaled in size during CAN operation. - Static Allocation Commands offer compatibility with TwinCAN applications, which are not list based. Advanced Interrupt Handling: - Up to 16 interrupt output lines are available. Most interrupt requests can be individually routed to one of the 16 interrupt output lines. - Message postprocessing notifications can be flexibly aggregated into a dedicated register field of 256 notification bits. User's Manual MultiCAN, V1.7d2 20-6 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller 20.2.2.2 Module Structure Figure 20-2 shows the general structure of the MultiCAN module with 5 CAN nodes. CAN Bus 0 CAN Bus 1 ... CAN Bus n-1 Node Control Unit Bitstream Processor CAN Node 0 CAN Node 1 ... CAN Node n-1 Bit Error Timing Handling Frame Unit Counter Unit Interrupt Control Unit Message Controller Interrupt Control Logic Message RAM List Control Logic Address Decoder interrupt control bus interface MultiCAN_Blockdiag_n.vsd Figure 20-2 MultiCAN Block Diagram with several CAN Nodes User's Manual MultiCAN, V1.7d2 20-7 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary CAN Nodes Each CAN node consists of several sub-units as described in Table 20-2.: Table 20-2 Subunit Bit Stream Processor Subunits of CAN Nodes Description The Bit Stream Processor performs data, remote, error and overload frame processing according to the ISO 11898 standard. This includes conversion between the serial data stream and the input/output shift registers. The Bit Timing Unit defines the length of a bit time and the location of the sample point according to the user settings, taking into account propagation delays and phase shift errors. The Bit Timing Unit also performs resynchronization. The Error Handling Unit manages the receive and transmit error counter. According to the contents of both counters the CAN node is set into an "Error Active", "Error Passive" or "Bus-Off" state. The Node Control Unit coordinates the operation of the CAN node: * Enables/disable CAN transfer of the node * Enable/Disable and generate node specific events that lead to an interrupt request (CAN bus errors, successful frame transfers etc.) * Administration of the Frame Counter Controller Area Network (MultiCAN) Controller Bit Timing Unit Error Handling Unit Node Control Unit Message Controller The message controller handles the exchange of CAN frames between the CAN nodes and the message objects which are stored in the Message RAM. It performs: * * * * * Receive Acceptance filtering to determine the correct message object for storing of a received CAN frame. Transmit Acceptance Filtering to determine the message object to be transmitted first, individually for each CAN node. Content transfer between message objects and the CAN nodes, taking into account the status/control bits of the message objects. Handling of the FIFO buffering and Gateway functionality. Aggregation of message pending notification bits. User's Manual MultiCAN, V1.7d2 20-8 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary List Controller The list controller performs all operations that lead to a modification of the double chained message object lists. Only the list controller is allowed to modify the list structure. The allocation/deallocation or reallocation of a message object can be requested via a user command interface (command panel). The list controller state machine then performs the requested command autonomously. Controller Area Network (MultiCAN) Controller User's Manual MultiCAN, V1.7d2 20-9 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller 20.2.3 CAN Node Control Each CAN node may be configured and run independently from the other CAN nodes. To this end each CAN node is equipped with an individual set of SFR registers to control and to monitor the CAN node. 20.2.3.1 Bit Timing According to ISO 11898 standard, a CAN bit time is subdivided into different segments (Figure 20-3). Each segment consists of multiples of a time quantum tq. The magnitude of tq is adjusted by the bit field BRP and by bit DIV8, both controlling the baud rate prescaler (see bit timing register NBTR). The baud rate prescaler is driven by the MultiCAN module clock fCAN. 1 Bit Time TSeg1 TSync TProp Tb1 TSeg2 Tb2 Sync. Seg 1 Time Quantum (tq) Sample Point Transmit Point MCT04518 Figure 20-3 CAN Bus Bit Timing Standard The Synchronization Segment (TSync) allows a phase synchronization between transmitter and receiver time base. The Synchronization Segment length is always 1 tq. The Propagation Time Segment (TProp) takes into account the physical propagation delay in the transmitter output driver, on the CAN bus line and in the transceiver circuit. For a working collision detect mechanism, TProp has to be two times the sum of all propagation delay quantities rounded up to a multiple of tq. The Phase Buffer Segments 1 and 2 (Tb1, Tb2) before and after the signal sample point are used to compensate a mismatch between transmitter and receiver clock phase detected in the synchronization segment. The maximum number of time quanta allowed for resynchronization is defined by bit field SJW in the CAN Node Bit Timing register NBTR. The Propagation Time Segment and the Phase Buffer Segment 1 are combined to parameter TSeg1, which is defined by the value TSEG1 in the respective CAN Node Bit Timing register NBTR. A minimum of 3 time quanta is requested by the ISO standard. Parameter TSeg2, which is defined by the value of TSEG2 in the CAN Node Bit Timing Register NBTR, covers the Phase Buffer Segment 2. A minimum of 2 time quanta is requested by the ISO standard. According User's Manual MultiCAN, V1.7d2 20-10 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller ISO standard, a CAN bit time, calculated as the sum of TSync, TSeg1 and TSeg2, must not fall below 8 time quanta. Calculation of the bit time: tq = (BRP+1) / fCAN = 8 x (BRP+1) / fCAN = 1 tq = (TSEG1 + 1) x tq = (TSEG2 + 1) x tq = TSync + TSeg1 + TSeg2 (min. 3 tq) (min. 2 tq) (min. 8 tq) if DIV8 = 0 if DIV8 = 1 TSync TSeg1 TSeg2 bit time To compensate phase shifts between clocks of different CAN controllers, the CAN controller has to synchronize on any edge from the recessive to the dominant bus level. If the hard synchronization is enabled (at the start of frame), the bit time is restarted at the synchronization segment. Otherwise, the resynchronization jump width TSJW defines the maximum number of time quanta a bit time may be shortened or lengthened by one resynchronization. The value of SJW is programmed in the CAN Node Bit Timing Register. TSJW TSeg1 TSeg2 = (SJW + 1) x tq TSJW + Tprop TSJW The maximum relative tolerance for fCAN depends on the Phase Buffer Segments and the resynchronization jump width. dfCAN dfCAN min (Tb1, Tb2) / 2 x (13 x bit time - Tb2) TSJW / 20 x bit time AND A valid CAN bit timing must be written to the CAN Node Bit Timing Register NBTR before resetting the INIT bit in the Node Control Register, i.e. before enabling the operation of the CAN node. The Node Bit Timing Register may be written only if bit CCE (Configuration Change Enable) is set in the corresponding Node Control Register. User's Manual MultiCAN, V1.7d2 20-11 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller 20.2.3.2 CAN Error Handling The Error Handling Unit of the CAN node is responsible for the fault confinement of the CAN device. Its two counters, the Receive Error Counter and the Transmit Error Counter (control register NECNT), are incremented and decremented by commands from the Bit Stream Processor. If the Bit Stream Processor itself detects an error while a transmit operation is running, the Transmit Error Counter is incremented by 8. An increment of 1 is used, when the error condition was reported by an external CAN node via an error frame generation. For error analysis, the transfer direction of the disturbed message and the node, recognizing the transfer error, are indicated in the control register NECNT of the respective CAN node. According to the values of the error counters, the CAN node is set into the states "error active", "error passive" and "bus-off". The CAN node is in error active state, if both error counters are below the error passive limit of 128. It is in error passive state, if at least one of the error counters equals or exceeds 128. The bus-off state is activated if the Transmit Error Counter equals or exceeds the busoff limit of 256. This state is reported by flag BOFF in the NSR status register of the CAN node. The device remains in this state, until the bus-off recovery sequence is finished. Additionally, there is the bit EWRN in the NSR status register, which is set, if at least one of the error counters equals or exceeds the error warning limit defined by bit field EWRNLVL in the control registers NECNT of the CAN node. Bit EWRN is reset if both error counters fall below the error warning limit again (see Page 20-63). 20.2.3.3 CAN Frame Counter Each CAN node is equipped with a frame counter which allows to count transmitted/received CAN frames or to obtain information about the time instant when a frame has been started to transmit or being received by the CAN node. CAN frame counting/bit time counting is performed by a 16 bit counter which is controlled by register NFCR of the respective CAN node. Bit field CFSEL of register NFCR defines the operation mode of the frame counter: * Frame Count Mode: The frame counter is incremented after the successful transmission and/or reception of a CAN frame. The incremented value is copied to the CFC field of the Interrupt Pointer Register of the message object involved in the transfer. Time Stamp Mode: The frame counter is incremented with the beginning of a new bit time. When the transmission/reception of a frame starts, the value of the frame counter is captured and stored to the CFC field of register NFCR. After the successful transfer of the frame the captured value is copied to the CFC field of the Interrupt Pointer Register of the message object involved in the transfer. Bit Timing Mode: Used for baud rate detection and analysis of the bit timing (Chapter 20.2.5.3). * * User's Manual MultiCAN, V1.7d2 20-12 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller 20.2.3.4 CAN Node Interrupts Each CAN node is equipped with four interrupt sources. NSRx TXOK 1 NCRx TRIE NIPRx TRINP Receive RXOK NSRx NSRx LEC 3 CAN Error NCRx 1 ALIE NIPRx ALINP List Length Error List Object Error LLE NSRx LOE NSRx NFCRx CFCOV Frame Counter Overflow/Event NFCRx CFCIE NIPRx CFCINP MCA05837 Correct Message Object Transfer Transmit NCRx LECIE NIPRx LECINP NSRx EWRN BOFF NSRx ALERT Figure 20-4 CAN Node Interrupts User's Manual MultiCAN, V1.7d2 20-13 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller An interrupt request is generated upon: * * * The successful transmission/reception of a frame, An overflow of the frame counter (frame count mode/time stamp mode) or a bit timing measurement event (bit timing mode), An error related to the CAN node. 20.2.4 Message Object List Structure The message objects of the MultiCAN module are organized in double chained lists, where each message object has a pointer to the previous message object in the list as well as a pointer to the next message object in the list. 20.2.4.1 Basics The MultiCAN module provides 16 different lists, where each object is allocated to one of these lists. A 4 bit LIST bit field in the Message Object Control Register indicates the list to which the respective message object is currently allocated. In the example of Figure 20-5 three message objects are allocated to the list with list index 2. PPREV = 5 PNEXT = 16 LIST = 2 PPREV = 5 PNEXT = 3 LIST = 2 PPREV = 16 PNEXT = 3 LIST = 2 Message Object 5 Message Object 16 Message Object 3 EMPTY = 0 SIZE = 2 BEGIN = 5 END = 3 Register LIST2 MultiCAN_list_basics Figure 20-5 Example Allocation of Message Objects to a List The BEGIN field of the List Register points to the first element in the list (object 5 in the example) whereas the END field points to the last element in the list (object 3 in the example). The number of elements in the list is indicated in the SIZE field of the List Register (#elements = SIZE + 1, thus SIZE = 2 for the 3 elements of the example). The User's Manual MultiCAN, V1.7d2 20-14 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller EMPTY bit indicates a list with no elements (EMPTY = 0 in the example, as the list is not empty). Each message object has a pointer PNEXT (located in the Message Object Control Register) that points to the next message object in the list and a pointer PREV that points to the previous message object in the list. PPREV of the first message object points to the object itself because the first object has no predecessor (in the example object 5 is the first object, indicated by PPREV = 5). PNEXT of the last message object also points to the object itself because the last element has no successor (in the example object 3 is the last object, indicated by PNEXT = 3). Each message object also has a 4 bit LIST field (located in the Message Object Control Register) which shows list index of the list to which the object is currently allocated (the objects of the example are allocated to list 2, thus LIST = 2). 20.2.4.2 List of Unallocated Elements The list with list index 0 has a special meaning: It is the list of all unallocated elements. An element is called unallocated if and only if it belongs to list zero. It is called allocated if and only if it belongs to one of the other lists. After reset all message objects are unallocated, i.e. belong to the list of unallocated elements. The initial allocation of the message objects within the list of unallocated objects is ordered by message number, i.e. the predecessor of message object n is object n-1 and the successor of object n is object n+1. 20.2.4.3 Connection to the CAN Nodes One CAN node is linked to exactly one unique list of message objects.. Table 20-3 List Index 0 1 to n_nodes List Indices Description List of unallocated elements Lists associated to a CAN node. List index i belongs to CAN node i -1. n_nodes+1 to n_lists- Free user lists, which are not associated to a CAN node. 1 User's Manual MultiCAN, V1.7d2 20-15 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller CAN Bus 0 CAN Bus 1 ... CAN Bus n-1 List of all unallocated elements CAN Node 0 CAN Node 1 CAN Node n-1 1st Object in List 0 1st Object in List 1 1st Object in List 2 ... 1st Object in List n 2nd Object in List 0 2nd Object in List 1 2nd Object in List 2 2nd Object in List n Last Object in List 0 Last Object in List 1 Last Object in List 2 Last Object in List n MultiCAN_list_to_can_n.vsd Figure 20-6 Message Objects Linked to several CAN Nodes User's Manual MultiCAN, V1.7d2 20-16 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller 20.2.4.4 List Command Panel The list structure may not be modified directly by means of write accesses to the LIST registers and the PPREV, PNEXT and LIST fields in the message objects as they are read only. The management of the list structure is performed by and limited to the list controller unit inside the MultiCAN module. The list controller is controlled via a command panel which allows the user to issue list allocation commands to the list controller. The list controller basically serves two purposes: 1. Ensure that all operations that modify the list structure result in a consistent list structure. 2. Present maximum comfort and flexibility to the user. The list controller and the associated command panel allows the programmer to concentrate on the final properties of the list, which are characterized by the allocation of message objects to a CAN node and the ordering relation between objects which are allocated to the same list. The process of list (re-)building is left to the list controller. A panel command is started by writing the respective command code (see Table 20-9 "Panel Commands" on Page 20-53) into to the PANCMD field of the panel control register. The corresponding command arguments must be written to PANAR1 and PANAR2 before writing the command code or latest together with the command code in a single 32 bit write access to the panel control register (only possible within 32 bit system environments). With the write of a valid command code the BUSY flag in the Panel Control Register becomes active (BUSY = 1) and the control panel registers are locked, which means that write accesses to the Panel Control Register are ignored. The BUSY flag remains active and the control panel remains locked until the execution of the requested command is completed. When the issued command is a dynamic allocation which takes an element from the list of unallocated objects, then also the RBUSY bit becomes active together with the BUSY bit (RBUSY = BUSY = 1) to indicate that PANAR1 and PANAR2 are going to be updated by the list controller: 1. The message number of the message object taken from the list of unallocated elements is written to PANAR1. 2. An error status is posted to bit 7 of PANAR2 (Bit 7 = ERR). If ERR = 1 then the list of unallocated elements was empty and the command is aborted. If ERR = 0 then the list was not empty and the command will be performed successfully. The results are written before the list controller starts the actual allocation process. As soon as the results are available, RBUSY becomes inactive (RBUSY = 0) again, while BUSY still remains active until completion of the command. This allows the user to setup the new message object while it is still in the process of list allocation. The access to message objects is not limited during ongoing list operations. However, any access to a User's Manual MultiCAN, V1.7d2 20-17 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller register resource located inside the RAM delays the ongoing allocation process by one access cycle. As soon as the command is done the BUSY flag becomes inactive (BUSY = 0) and write accesses to the Panel Control Register are enabled again. Also the NOP command code is automatically written to the CMD field of the Panel Control Register. A new command may be started any time during BUSY inactive. All fields of the Panel Control Register except BUSY and RBUSY may be written by the user. This allows to save and restore the Panel Control Register if the Command Panel shall be used within independent (mutually interruptible) interrupt routines. If this is the case then any task that uses the Command Panel and that may interrupt another task also using the Command Panel should poll the BUSY flag until is becomes inactive and save the whole PANCTR register to a save memory location before issuing a command. At the end it should restore PANCTR from the said memory location. Before a message object which is allocated to the list of an active CAN node shall be moved to another list or to another position within the same list, bit MSGVAL ("Message Valid") should be cleared in the Message Object Control Register of the message object. User's Manual MultiCAN, V1.7d2 20-18 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller 20.2.5 CAN Node Analysis Features CAN Analyze Mode allows to monitor the CAN traffic without affecting the logical state of the CAN bus. 20.2.5.1 Analyze Mode CAN Analyze Mode is selected by setting bit CALM in the Node Control Register. CAN Analyze Mode may be selected for each CAN node individually. In CAN Analyze Mode the transmit pin of the CAN node is held on recessive level. The CAN node may receive frames (data-, remote-, and error frames) but is not allowed to transmit. Active error frames are sent recessive. Received data/remote frames are not acknowledged (i.e. acknowledge slot is sent recessive), but will be received and stored in matching message objects as long as there is any other node that acknowledges the frame. All message object functionality is available, but no transmit request will be executed. 20.2.5.2 Loop-back Mode The MultiCAN module provides a loop-back mode to enable an in-system test of the MultiCAN module as well as the development of CAN driver software without access to an external CAN bus. The loop-back feature consists of an internal CAN bus (inside the MultiCAN module) and a bus select switch for each CAN node (Figure 20-7). With the switch each CAN node can be wired either to the internal CAN bus (loop-back mode activated) or the external CAN bus, i.e. the transmit- and receive pins (normal operation). The CAN bus which is currently not selected is driven recessive, i.e. the transmit pin is held at 1 and the receive pin is ignored by the CAN nodes which are in loop-back mode. Loop-back Mode is selected individually for each CAN node by setting bit LBM in the respective Node Port Control Register. All CAN nodes that are in loop-back mode may communicate on the internal CAN bus without affecting the normal operation of the other CAN nodes which are not in loop-back mode. User's Manual MultiCAN, V1.7d2 20-19 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller NPCR0.LBM Internal CAN Bus CAN Node 0 0 1 External CAN Bus 0 NPCR1.LBM 0 1 CAN Node 1 External CAN Bus 1 NPCR2.LBM 0 1 CAN Node 2 External CAN Bus 2 NPCR3.LBM External CAN Bus x MCA05840 CAN Node x 0 1 Figure 20-7 Loop-back Mode for several CAN Nodes User's Manual MultiCAN, V1.7d2 20-20 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller 20.2.5.3 Bit Timing Analysis For each CAN node detailed analysis of the bit timing can be performed by means of using dedicated analysis modes of the CAN frame counter. The bit timing analysis functionality of the frame counter may be used for automatic detection of the CAN baud rate as well as for the analysis of the timing of the CAN network. Bit timing analysis for a CAN node is selected by CFMOD = 10B (Bit Timing Mode) in the CAN Node Frame Counter Register. Bit timing analysis does not affect the operation of the CAN node. The measurement results are written to the CFC field. Whenever CFC is updated in Bit Timing Mode, then also the CFCOV bit is set in order to indicate the update event. If CFCIE is set then also an interrupt request is generated, where for the the CAN node i = 0 to 4 the interrupt request is generated on the interrupt output line i. Automatic Baud Rate Detection Automatic baud rate detection requires to measure the time between the observation of subsequent dominant edges on the CAN bus. This measurement is automatically performed if CFSE = 000B in the CAN Node Frame Counter Register. With each dominant edge monitored on the CAN receive input the time (measured in clock cycles) between this edge and the most recent dominant edge is stored in the CFC field. Synchronization Analysis The bit time synchronization is monitored if CFSEL = 010B. The time between the first dominant edge and the sample point is measured and stored in CFC. The bit timing synchronization offset may be derived from this time as the first edge after the sample point triggers synchronization and there is only one synchronization between consecutive sample points. Synchronization Analysis may be used to fine tune the baud rate during reception of the first CAN frame with the measured baud rate. Driver Delay Measurement The delay between a transmitted edge and the corresponding received edge is measured with CFSEL = 011B (dominant to dominant) and CFSEL = 001B (recessive to recessive). These delays indicate the time needed to represent a new bit value on the physical implementation of the CAN bus. User's Manual MultiCAN, V1.7d2 20-21 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller 20.2.6 Message Acceptance Filtering The message acceptance filtering includes receive and transmit filtering. 20.2.6.1 Receive Acceptance Filtering When a message object is received on a CAN node, then a unique message object is determined in which the received frame will be stored upon successful frame reception. A message object qualifies for the reception of a frame if and only if the following conditions are fulfilled: 1. The message object is allocated to the list of the CAN node on which the frame is received. 2. MSGVAL is set in the Message Control Register 3. RXEN is set in the Message Control Register 4. The DIR bit in the Message Control Register equals the RTR bit of the received frame. If DIR = 1 (transmit object) then the message object only accepts remote frames. If DIR = 0 (receive object) then the message object only accepts data frames. 5. If MIDE = 1 in the Acceptance Mask Register (MOAMR) then the IDE bit of the received frame equals the IDE bit in the Arbitration Register (MOAR). IF MOAR.IDE = 1 then the message object only accepts frames with extended identifier. If MOAR.IDE = 0 then the message object only accepts standard frames. If MOAMR.MIDE = 0 then the IDE bit of the received frame is don't care, i.e. the message object accepts both standard and extended frames. 6. The identifier of the received frame matches the identifier stored in the Arbitration Register of the message object with respect to the acceptance mask in the MOAMR register. This means that each bit of the received identifier is equal to the corresponding identifier bit in the Acceptance Register, except those bits for which the corresponding mask bits in MOAMR are cleared. These identifier bits are don't care. Figure 20-8 illustrates this identifier check. A priority ordering relation is defined for the message objects: A message object A has higher receive priority than a message object B if and only if the following conditions are fulfilled: 1. A belongs to a higher priority class than B, i.e. MOAR.PRI of A must be less than or equal to MOAR.PRI of B. 2. If both objects belong to the same priority class (PRI of A = PRI of B) then message object B is a list successor of A, i.e. B can be reached by means of successively stepping forward in the list, starting from A. Among all messages that fulfill all 6 qualifying criteria the unique message object with highest receive priority wins acceptance filtering, i.e. is selected for storage of the received frame. All other message objects loose receive acceptance filtering. User's Manual MultiCAN, V1.7d2 20-22 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller identifier of received frame identifier of message object bitwise XOR 0 = bit match 1 = no match acceptance mask of message object bitwise AND IDmatch IDmatch = 0 : ID of received frame fits to message object IDmatch > 0 : ID of received frame does not fit to message object reg_id_match Figure 20-8 Received Message Identifier Acceptance Check 20.2.6.2 Transmit Acceptance Filtering A message is requested for transmission by means of setting a transmit request in the message object which holds the message. If more than one message object has a valid transmit request for the same CAN node, then a single message object is chosen for actual transmission from the candidates, because only a single message object may be transmitted at the same time on a single CAN bus. A message object qualifies for transmission on a given CAN node if and only if it meets the following criteria (Figure 20-9): 1. 2. 3. 4. The message object is allocated to the list of the CAN node considered. MSGVAL is set in the Message Object Control Register. TXRQ is set in the Message Object Control Register. TXEN0 and TXEN1 are set in the Message Object Control Register. A priority order relation is defined for all qualifying objects to determine the message to be transmitted first: Let A and B be two message objects qualifying for transmission, where without loss of generality object B is assumed to be is a list successor of A, i.e. B can be reached by means of successively stepping forward in the list, starting from A. For both message objects associated CAN messages CANA and CANB are defined, where identifier, IDE and RTR bit are taken from MOAR.ID, MOAR.IDE and MOCTR.DIR. If both message objects belong to a different priority class (different value of bit field PRI in the Message Object Arbitration Register MOAR) then the message object with lower PRI value has higher transmit priority and will be transmitted first. User's Manual MultiCAN, V1.7d2 20-23 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller If both message objects belong to the same priority class (equal value of bit field MOAR.PRI), then message object A has higher transmit priority than object B if and only if one of the following conditions is fulfilled: 1. PRI = 10 and CAN message CANA has higher or equal priority than CAN message CANB with respect to CAN arbitration rules (see Table 20-13). 2. PRI = 01 or PRI = 11 (priority by list order). 3. PRI = 00 is reserved. Transmit objects with PRI = 00 are not taken into account for the transmit acceptance filtering. The unique message object that qualifies for transmission and has highest transmit priority wins transmit acceptance filtering, i.e. will be transmitted first. All other message objects lose the current transmit acceptance filtering round. They get a new chance in subsequent filtering rounds. MSGVAL TXRQ TXEN0 TXEN1 & 0 = Object will not be transmitted 1 = Object is requested for transmission MCA05842 Figure 20-9 Effective Transmit Request of Message Object User's Manual MultiCAN, V1.7d2 20-24 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller 20.2.7 Message Postprocessing Interface When a message object has received or transmitted a frame successfully then the CPU may be notified to perform message postprocessing on the message object. The postprocessing interface of the MultiCAN module consists of two elements: 1. Message Interrupts to trigger postprocessing. 2. Message Pending Registers to aggregate the pending message interrupts into a common structure for postprocessing. 20.2.7.1 Message Interrupts When the storage of a received frame into a message object or the successful transmission of a frame is completed then a message interrupt my be requested. For each message object both transmit and receive interrupts may be routed individually to one of the available interrupt output lines, as illustrated in Table 20-10. A receive interrupt is not restricted to the direct storage of a received frame from the CAN node the message object belongs to. It also occurs upon frame storage induced by FIFO or gateway action. The TXPND and RXPND bits are set whenever a successful transmission/reception takes place, no matter if the respective interrupt is enabled or not. MOSTATn TXPND RXPND MOFCRn OVIE TXIE RXIE MMC = 0010B Message n Transmitted Message n FIFO full = 0001B 1 MOIPRn TXINP & & Message n Received MMC = 0001B: Message object n is a Receive FIFO Base Object MMC = 0010B: Message object n is a Transmit FIFO Base Object 1 MOIPRn RXINP MCA05843 Figure 20-10 Message Interrupt Request Routing User's Manual MultiCAN, V1.7d2 20-25 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller 20.2.7.2 Message Pendings When a message interrupt request is generated then also a message pending bit is set in one of the Message Pending Register. To this end the pending bit selection field MPN is defined in the Message Object Interrupt Pointer Register. The value of MPN is combined with TXINP and RXINP to yield the effective bit position of the Pending bit, as illustrated in Figure 20-11. The bit position consists of 2 parts: 1. The high part (bits [7:5]) of the calculated position selects the Message Pending Register in which the pending bit will be set. 2. The low part (bits [4:0]) of the calculated position selects the position (0-31) of the pending bit within the 32 bit Message Pending Register. The MPSEL bit field in the MultiCAN Control Register allows to include the interrupt request node pointer (RXINP for reception, TXINP for transmission) so as to implement different target location of the pending bit for receive and transmit. The Message Pending Registers may be written by the CPU, but those bits that are written 1 are left unchanged and only those bits which are written 0 are cleared. This allows to clear individual bits with a single write access instead of a read/modify/writeback access. Thus there is no access conflict when the MultiCAN module sets another pending bit in the same register at the same time. Each Message Pending Register is linked to an individual Message Index Register which displays the lowest bit position of all set (1) bits in the Message Pending Register. The Message Index Register is read only and is updated immediately when the value of the corresponding Message Pending Register changes. There is no direct link between the Message Pending Registers and the interrupt request nodes. Such a link may, however, be established by the application. For example, each interrupt request node could be linked to a unique Message Pending Register. The example shown in Figure 20-12 links message Pending Register n to interrupt output line n (n = 0-7). User's Manual MultiCAN, V1.7d2 20-26 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller Message Object n Interrupt Pointer Register MOIPRn[15:0] MPN 7 15 6 5 4 3 2 1 0 3 TXINP 2 1 0 3 RXINP 2 1 0 0 01 01 01 01 0 = transmit event 1 = receive event Message Pending Registers 1 0 7 1 0 7 6 5 2D E 1M U 0X 0 255 223 191 159 127 95 63 31 MSPND7 MSPND6 MSPND5 MSPND4 MSPND3 MSPND2 MSPND1 MSPND0 224 192 160 128 96 64 32 0 .......... ..... 1 0 31 D 4E M U X 3:0 0 1 0 MSB 4 ........ 3 31 2 1 0 0 MCA05844 MPSEL Modul Control Register MCR[31:0] Figure 20-11 Target Location of the Message Pending Bit (Transmit/Receive) User's Manual MultiCAN, V1.7d2 20-27 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller RXINP, TXINP = n MPN[7:5] = n Message Object Message Pending Register n Interrupt Node n link_int_to_pendings Figure 20-12 Example Link of Message Pending Registers to Interrupt Output Lines User's Manual MultiCAN, V1.7d2 20-28 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller 20.2.8 Message Object Data Handling The follwing section describes the actions taken during a frame reception and during a frame transmition. 20.2.8.1 Frame Reception When a message is received on the CAN bus then the storage of the message into a message object is prepared and performed according to the scheme shown in Figure 20-13. The MultiCAN module not just copies the received data into the message object, but it provides advanced features to enable consistent data exchange between MultiCAN and CPU. MSGVAL The MSGVAL ("Message Valid") bit in the Message Object Control Register is the main switch of the message object. The MultiCAN module only stores information in the message object during the frame reception process when MSGVAL is set (MSGVAL = 1). Whenever MSGVAL is reset (MSGVAL = 0) by the CPU then the MultiCAN module stops all ongoing write accesses to the message object so that the message object may be reconfigured by the CPU in subsequent write accesses to the message object without being disturbed by the MultiCAN. RTSEL When the CPU re-configures a message object (.i.e. clears MSGVAL, modifies the message object and sets MSGVAL again) during CAN operation then the following scenario can occur: 1. 2. 3. 4. The message object wins receive acceptance filtering. The CPU clears MSGVAL to reconfigure the message object. The CPU sets MSGVAL again after reconfiguration. The end of the received frame is reached. As MSGVAL is set, the received data are stored in the message object, a message interrupt request is generated, gateway and fifo actions are processed etc. The storage of the received data may be undesirable if the context of the message object has changed, because the old message object configuration has been used for acceptance filtering of the message. Bit MOCTR.RTSEL ("Receive/Transmit Selected") allows to disconnect a message object from an ongoing frame reception: When a message object wins receive acceptance filtering then bit RTSEL is set (RTSEL = 1) by the MultiCAN in order to indicate an upcoming frame delivery. The MultiCAN checks RTSEL for value 1 upon successful frame reception in order to verify User's Manual MultiCAN, V1.7d2 20-29 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller that the object is still ready for receiving the frame. The received frame is stored in the message object (along with all subsequent actions such as message interrupts, FIFO & gateway actions, flag updates) only if RTSEL = 1. When the user invalidates a message object during CAN operation (MSGVAL -> 0) then the user should clear RTSEL before setting MSGVAL again (latest with the same write access that sets MSGVAL) in order to prevent the storage of a frame that belongs to the old context of the message object. Thus message object reconfiguration should consist of the following sequence of steps: 1. Clear MSGVAL. 2. Reconfigure message object while MSGVAL = 0. 3. Clear RTSEL and set MSGVAL. RXEN Bit MOCTR.RXEN enables a message object for frame reception. A message object can receive CAN messages from the CAN bus only if RXEN = 1. The MultiCAN evaluates RXEN only during receive acceptance filtering. After receive acceptance filtering RXEN is ignored, i.e. the value of RXEN has no influence on the actual storage of a received message in a message object. Bit RXEN enables a "soft phase out" of a message object: When the user clears RXEN then a currently received CAN message for which the message object has won acceptance filtering is still stored in the message object, but for subsequent messages the message object no longer wins receive acceptance filtering. RXUPD, NEWDAT and MSGLST An ongoing frame storage process is indicated with the RXUPD ("Receive Updating") bit in the Message Object Control Register. The MultiCAN module sets RXUPD with the start and clears RXUPD with the end of a message object update (which consists of frame storage as well as flag updates). After storing the received frame (identifier, IDE bit, DLC and for data frames also the data field) in the message object NEWDAT ("New Data") is set by the MultiCAN. If NEWDAT was already set then also MSGLST ("Message Lost") is set in order to indicate data loss. The RXUPD and NEWDAT flags may be used by the CPU to read consistent frame data from the message object during ongoing CAN operation. The following steps are recommended: 1. Clear NEWDAT 2. Read message content (identifier, data etc.) from message object 3. Read Message Object Control Register and check that both NEWDAT and RXUPD are cleared. If this is not the case then goto back to step 1. 4. As step 3 was successful, the read message content is consistent, i.e. has not been updated by the MultiCAN while reading. User's Manual MultiCAN, V1.7d2 20-30 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller The bits RXUPD, NEWDAT and MSGLST work in the same fashion for the reception of data as well as remote frames. 20.2.8.2 Frame Transmission The process of message object transmission is illustrated in Figure 20-14. In addition to copying the message content (identifier, IDE bit, RTR = DIR bit, DLC and for data frames also the data field) to the internal transmit buffer of the CAN node that the message object belongs to, also several status flags are served and monitored in order to enable consistent data handling. The transmission process (after transmit acceptance filtering) of a given message object makes no difference between remote and data frames. MSGVAL, TXRQ, TXEN0, TXEN1 For the MSGVAL bit the section "MSGVAL" on Page 20-29 for frame reception is also valid for transmission. A message may only be transmitted if all four bits MSGVAL ("Message Valid"), TXRQ ("Transmit Request"), TXEN0 ("Transmit Enable 0"), TXEN1("Transmit Enable 1") of the Message Object Control Register are set (1) (see also Figure 20-9). Although these bits are equivalent with respect to the transmission process, they have different semantics: Table 20-4 Bit MSGVAL TXRQ Bits to set (1) in MOCTR for message transmission Description Message Valid Main Switch of the Message Object Transmit Request Standard Transmit Request bit. The CPU should set this bit whenever a message object shall be transmitted. TXRQ is cleared automatically at the end of the successful transmission, except when there are new data (indicated by NEWDAT = 1) to be transmitted. When the single transmit trial bit is set (STT = 1) in the Message Object Function Register then TXRQ is already cleared by the MultiCAN when the content of the message object is copied to the transmit frame buffer of the CAN node. A received remote request (i.e. remote frame received on CAN bus) sets bit TXRQ to request the transmission of the corresponding data frame. User's Manual MultiCAN, V1.7d2 20-31 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Table 20-4 Bit TXEN0 Controller Area Network (MultiCAN) Controller Bits to set (1) in MOCTR for message transmission (cont'd) Description Transmit Enable 0 This bit may be temporarily cleared by the CPU to suppress the transmission of this object when it writes new content to the data field. This avoids transmission of inconsistent frames which consist of a mixture of old and new data. Remote requests are still accepted during TXEN0 = 0, but transmission of the data frame is suspended until the CPU re-enables transmission (TXEN0 = 1). Transmit Enable 1 This bit is used in transmit FIFOs to select the message object which is transmit active within the FIFO structure. For message objects which are not transmit FIFO elements TXEN1 may either be set to 1 permanently or be used as a second, independent transmission enable bit. TXEN1 RTSEL When a message object has been identified to be transmitted next (by acceptance filtering) then the MultiCAN set bit MOCTR.RTSEL ("Receive/Transmit Selected"). When the MultiCAN copies the message object to the transmit buffer it checks bit RTSEL and the message is transmitted only if RTSEL = 1. After the successful transmission of the message bit RTSEL is checked again and message postprocessing is only performed if RTSEL = 1. A complete reconfiguration of an operating message object should be done by means of the following steps: 1. Clear MSGVAL ("Message Valid"). 2. Reconfigure message object while MSGVAL = 0. 3. Clear RTSEL and set MSGVAL. Here clearing RTSEL ensures that the message object is disconnected from an ongoing/scheduled transmission and no message object processing (copying message to transmit buffer incl. clearing NEWDAT, clearing TXRQ, time stamp update, message interrupt etc.) within the old context of the object may occur after the message object becomes valid again, but within a new context. NEWDAT When the content of a message object has been transferred to the transmit buffer of the CAN node then bit NEWDAT ("New Data") is cleared to indicate that the transmit data of the message object are no longer new. User's Manual MultiCAN, V1.7d2 20-32 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller When the CAN transmission of the frame is successful and NEWDAT is still cleared (i.e. no new data have been copied to the message object in the meantime) then TXRQ ("Transmit Request") is cleared automatically. If, however, the NEWDAT bit has been set again by the CPU (because a new frame shall be transmitted) then TXRQ is not cleared in order to enable the transmission of the new data. User's Manual MultiCAN, V1.7d2 20-33 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller Start receiving CAN frame Get data from gateway/FIFO source no Object wins acc. filtering? yes RTSEL := 1 Time Milestones 1 no CAN rec. successful? yes no MSGVAL & RTSEL =1? yes RXUPD := 1 MSGVAL =1? yes RXUPD := 1 no 2 Copy frame to message object Copy frame to message object 3 yes DIR =1? no yes NEWDAT =1? no NEWDAT := 1 RXUPD := 0 RXPND := 1 TXRQ := 1 in this or in foreign objects MSGLST := 1 4 yes RXIE =1? no Done MCA05845 MSGLST := 1 Figure 20-13 Data Delivery to Message Object by MultiCAN Module User's Manual MultiCAN, V1.7d2 20-34 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller Object wins transmit acc. filtering RTSEL := 1 Time Milestones 1 Copy Message to internal transmit buffer MSGVAL & TXRQ & TXEN0 & TXEN1 = 1 continuously valid yes RTSEL = 1? yes Request transmission of internal buffer on CAN bus NEWDAT := 0 no no 2 Transmission successful? yes MSGVAL & RTSEL =1? yes NEWDAT = 1? yes no no no TXRQ := 0 TXIE =1? yes Issue interrupt no 3 Done MCA05846 Figure 20-14 Transmission of a Message Object User's Manual MultiCAN, V1.7d2 20-35 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller 20.2.9 Message Object Functionality This section describes the functionality that is related to each individual Message Object. 20.2.9.1 Standard Message Object Mode Standard message mode is selected via MMC = 0000B in the Message Object Function Control Register of the message object. In this mode a message object may transmit and receive CAN frames according to the basic rules as described in the previous sections. Additional services such as Single Data Transfer Mode or Single Transmit Trial (see sections below) are available and may be selected individually by the user. 20.2.9.2 Single Data Transfer Mode Single Data Transfer Mode is a useful feature in order to broadcast data over the CAN bus without unintended doubling of information. Single Data Transfer Mode is selected via bit SDT in the Message Object Function Register of the message object. Message Reception When a received message is stored in a message object and further messages are stored in the same message object before the CPU reads the first message object, then the content of the first message gets lost and is replaced with the content of the subsequent messages (indicated by MSGLST = 1). If SDT = 1 (Single Data Transfer Mode activated) then the MultiCAN controller automatically clears the MSGVAL bit of the message object after the storage of a received data frame to prevent the reception of further messages. The reception of a remote frame does not lead to the clearance of MSGVAL. Message Transmission When a message object receives a series of multiple remote requests then it transmit several data frames in response to the requests. If the data within the message object has not been updated in the time between the transmissions, the same data may be represented more than once on the CAN bus. In Single Data Transfer Mode (SDT = 1) this is avoided because the MultiCAN controller automatically clears MSGVAL after the successful transmission of a data frame. The transmission of a remote frame does not clear MSGVAL. 20.2.9.3 Single Transmit Trial If the bit STT in the message object function register is set (STT = 1) then the transmission request is cleared (TXRQ := 0) when the frame content of the message User's Manual MultiCAN, V1.7d2 20-36 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller object has been copied to the internal transmit buffer of the CAN node. Thus the transmission of the message object is not tried again when it fails due to CAN bus errors. 20.2.9.4 Message Object FIFO Structure In case of high CPU load it may be difficult to process a series of CAN frames in time. This may happen for the short term reception of multiple messages as well as the transmission of a series with tight due date. Therefore a FIFO buffer structure has been implemented in order to avoid loss of incoming messages and to minimize the setup time for outgoing messages. The FIFO structure may also be used to automate the reception or transmission of a series of CAN messages and to generate a single message interrupt when the whole series is done. There may be as many FIFOs in parallel as are required by the application. The number of FIFOs and their size are only limited by the number of message objects available. A FIFO may be installed, resized and deinstalled any time, even during CAN operation. The basic structure of a FIFO is shown in Figure 20-15. A FIFO consists of a single base object (shown on the left side) and several slave objects (shown on the right side). The slave objects are chained together in the same list structure. The base object may be allocated to any list. Although Figure 20-15 shows the base object as a separate item apart from the slave objects, it is also possible to integrate the base object at any place into the chain of slave objects, so that the base object is slave object, too (not possible for gateways). The FIFO structure fully relies on the list structure. The absolute object numbers of the message objects have no impact on the operation of the FIFO. The base object needs not be allocated to the same list as the slave objects. Only the slave object must be allocated to a common list (as they are chained together). The BOT, CUR and TOP pointer link the base object to the slave objects, no matter whether the base object is allocated to the same or to another list than the slave objects. The absolute minimum FIFO would consist of a single message object which is both FIFO base and FIFO slave (not very useful). The biggest possible FIFO would use all message objects of the MultiCAN module. Any sizes between these extremes are possible. In the FIFO base object the boundaries of the FIFO are defined. The BOT field in the FIFO/Gateway Pointer Register of the base object points to the first (bottom) slave element in the FIFO. The TOP field in the FIFO/Gateway Pointer Register of the base object points to the last (top) slave element. The CUR field in the FIFO/Gateway Pointer Register of the FIFO base object points to the actual slave object selected by the MultiCAN for message transfer. When a message transfer takes place with this object then CUR is moved to the next position. If CUR has already reached the top of the FIFO (CUR = TOP) then it is wrapped around to the bottom of the FIFO (CUR := BOT). Otherwise CUR is moved to the next message object in the list structure of the slave objects (CUR := PNEXT of current object). This scheme User's Manual MultiCAN, V1.7d2 20-37 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller yields a circular FIFO structure where the fields BOT and TOP just establish the link from the last to the first element, which is missing in the linear structure. The SEL field in the FIFO/Gateway Pointer register of the base object may be used for monitoring purposes. It allows to select any slave object and to generate a message interrupt if the CUR pointer reaches the value of SEL. Thus SEL offers a convenient way to determine the end of a predefined series of message transfers, or it may be used to issue a warning to the CPU when the FIFO gets full. User's Manual MultiCAN, V1.7d2 20-38 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller PPREV PNEXT=f2 Object f1 PPREV=f1 PNEXT=f3 PPREV PNEXT BOT=f1 CUR=fi TOP=fn Base Object PPREV=f[i-1] PNEXT=f[i+1] Object fi Object f2 PPREV=f[n-1] PNEXT Object fn msgobj_fifo Figure 20-15 FIFO Structure with FIFO Base and n FIFO Destinations (Slaves) User's Manual MultiCAN, V1.7d2 20-39 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller 20.2.9.5 Receive FIFO The Receive FIFO structure is used to buffer incoming (received) remote or data frames. A Receive FIFO is selected via MMC = 0001B in the Message Object Function Control Register of the FIFO base object. This MMC code automatically designates the message object as FIFO base object. The message mode of the FIFO slave objects are not relevant for the operation of the Receive FIFO. When the FIFO base object receives a frame from the CAN node it belongs to, then the frame is not stored in the base object. Instead the message is stored in the message object that is selected by the CUR pointer in the FIFO/Gateway Pointer Register of the FIFO base object. The message object selected by CUR receives the CAN message as if it were the direct receiver of the message. However, MMC = 0000B is implicitly assumed for the FIFO slave, i.e. a standard message delivery is performed. The actual message mode (MMC) of the FIFO slave is ignored. There is also no extra acceptance filtering to match the received frame against the identifier, IDE bit and DIR bit of the slave object. When the FIFO base object receives a CAN frame then the MultiCAN moves the current pointer CUR to the next message object in the FIFO structure, which will then be used to store the next incoming message. The old value of CUR is used for the current transfer. IF bit OVIE is set in the Message Object Function Register of the FIFO base object and the pointer CUR reaches the value stored in SEL then a FIFO overflow interrupt request is generated. The interrupt request is generated on interrupt output line TXINP (TXINP of the base object) immediately after the storage of the received frame into the slave object. Transmit interrupts are still generated if TXIE is set. A CAN message is stored in a FIFO slave only if MSGVAL = 1 in both FIFO base and slave object. In order to avoid direct reception of a message by a slave message object, as if it was an independent message object and not a part of a FIFO, the bit RXEN of each slave object must be cleared. The setting of the bit RXEN is "don't care" only if the slave object is located in a list not assigned to a CAN node. User's Manual MultiCAN, V1.7d2 20-40 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller 20.2.9.6 Transmit FIFO The Transmit FIFO structure is used to buffer a series of data or remote frames to be transmitted. A transmit FIFO consists of one base message object and one or more slave message objects. A Transmit FIFO base object is selected via MMC = 0010B in the Message Object Function Control Register of the FIFO base object. Unlike the Receive FIFO the Transmit FIFO requires the explicit declaration of the FIFO slave objects via MMC = 0011B. The CUR pointer of all slave objects must point back to the Transmit FIFO Base Object (to be initialized by user). The TXEN1 bits of all message objects except the one which is selected by the CUR pointer of the base object must be cleared (to be initialized by user). TXEN1 of the message object selected by CUR must be set. CUR may be initialized to any FIFO slave object. When tagging the message objects of the FIFO valid to start the operation of the FIFO then the base object must be tagged valid (MSGVAL := 1) first. When a Transmit FIFO shall be deinstalled during operation, then the slave objects must be tagged invalid (MSGVAL := 0) first. The Transmit FIFO uses the TXEN1 bit in the Message Object Control Register of all FIFO elements to select the actual message for transmission. Transmit acceptance filtering evaluates TXEN1 for each message object and a message object may win transit acceptance filtering only if TXEN1 is set. When a FIFO element has transmitted a message then in addition to standard transmit postprocessing (clear TXRQ, transmit interrupt etc.) the MultiCAN clears TXEN1 in that message object and moves the CUR pointer in the corresponding FIFO base object to the next message object to be transmitted. TXEN1 is set automatically in the next message object. Thus TXEN1 moves along the FIFO structure like a token to select the active element. IF bit OVIE is set in the Message Object Function Register of the FIFO base object and the pointer CUR reaches the value stored in SEL then a FIFO overflow interrupt request is generated. The interrupt request is generated on interrupt output line as defined by RXINP (RXINP of the base object) when postprocessing of the received frame is done. Receive interrupts are still generated for the Transmit FIFO base object if bit RXIE is set. User's Manual MultiCAN, V1.7d2 20-41 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller 20.2.9.7 Gateway Mode The Gateway Mode allows to establish an automatic information transfer between two independent CAN bus systems without CPU interaction. The Gateway Mode operates on message object level. In Gateway mode, information is transferred between two message objects, resulting in an information transfer between the two CAN nodes to which the message objects are allocated. A gateway may be established between any pair of CAN nodes and there may be as many gateways as there are message objects available to build the gateway structure. Gateway Mode is selected via MMC = 0100B in the Message Object Function Control Register of the gateway source object. The gateway destination object is selected by the CUR pointer in the FIFO/Gateway Pointer Register of the source object. The gateway destination object just needs to be valid (MSGVAL = 1), all other settings are not relevant for the information transfer from the source object to the destination object. A gateway source object behaves like a standard message objects, but when a CAN frame has been received and stored in the source object, some additional actions are performed by the MultiCAN (Figure 20-16): 1. If bit DLCC is set in the Message Object Function Register of the source object, then the DLC code is copied from the source object to the destination object. 2. if bit IDC is set in the Message Object Function Register of the source object, then the identifier and the IDE bit are copied from the source object to the destination object. 3. if bit DATC is set in the Message Object Function Register of the source object, then the data field is copied from the source object to the destination object. 4. If bit GDFS is set in the Message Object Function Register of the source object, then TXRQ is set in the Message Object Control Register of the destination object. 5. RXPND and NEWDAT are set in the Message Object Control Register of the destination object. 6. A message interrupt request is generated for the destination object if RXIE is set in the Message Object Control Register of the destination object. 7. The current pointer CUR in the FIFO/Gateway Pointer Register of the source object is moved to the next destination object according to the FIFO rules as described in Chapter 20.2.9.4. A gateway with a single (static) destination object is obtained by means of setting TOP = BOT = CUR = destination object. The link from the source to the destination object works in the same way as the link from a FIFO source to a FIFO slave. This means that a gateway with an integrated destination FIFO may be created (Figure 20-15), where the object on the left in Figure 20-15 is the gateway source object and the message objects on the right side are the gateway destination objects. The gateway works in the same way for the reception of data frames (source object is receive object, i.e. DIR = 0) as wall as for the reception of remote frames (source object is transmit object). User's Manual MultiCAN, V1.7d2 20-42 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller Source CAN bus Destination CAN bus Pointer to Destination Object CUR Identifier + IDE copy if IDCsource = 1 copy if DLCCsource = 1 copy if DATCsource = 1 set if GDFSsource = 1 set set Identifier + IDE DLC DLC Data Data TXRQ NEWDAT RXPND Dest. Object msgobj_gateway Source Object, MMC = 0100B Figure 20-16 Gateway Transfer from Source to Destination User's Manual MultiCAN, V1.7d2 20-43 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller 20.2.9.8 Foreign Remote Requests When a remote frame received on a CAN node is stored in a message object, then a transmit request is set in order to trigger the answer (data frame transmission) to the request or to automatically issue a secondary request. If bit FRREN is cleared (FRREN = 0) in the Function Control register of the message object where the remote request is stored, then TXRQ is set in the Control Register of the same message object. If bit FRREN is set (FRREN = 1: foreign remote request enabled) then TXRQ is set in the message object that is referenced by pointer CUR in the FIFO/Gateway Pointer Register. The value of CUR is, however, not changed by this feature. Although the foreign remote request feature works independently from the selected message mode, it is especially useful for gateways to issue a remote request on the source of a gateway upon the reception of a remote request on the gateway destination. According to the setting of FRREN in the gateway destination object there are two ways to handle remote requests that appear on the destination side (assuming that the source object is a receive object and the destination is a transmit object, i.e. DIRsource = 0 and DIRdestination = 1): FRREN = 0 in the Gateway Destination Object 1. A remote frame is received by gateway destination. 2. TXRQ is set automatically in the gateway destination object. 3. A data frame with the current data stored in the destination object is transmitted on the destination bus. FRREN = 1 in the Gateway Destination Object 1. A remote frame is received by gateway destination. 2. TXRQ is set automatically in the gateway source object (must be referenced by CUR pointer of the destination object). 3. A remote request is transmitted by the source object (which is a receive object) on the source CAN bus. 4. The receiver of the remote request responds with a data frame on the source bus. 5. The data frame is stored in the source object. 6. The data frame is copied to the destination object (gateway action). 7. TXRQ is set in the destination object (assuming GDFSsource = 1). 8. The new data stored in the destination object is transmitted on the destination bus, as response to the initial remote request on the destination bus. User's Manual MultiCAN, V1.7d2 20-44 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller 20.2.10 MultiCAN Kernel Registers The register set of the MultiCAN module consists of three distinct subsets: 1. The Global Module Registers apply to the whole MultiCAN module and exist only once. 2. The CAN Node Registers apply to a single CAN node and thus exist once for each CAN node. 3. The collection of Message Object Registers defines a single message object and thus exists once for each message object. 20.2.10.1 Register Address Map Table 20-5 shows the address map of the MultiCAN module with respect to the base address of the MultiCAN module. Table 20-5 MultiCAN Address Map (Relative to MultiCAN Base Address) Start address +100H +1000H Total Range +100H to + 1FFH +200H to + 2FFH +1000H to + 13FFH Register Group Global Module Registers Message Objects n = 0 - 127 CAN Node Registers for CANx, x = 0 - 4 +200H User's Manual MultiCAN, V1.7d2 20-45 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Global Module Registers The global module registers exist only once. They are listed in Table 20-6 with their relative address with respect to the start address of the Global Module Registers. Table 20-6 Register LIST0L LIST0H LIST1L LIST1H LIST2L LIST2H LIST3L LIST3H LIST4L LIST4H LIST5L LIST5H LIST6L LIST6H LIST7L LIST7H MSPND0L MSPND0H MSPND1L MSPND1H MSPND2L MSPND2H MSPND3L MSPND3H MSPND4L MSPND4H MSPND5L User's Manual MultiCAN, V1.7d2 Controller Area Network (MultiCAN) Controller Relative Addresses of Global Module Registers Rel. Address 100H 102H 104H 106H 108H 10AH 10CH 10EH 110H 112H 114H 116H 118H 11AH 11CH 11EH 140H 142H 144H 146H 148H 14AH 14CH 14EH 150H 152H 154H Full Name of Register List Registers 0 Low List Registers 0 High List Registers 1 Low List Registers 1 High List Registers 2 Low List Registers 2 High List Registers 3 Low List Registers 3High List Registers 4 Low List Registers 4 High List Registers 5 Low List Registers 5 High List Registers 6 Low List Registers 6 High List Registers 7 Low List Registers 7 High Message Pending Registers 0 Low Message Pending Registers 0 High Message Pending Registers 1 Low Message Pending Registers 1 High Message Pending Registers 2 Low Message Pending Registers 2 High Message Pending Registers 3 Low Message Pending Registers 3 High Message Pending Registers 4 Low Message Pending Registers 4 High Message Pending Registers 5 Low 20-46 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Table 20-6 Register MSPND5H MSPND6L MSPND6H MSPND7L MSPND7H MSID0 MSID1 MSID2 MSID3 MSID4 MSID5 MSID6 MSID7 MSIMASKL MSIMASKH PANCTRL PANCTRH MCR MITR Controller Area Network (MultiCAN) Controller Relative Addresses of Global Module Registers Rel. Address 156H 158H 15AH 15CH 146H 180H 184H 188H 18CH 190H 194H 198H 19CH 1C0H 1C2H 1C4H 1C6H 1C8H 1CCH +120H ... +13EH +148H ... +17EH +188H ... +1BEH +1CEH ... +1FEH Full Name of Register Message Pending Registers 5 High Message Pending Registers 6 Low Message Pending Registers 6 High Message Pending Registers 7 Low Message Pending Registers 7 High Message Index Registers 0 Message Index Registers 1 Message Index Registers 2 Message Index Registers 3 Message Index Registers 4 Message Index Registers 5 Message Index Registers 6 Message Index Registers 7 Message Index Mask Register Low Message Index Mask Register High Panel Control Register Low Panel Control Register High Module Control Register Module Interrupt Trigger Register Reserved CAN Node Registers The registers of a CAN node are located at consecutive 32 bit addresses according toTable 20-7 which shows the relative address of the 32 bit CAN Node Registers with respect to the base address of CAN node register block. The CAN Node Register block exists once for each CAN node. User's Manual MultiCAN, V1.7d2 20-47 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Table 20-7 Register NCR NSR NIPR NPCR NBTRL NBTRH NECNTL NECNTH NFCRL NFCRH Controller Area Network (MultiCAN) Controller Relative Addresses of CAN Node Registers Rel. Address Full Name of Register +00H +04H +08H +0CH +10H +12H +14H +16H +18H +1AH +1CH to +FEH CAN Node Control Register CAN Node Status Register CAN Node Interrupt Pointer Register CAN Node Port Control Register CAN Node Bit Timing Register Low CAN Node Bit Timing Register High CAN Node Error Counter Register Low CAN Node Error Counter Register High CAN Node Frame Counter Register Low CAN Node Frame Counter Register High Reserved Message Object Registers The registers of a message object are located at consecutive 32 bit addresses according to Table 20-8 which shows the relative address of the 32 bit Message Object Registers with respect to the base address of the Message Object. Table 20-8 Register MOFCRL MOFCRH MOFGPRL MOFGPRH MOIPRL MOIPRH MOAMRL MOAMRH MODATALL MODATALH MODATAHL Relative Addresses of Message Object Registers Rel. Address +00H +02H +04H +06H +08H +0AH +0CH +0EH +10H +12H +14H Full Name of Register Message Object Function Control Register Low Message Object Function Control Register High Message Object FIFO/Gateway Pointer Reg. Low Message Object FIFO/Gateway Pointer Reg. High Message Object Interrupt Pointer Register Low Message Object Interrupt Pointer Register High Message Object Acceptance Mask Register Low Message Object Acceptance Mask Register High Message Object Data Register Low Low Message Object Data Register Low High Message Object Data Register High Low User's Manual MultiCAN, V1.7d2 20-48 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Table 20-8 Register MODATAHH MOARL MOARH MOCTRL MOCTRH Controller Area Network (MultiCAN) Controller Relative Addresses of Message Object Registers Rel. Address +16H +18H +1AH +1CH +1EH Full Name of Register Message Object Data Register High High Message Object Arbitration Register Low Message Object Arbitration Register High Message Object Control Register Low Message Object Control Register High Registers Description User's Manual MultiCAN, V1.7d2 20-49 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller 20.2.10.2 Module Identification Register ID Module Identification Register 15 14 13 12 11 10 9 (08H) 8 7 6 5 4 Reset Value: 4001H 3 2 1 0 MOD_NUMBER r MOD_REV r Field MOD_REV Bits [7:0] Type Description r Module Revision Number Value Bits 7-0 bits are used for module revision numbering. The value of the module revision number starts with 01H (first revision), 02H, 03H, ... up to FFH. Module Identification Number Value Bits 15-8 are used for module identification. The MultiCAN has the module number 40H. MOD_NUMBER [15:8] r User's Manual MultiCAN, V1.7d2 20-50 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller 20.2.10.3 Command Panel All list operations such as allocation, deallocation and relocation of message objects within the list structure are performed via the Command Panel. It is not possible to modify the list structure directly by means of writing to the message objects and the LIST registers. A new command is started by means of writing the command arguments and the command code to the Panel Control Register. PANCTRH Panel Control Register 15 14 13 12 11 10 9 (1C6H) 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 PANAR2 rwh PANAR1 rwh Field PANAR1 PANAR2 Bits [7:0] [15:8] Type Description rwh rwh Panel Argument 1 Panel Argument 2 PANCTRL Panel Control Register 15 14 13 0 r 12 11 10 9 (1C4H) 8 7 6 5 4 Reset Value: 0301H 3 2 1 0 RBU BUS SY Y rh rh PANCMD rwh Field PANCMD Bits [7:0] Type Description rwh Panel Command A new command is started by means of writing the command number to PANCMD. At the end of a panel command the NOP (no operation) command code is automatically written to PANCMD. User's Manual MultiCAN, V1.7d2 20-51 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field BUSY Bits 8 Controller Area Network (MultiCAN) Controller Type Description rh Panel Busy 0 Panel has finished command and is ready to accept a new command. 1 Panel operation is in progress. Result Busy 0No update of PANAR1 and PANAR2 is scheduled by the list controller. 1A list command is running (BUSY = 1) that will write results to PANAR1 and PANAR2, but the results are not yet available. reserved; returns '0' if read; should be written with '0'; RBUSY 9 rh 0 [10:15] r User's Manual MultiCAN, V1.7d2 20-52 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Panel Commands A panel operation consists of a command code to be written to PANCMD and up to 2 panel arguments (PANAR1, PANAR2). Commands that have a return value deliver it to the PANAR1 field. Commands that deliver an error flag post it to bit 7 of PANAR2. Table 20-9 0 Panel Commands PANAR1 Command Description No Operation Writing value 0 to PANCMD has no effect. No new command is started. Result: Bit 7 : ERR Bit 6-0 : undefined Initialize Lists Run the initialization sequence to reset the CTRL and LIST field of all message objects and the list registers LIST[7:0] to their reset values. This results in the deallocation of all message objects. The initialization command requires that bits INIT and CCE are set in the Node Control Register of all CAN nodes 0-4. An ERR bit (bit 7 of PANAR2) reports the success of the operation: 0Success 1Not all INIT and CCE bits are set. Thus no initialization is performed. The initialization command is automatically performed with each reset of the MultiCAN module, but with the exception that all message object registers are reset. Argument: Message Object Number Static Allocate Allocate a given message object to a list. The message object is removed from the list that it currently belongs to and appended to the end of the list. given by PANAR2. This command is also used to deallocate a message object. In this case the target list is the list of unallocated elements. (PANAR2 = 0). Controller Area Network (MultiCAN) Controller Code PANAR2 1 2 Argument: List Index User's Manual MultiCAN, V1.7d2 20-53 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Table 20-9 3 Panel Commands PANAR1 Result: Message Object Number Command Description Dynamic Allocate Allocate the first message object of the list of unallocated objects to the selected list. The message object is appended to the end of the list. The message number of the message object is returned in PANAR1. An ERR bit (bit 7 of PANAR2) reports the success of the operation: 0Success. 1The operation has not been performed because the list of unallocated elements was empty. Controller Area Network (MultiCAN) Controller Code PANAR2 Argument: List Index Result: Bit 7 : ERR Bit 6-0 : undefined 4 Argument: Argument: Static Insert Before Destination Object Source Remove a message object (source object) Number Object from the list that it currently belongs to and Number insert it before a given destination object into the list structure of the destination object. The source object thus becomes the predecessor of the destination object. Argument: Destination Object Number Result: Bit 7 : ERR Bit 6-0 : undefined Result: Object Number of inserted object Dynamic Insert Before Insert a new message object before a given destination object. The new object is taken from the list of unallocated elements (the first element is chosen). The number of the new object is delivered as result to PANAR1. An ERR bit (bit 7 of PANAR2) reports the success of the operation: 0Success. 1The operation has not been performed because the list of unallocated elements was empty. 5 6 Argument: Static Insert Behind Argument: Remove a message object (source object) Destination Object Source from the list that it currently belongs to and Object Number insert it behind a given destination object into Number the list structure of the destination object. The source object thus becomes the successor of the destination object. 20-54 V1.0, 2007-06 User's Manual MultiCAN, V1.7d2 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Table 20-9 7 Panel Commands PANAR1 Result: Object Number of inserted object Command Description Dynamic Insert Behind Insert a new message object behind a given destination object. The new object is taken from the list of unallocated elements (the first element is chosen). The number of the new object is delivered as result to PANAR1. An ERR bit (bit 7 of PANAR2) reports the success of the operation: 0Success. 1The operation has not been performed because the list of unallocated elements was empty. 8255 Reserved Controller Area Network (MultiCAN) Controller Code PANAR2 Argument: Destination Object Number Result: Bit 7 : ERR Bit 6-0 : undefined User's Manual MultiCAN, V1.7d2 20-55 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller 20.2.10.4 Module Setup The Module Control Register contains basic settings to define the operation of the module. MCR Module Control Register 15 14 13 12 11 10 9 (1C8H) 8 7 6 0 r 5 4 Reset Value: 0000H 3 2 1 0 MPSEL rw Field MPSEL Bits Type Description Message Pending Selector MPSEL allows to calculate the bit position of the message pending bit to be set after a message reception/transmission interrupt from a mixture of RXINP,TXINP and MPN (Message Pending Number). With the definitions INP ... RXINP upon message reception, TXINP upon message transmission MPN ... 8 bit message pending number the effective position of the message pending bit is calculated according to the formula POS = ( (INP & MPSEL) << 4 ) | (MPN & (~MPSEL<< 4) ) | ( MPN & = 0x0FH ) If MPSEL = 0 then the position is simply given by the message pending number MPN. If MPSEL = 1111B then the upper 4 bits of the position is given by the interrupt output line pointer INP and the lower 4 bits are taken from MPN. [15:12] rw 0 [11:0] r reserved; returns '0' if read; should be written with '0'; User's Manual MultiCAN, V1.7d2 20-56 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller 20.2.10.5 Interrupt Trigger Register ITR The Interrupt Trigger Register ITR allows to trigger interrupt requests on each interrupt output line by software. MITR Module Interrupt Trigger Register 15 14 13 12 11 10 9 (1CCH) 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 IT[15:0] w Field IT[15:0] Bits [15:0] Type Description w Interrupt Trigger Writing value 1 to bit n (n = 15-0) generates an interrupt request on interrupt output line n. Writing value 0 has no effect. Reading delivers always 0. More than one interrupt request may be generated at the same time by means of writing 1 to several bit positions of IT with a single write access. User's Manual MultiCAN, V1.7d2 20-57 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller 20.2.10.6 List Pointer Each CAN node has an own list which defines the message objects that are allocated to the respective node. In addition to that there is the list of all unallocated objects and finally a general purpose user list which is not associated to a CAN node. Each list is assigned a list index according to Table 20-3 "List Indices" on Page 20-15. Each list is terminated with a List Register which defines the first and the last element in the list. LIST0H List Register 0 High LISTyH (y = 1-7) List Register y High 15 14 13 12 0 r 11 10 9 (102H) (102H+y*4) 8 EMP TY rh 7 6 5 4 Reset Value: 007FH Reset Value: 0100H 3 2 1 0 SIZE rh Field SIZE Bits [7:0] Type Description rh Size of List The number of elements in the list l is given by #elements = SIZE + 1, provided the list is not empty. If the list l is empty, the value of SIZE is zero. List Empty Indication 0At least one message object is allocated to list l. 1No message object is allocated to the list l. Reserved; read as 0; should be written with 0. EMPTY 8 rh 0 [15:9] r User's Manual MultiCAN, V1.7d2 20-58 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary LIST0L List Register 0 Low LISTxL (x = 1-7) List Register x Low 15 14 13 12 11 10 9 Controller Area Network (MultiCAN) Controller (100H) (100H+x*4) 8 7 6 5 4 Reset Value: 7F00H Reset Value: 0000H 3 2 1 0 END rh BEGIN rh Field BEGIN END Bits [7:0] [15:8] Type Description rh rh List Begin Pointer to the first message object in the list l. END Pointer Pointer to the last message object in the list l. User's Manual MultiCAN, V1.7d2 20-59 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller 20.2.10.7 Message Notifications When a message object generates an interrupt request upon the transmission or reception of a message, then the request is routed to the interrupt output line selected by TXINP or RXINP of the message object. As there are more message objects than interrupt output lines, an interrupt routine typically processes requests from more than one message object. Therefore a priority selection mechanism is implemented in the MultiCAN module to select the highest priority object within a collection of message objects.The Message Pending Register contains the interrupt pending. MSPNDkH (k = 0-7) Message Pending Register k High (142H+k*4) 15 14 13 12 11 10 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 PND[31:16] rwh Field PND[31:16] Bits [15:0] Type Description rwh Message Pending When a message interrupt occurs then the message object sets a bit in one of the MSPND register, where the bit position is given by the MPN[4:0] field of the IPR register of the message object. The register selection n is given by the higher bits of MPN. The register bits may be cleared by SW (write 0), but writing 1 has no effect. MSPNDkL (k = 0-7) Message Pending Register k Low (140H+k*4) 15 14 13 12 11 10 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 PND[15:0] rwh Field PND[15:0] Bits [15:0] Type Description rwh Message Pending The same as PND[31:16] User's Manual MultiCAN, V1.7d2 20-60 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller Each Message Pending Register has a Message Index Register associated to it. The Message Index Register shows the active (set) pending bit with lowest bit position within groups of pending bits. MSIDk (k = 0-7) Message Index Register k 15 14 13 12 11 0 R 10 9 (180H+k*4) 8 7 6 5 4 Reset Value: 0020H 3 2 1 0 INDEX rh Field INDEX Bits [5:0] Type Description rh Message Pending Index The value of INDEX is given by the bit position i of the pending bit of MSPNDk with the following properties: 1. MSPNDk[i] & IM[i] = 1 2. i = 0 or MSPNDk[i-1:0] & IM[i-1:0] = 0 If no bit of MSPNDk satisfies these conditions then INDEX reads 100000B. Thus INDEX shows the position of the first pending bit of MSPNDk, where only those bits of MSPNDk which are selected in the Message Index Mask Register are taken into account. Reserved: read as 0; should be written with 0. 0 [15:6] r User's Manual MultiCAN, V1.7d2 20-61 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller The Message Index Mask Register selects individual bits for the calculation of the Message Pending Index. The Message Index Mask Register is used commonly for all Message Pending registers and their associated Message Index registers. MSIMASKH Message Index Mask Register High 15 14 13 12 11 10 9 (1C2H) 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 IM[31:16] rw Field IM[31:16] Bits [15:0] Type Description rw Message Index Mask Only those bits in MSPNDk for which the corresponding Index Mask bits are set contribute to the calculation of the Message Index. MSIMASKL Message Index Mask Register Low 15 14 13 12 11 10 9 (1C0H) 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 IM[15:0] rw Field IM[15:0] Bits [15:0] Type Description rw Message Index Mask Only those bits in MSPNDk for which the corresponding Index Mask bits are set contribute to the calculation of the Message Index. 20.2.11 CAN Node Specific Registers The CAN node specific registers exist once for each CAN node of the MultiCAN module.They contain information that is directly related to the operation of the CAN nodes and which may not be shared among the nodes. The Node Control Register contains basic settings that define the operation of the CAN node and the interaction of the CAN node with the message objects. User's Manual MultiCAN, V1.7d2 20-62 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary NCRx (x = 0-4) Node x Control Register 15 14 13 12 0 r 11 10 9 Controller Area Network (MultiCAN) Controller (200H+x*100H) 8 7 6 5 0 r 4 Reset Value: 0001H 3 2 1 0 SUS CAL CCE EN M rw rw rw CAN LECI ALIE TRIE INIT DIS E rw rw rw rw rwh Field INIT Bits 0 Type Description rwh Node Initialization 0 Resetting bit INIT enables the participation of the node in the CAN traffic. If the CAN node is in the bus off state then the ongoing bus off recovery (which does not depend on the INIT bit) is continued. With the end of the bus off recovery sequence the CAN node is allowed to take part in the CAN traffic. If the CAN node is not in the bus off state a sequence of 11 consecutive recessive bits must be detected before the node is allowed to take part in the CAN traffic. 1Setting this bit terminates the participation of this node in the CAN traffic. Any ongoing frame transfer is cancelled and the transmit line goes recessive. If the CAN node is in the bus off state then the running bus off recovery sequence is continued. If the INIT bit is still set after the successful completion of the bus off recovery sequence, i.e. after detecting 128 sequences of 11 consecutive recessive bits (11 x 1) then the CAN node leaves the bus off state but remains inactive as long as INIT remains set. Bit INIT is automatically set when the CAN node becomes `bus off' (see Page 20-12). Transfer Interrupt Enable If this bit is set, then an interrupt request is generated upon the successful reception or transmission of a CAN frame. The interrupt output line is selected by TRINP in the CAN Node Interrupt Pointer Register. TRIE 1 rw User's Manual MultiCAN, V1.7d2 20-63 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field LECIE Bits 2 Controller Area Network (MultiCAN) Controller Type Description rw LEC indicated Error Interrupt Enable If this bit is set, then an interrupt request is generated upon each update of the LEC field in the Node Status Register leading to LEC > 0 (CAN protocol error). The interrupt output line is selected by LECINP in the CAN Node Interrupt Pointer Register. Alert Interrupt Enable If this bit is set then an alert interrupt is generated on one of the following events: 1) A change of bit BOFF in the CAN Node Status Register. 2) A change of bit EWRN in the CAN Node Status Register. 3) A List Length Error, which also sets bit LLE in the CAN Node Status Register. 4) A List Object Error, which also sets bit LOE in the CAN Node Status Register. 5) Bit INIT has been set by the MultiCAN. The interrupt is requested on the interrupt output line selected by ALINP in the CAN Node Interrupt Pointer Register. CAN Disable Setting this bit disables the CAN node. The CAN node first waits until it is BUS IDLE or BUS OFF. Then bit INIT is automatically set and an alert interrupt is generated if bit ALIE is set. Configuration Change Enable 0 The Bit Timing Register, the Port Control Register and the Error Counter Register may only be read. All attempts to modify them are ignored. 1 The Bit Timing Register, the Port Control Register and the Error Counter Register may be read and written. ALIE 3 rw CANDIS 4 rw CCE 6 rw User's Manual MultiCAN, V1.7d2 20-64 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field CALM Bits 7 Controller Area Network (MultiCAN) Controller Type Description rw Can Analyze Mode If this bit is set then the CAN node operates in analyze mode. This means that messages may be received, but not transmitted. No acknowledge is sent on the CAN bus upon frame reception. Active error flags are sent recessive instead of dominant. The transmit line is continuously held at recessive (1) level. Bit CALM can be written only while bit INIT is set. Suspend Enable This bit allows to set the CAN node into suspend mode via OCDS (on chip debug support): 0 An OCDS suspend trigger is ignored by the CAN node. 1 An OCDS suspend trigger disables the CAN node: As soon as the CAN node becomes BUS IDLE or BUS OFF bit INIT is internally forced to `1' to disable the CAN node. The actual value of bit INIT remains unchanged. Bit SUSEN is reset via OCDS Reset. Reserved; read as 0; should be written with 0. SUSEN 8 rw 0 5, [15:9] r User's Manual MultiCAN, V1.7d2 20-65 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller The Node Status Register reports errors as well as successfully transferred CAN frames. NSRx (x = 0-4) Node x Status Register 15 14 13 0 r 12 11 10 9 (204H+x*100H) 8 7 6 5 4 Reset Value: 0000H 3 2 1 LEC rwh 0 SUS BOF EWR ALE RXO TXO LOE LLE ACK F N RT K K rh rwh rwh rh rh rwh rwh rwh Field LEC TXOK Bits [2:0] 3 Type Description rwh rwh Last Error Code The encoding of this bit field is detailed in Table 20-10. Message Transmitted Successfully 0 No successful transmission since last flag reset. 1 A message has been transmitted successfully (error free and acknowledged by at least another node). TXOK must be reset by software (write 0). Writing 1 has no effect. Message Received Successfully 0 No successful reception since last flag reset. 1 A message has been received successfully. RXOK must be reset by software (write 0). Writing 1 has no effect. RXOK 4 rwh User's Manual MultiCAN, V1.7d2 20-66 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field ALERT Bits 5 Controller Area Network (MultiCAN) Controller Type Description rwh Alert Warning The ALERT bit is set upon the occurrence of one of the following events (the same events which also trigger an alert interrupt if ALIE is set): 1) A change of bit BOFF in the CAN Node Status Register. 2) A change of bit EWRN in the CAN Node Status Register. 3) A List Length Error, which also sets bit LLE in the CAN Node Status Register. 4) A List Object Error, which also sets bit LOE in the CAN Node Status Register. 5) Bit INIT has been set by the MultiCAN. ALERT must be reset by software (write 0). Writing 1 has no effect. Error Warning Status 0 No warning limit exceeded. 1 One of the error counters REC or TEC reached the warning limit EWRNLVL. Bus-off Status 0CAN controller is not in the bus-off state. 1CAN controller is in the bus-off state. List Length Error 0 No list length error since last flag reset. 1 A list length error has been detected during message acceptance filtering. The number of elements in the list that belongs to this CAN node differs from the list SIZE given in the list termination pointer. LLE must be reset by software (write 0). Writing 1 has no effect. List Object Error 0 No list object error since last flag reset. 1 A list object error has been detected during message acceptance filtering. A message object with wrong LIST index entry in the Message Object Control Register has been detected. LOE must be reset by software (write 0). Writing 1 has no effect. 20-67 V1.0, 2007-06 EWRN 6 rh BOFF 7 rh LLE 8 rwh LOE 9 rwh User's Manual MultiCAN, V1.7d2 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field SUSACK Bits 10 Controller Area Network (MultiCAN) Controller Type Description rh Suspend Acknowledge 0 The CAN node is not in suspend mode or a suspend request is pending, but the CAN node has not yet reached BUS IDLE or BUS OFF. 1 The CAN node is in suspend mode: The CAN node is inactive (bit NCR.INIT internally forced to `1') due to an OCDS suspend request. Reserved; read as 0; should be written with 0. 0 [15:11] r User's Manual MultiCAN, V1.7d2 20-68 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Encoding of the LEC Bitfield Table 20-10 Encoding of the LEC Bit Field LEC Value 000B 001B Signification No Error: No error was detected for the last message on the CAN bus. Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. Form Error: A `fixed format part' of a received frame has the wrong format. Ack Error: The transmitted message was not acknowledged by another node. Bit1 Error: During a message transmission the CAN node tried to send a recessive level (1) outside the arbitration field and the acknowledge slot, but the monitored bus value was dominant. Bit0 Error: Two different conditions are signalled by this code: a) During transmission of a message (or acknowledge bit, active error flag, overload flag) the CAN node tried to send a dominant level (0), but the monitored bus value was recessive. b) During bus-off recovery this code is set each time a sequence of 11 recessive bits has been monitored. The CPU may use this code as indication that the bus is not continuously disturbed. CRC Error: The CRC checksum of the received message was incorrect. CPU write to LEC: Whenever the the CPU writes the value 111 to LEC, it takes the value 111. Whenever the CPU writes another value to LEC, the written LEC value is ignored. Controller Area Network (MultiCAN) Controller 010B 011B 100B 101B 110B 111B User's Manual MultiCAN, V1.7d2 20-69 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller The Node Interrupt Pointer Register connects each interrupt request source of the CAN node to one of the up to 16 available interrupt output lines. NIPRx (x = 0-4) Node x Interrupt Pointer Register (208H+x*100H) 15 14 13 12 11 10 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 CFCINP rw TRINP rw LECINP rw ALINP rw Field ALINP Bits [3:0] Type Description rw Alert Interrupt Node Pointer Number of interrupt output line INT_Om (m=0-15) reporting the "Alert Interrupt Request", if enabled by ALIE = 1. Last Error Code Interrupt Node Pointer Number of interrupt output line INT_Om (m=0-15) reporting the "Last Error Interrupt Request", if enabled by LECIE = 1. Transfer OK Interrupt Node Pointer Number of interrupt output line INT_Om (m=0-15) reporting the "Transfer Interrupt Request", if enabled by TRIE. Frame Counter Interrupt Node Pointer Number of interrupt output line INT_Om (m=0-15) reporting the "Frame Counter Overflow Interrupt Request", if enabled by CFCIE = 1. LECINP [7:4] rw TRINP [11:8] rw CFCINP [15:12] rw User's Manual MultiCAN, V1.7d2 20-70 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller The Node Port Control Register configures the CAN bus transmit/receive ports. NPCRx may be written only if bit NCRx.CCE is set. NPCRx (x = 0-4) Node x Port Control Register 15 14 13 12 0 r 11 10 9 (20CH+x*100H) 8 LBM rw 7 6 5 0 r 4 Reset Value: 0000H 3 2 1 RXSEL rw 0 Field RXSEL Bits [2:0] Type Description rw Receive Select RXSEL selects one out of 8 possible receive inputs. CAN traffic is performed through the selected input. The other inputs are ignored. See also "Receive Input Selection" Section Loop Back Mode 0 Loop back mode is disabled. 1 Loop back mode is enabled. This node is connected to an internal (virtual) loop back CAN bus. All CAN nodes which are in loop back mode are connected to this virtual CAN bus so that they can communicate with each other internally. The external transmit line is forced recessive in loop back mode. Reserved; read as 0; should be written with 0. LBM 8 rw 0 [7:3], [15:9] r User's Manual MultiCAN, V1.7d2 20-71 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller The Node Bit Timing Register contains all parameters to setup the bit timing for the CAN transfer. NBTRx may be written only if bit NCRx.CCE is set. NBTRxH (x = 0-4) Node x Bit Timing Register High (212H+x*100H) 15 14 13 12 11 10 9 8 0 r 7 6 5 4 Reset Value: 0000H 3 2 1 0 FTX rw Field FTX Bits 0 Type Description rw Fast Transmit (TTC only) When a message is requested for transmission on the CAN bus, then the start of frame (SOF) symbol is sent with the beginning of a new bit time. If the CAN bus is in the idle state and bit FTX is set (FTX = 1) then a new bit time is started immediately with the transmit trigger of a new message. This eliminates the variable delay between the transmit trigger of a message and the actual SOF signal on the transmit output. Such a variable delay occurs when transmit triggers occur at different positions within a CAN bit time. 0 [15:1] r reserved; returns '0' if read; should be written with '0'; User's Manual MultiCAN, V1.7d2 20-72 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller NBTRxL (x = 0-4) Node x Bit Timing Register Low (210H+x*100H) 15 DIV8 rw 14 13 TSEG2 rw 12 11 10 9 8 7 6 5 4 Reset Value: 0000H 3 BRP rw 2 1 0 TSEG1 rw SJW rw Field BRP Bits [5:0] Type Description rw Baud Rate Prescaler The duration of one time quantum is given by (BRP + 1) clock cycles if DIV8 = 0. The duration of one time quantum is given by 8 x (BRP + 1) clock cycles if DIV8 = 1. (Re)Synchronization Jump Width (SJW + 1) time quanta are allowed for resynchronization. Time Segment Before Sample Point (TSEG1 + 1) time quanta is the user defined nominal time between the end of the synchronization segment and the sample point. It includes the propagation segment, which takes into account signal propagation delays. The time segment may be lengthened due to resynchronization. Valid values for TSEG1 are 2 to 15. Time Segment After Sample Point (TSEG2 + 1) time quanta is the user defined nominal time between the sample point and the start of the next synchronization segment. It may be shortened due to resynchronization. Valid values for TSEG2 are 1 to 7. Divide Prescaler Clock by 8 0 A time quantum lasts (BRP+1) clock cycles. 1 A time quantum lasts 8 x (BRP+1) clock cycles. SJW [7:6] rw TSEG1 [11:8] rw TSEG2 [14:12] rw DIV8 15 rw User's Manual MultiCAN, V1.7d2 20-73 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller NECNTxH (x = 0-4) Node x Error Counter Register High(216H+x*100H) 15 14 13 0 r 12 11 10 9 8 7 6 5 4 Reset Value: 0060H 3 2 1 0 LEIN LET C D rh rh EWRNLVL rw Field EWRNLVL Bits [7:0] Type Description rw Error Warning Level Bit field EWRNLVL defines the threshold value (warning level, default 96) to be reached in order to set the corresponding error warning bit EWRN. Last Error Transfer Direction 0 The last error occurred while the CAN node was receiver (REC has been incremented). 1 The last error occurred while the CAN node was transmitter (TEC has been incremented). Last Error Increment 0The last error led to an error counter increment of 1. 1The last error led to an error counter increment of 8. Reserved; read as 0; should be written with 0. LETD 8 rh LEINC 9 rh 0 [15:10] r NECNTxL (x = 0-4) Node x Error Counter Register Low(214H+x*100H) 15 14 13 12 11 10 9 8 7 6 5 4 Reset Value: 0000H 3 REC rwh 2 1 0 TEC rwh Field REC Bits [7:0] Type Description rwh Receive Error Counter Bit field REC contains the value of the receive error counter of the CAN node. User's Manual MultiCAN, V1.7d2 20-74 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field TEC Bits [15:8] Controller Area Network (MultiCAN) Controller Type Description rwh Transmit Error Counter Bit field TEC contains the value of the transmit error counter of the CAN node. User's Manual MultiCAN, V1.7d2 20-75 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller The Node Frame Counter Register contains the actual value of the frame counter as well as control and status bits of the frame counter. NFCRxH (x = 0-4) Node x Frame Counter Register High(21AH+x*100H) 15 14 13 12 0 r 11 10 9 8 7 6 5 0 r 4 Reset Value: 0000H 3 2 1 CFSEL rw 0 CFC CFCI OV E rwh rw CFMOD rw Field CFSEL Bits [2:0] Type Description rw CAN Frame Count Selection This bit field selects the function of the frame counter for the chosen frame count mode. Frame Count Mode Bit 0 If Bit 0 of CFSEL is set then CFC is incremented each time a foreign frame (i.e. a frame not matching to a message object) has been received on the CAN bus. Bit 1 If Bit 1 of CFSEL is set then CFC is incremented each time a frame matching to a message object has been received on the CAN bus. Bit 2 If Bit 2 of CFSEL is set then CFC is incremented each time a frame has been transmitted successfully by the node. Time Stamp Mode The frame counter is incremented (internally) with the beginning of a new bit time. Its value is permanently sampled in the CFC field while the bus is idle. The value sampled just before the SOF bit of a new frame is detected is written to the corresponding message object. When the treatment of a message object is finished, the sampling continues. Bit Timing Mode The available bit timing measurement modes are shown in Table 20-11. If CFCIE is set then an interrupt on request node x (where x is the CAN node index) is generated with a CFC update. User's Manual MultiCAN, V1.7d2 20-76 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field CFMOD Bits [4:3] Controller Area Network (MultiCAN) Controller Type Description rw CAN Frame Counter Mode This bit field defines the operation mode of the frame counter. 00B Frame Count Mode: The frame counter is incremented upon the reception and transmission of frames. 01B Time Stamp Mode: The frame counter is used to count CAN bit times. 10B Bit Timing Mode: The frame counter is used for analysis of the bit timing.1) 11B reserved CAN Frame Count Interrupt Enable 0 CAN Frame Counter Overflow interrupt request is disabled. 1 CAN Frame Counter Overflow interrupt request is enabled. CAN Frame Counter Overflow Flag Flag CFCOV is set upon a frame counter overflow (transition from FFFFH to 0000H). In bit timing analysis mode CFCOV is set upon an update of CFC. An interrupt request is generated if CFCIE = 1. 0 No overflow has occurred since last flag reset. 1 An overflow has occurred since last flag reset. CFCOV must be cleared by software. reserved; returns '0' if read; should be written with '0'; CFCIE 6 rw CFCOV 7 rwh 0 1) 5, [15:8] r For all bit timing analysis modes, the count value of NFCRx.CFC always displays the measured value minus 1. Example: A CFC value of 34 in mode CFSEL = 000 indicates that 35 have been elapsed between the most recent 2 dominat edges on the receive input. NFCRxL (x = 0-4) Node x Frame Counter Register Low(218H+x*100H) 15 14 13 12 11 10 9 8 CFC rwh 7 6 5 4 Reset Value: 0000H 3 2 1 0 User's Manual MultiCAN, V1.7d2 20-77 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller Field CFC Bits [15:0] Type Description rwh CAN Frame Counter In Frame Count Mode this bit field contains the frame count value. In TimeStamp Mode this bit field contains the captured bit time count value, captured with the start of a new frame. Bit Timings Analysis Modes and States Table 20-11 Bit Timing Analysis Modes (CFMOD = 10) CFSEL Measurement 000 Whenever a dominant edge (transition from 1 to 0) is monitored on the receive input the time (measured in clock cycles) between this edge and the most recent dominant edge is stored in CFC. Whenever a recessive edge (transition from 0 to 1) is monitored on the receive input the time (measured in clock cycles) between this edge and the most recent dominant edge is stored in CFC. Whenever a dominant edge is received as a result of a transmitted dominant edge the time (clock cycles) between both edges is stored in CFC. Whenever a recessive edge is received as a result of a transmitted recessive edge the time (clock cycles) between both edges is stored in CFC. Whenever a dominant edge that qualifies for synchronization is monitored on the receive input the time (measured in clock cycles) between this edge and the most recent sample point is stored in CFC. With each sample point, the time (measured in clock cycles) between the start of the new bit time and the start of the previous bit time is stored in CFC[11:0]. Additional information is written to CFC[15:12] at each sample point: CFC[15] : Transmit value of actual bit time CFC[14] : Receive sample value of actual bit time CFC[13:12] : CAN bus information (see Table 20-12) reserved reserved 001 010 011 100 101 110 111 User's Manual MultiCAN, V1.7d2 20-78 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller Table 20-12 CAN Bus State Information CFC[13:12] CAN bus state 00 NoBit The CAN bus is idle, performs bit (de-) stuffing or is in one of the following frame segments: SOF, SRR, CRC, delimiters, first 6 EOF bits, IFS NewBit This code represents the first bit of a new frame segment. The current bit is the first bit in one of the following frame segments: bit 10 (MSB) of standard ID (transmit only), RTR, reserved bits, IDE, DLC(MSB), bit 7 (MSB) in each data byte and the first bit of the ID extension Bit This code represents a bit inside a frame segment with a length of more than one bit (not the first bit of those frame segments which is indicated by NewBit). The current bit is processed within one of the following frame segments: ID bits (except first bit of standard ID for transmission and first bit of ID extension), DLC (3 LSB) and bits 6-0 in each data byte Done The current bit is in one of the following frame segments: Acknowledge slot, last bit of EOF, active/passive error frame, overload frame. Two or more directly consecutive Done codes signal an error frame. 01 10 11 20.2.12 Message Object Registers The Message Object Control Register contains control bits for the CAN transfer and the message object link pointer. Each control bit has a corresponding bit in the CTRL field. A control bit is set by writing 1 to the corresponding bit in CTRL. It is cleared by writing 1 to the control bit directly. Any other combination leaves the control bit unchanged . After reset initialization the pointer PNEXT (read value of MOCTRnH[15:8]) points to message object n+1 (PNEXT = n+1), except for PNEXT of message object 127, which terminates the initial list (PNEXT = 127). Pointer PREV (read value of MOCTRnH[7:0]) initially points to message object n-1 (PPREV = n-1), except for PPREV of message object 0 which indicates the start of the initial list (PPREV = 0). This reset initialization means that all message objects initially belong to the list of unallocated elements. User's Manual MultiCAN, V1.7d2 20-79 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller MOCTRnH (n = 0-127) Message Object n Control Register High (101EH+n*20H) Value:shiftl8(n+1)+(n-1)1) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Reset 0 0 SET SET SET SET SET SET SET SET SET SET SET SET TXE TXE TXR RXE RTS MSG MSG NEW RXU TXP RXP DIR N1 N0 Q N EL VAL LST DAT PD ND ND w w w w w w w w w w w w w 1) Exceptions: Message Obj. 0 : Reset val. of PPREV = 0, Message Obj. 127 : Reset val. of PNEXT = 127 Field SETRXPND SETTXPND SETRXUPD Bits 0 1 2 Type Description w w w w w w w w w w w w Set Receive Pending This bit sets the RXPND Set Transmit Pending This bit sets the TXPND Set Receive Updating This bit sets the RXUPD Set New Data This bit sets the NEWDAT Set Message Lost This bit sets the MSGLST Set Message Valid This bit sets the MSGVAL Set Receive/Transmit Selected This bit sets the RTSEL Set Receive Enable This bit sets the RXEN Set Transmit Request This bit sets the TXRQ Set Transmit Enable 0 This bit sets the TXEN0 Set Transmit Enable 1 This bit sets the TXEN1 Set Message Direction This bit sets the DIR 20-80 V1.0, 2007-06 SETNEWDAT 3 SETMSGLST SETMSGVAL SETRTSEL SETRXEN SETTXRQ SETTXEN0 SETTXEN1 SETDIR 4 5 6 7 8 9 10 11 User's Manual MultiCAN, V1.7d2 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field 0 Bits Controller Area Network (MultiCAN) Controller Type Description Reserved Should be written with 0. [15:12] w MOCTRnL (n = 0-127) Message Object n Control Register Low(101CH+n*20H) 15 14 13 12 11 10 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 0 RES RES RES RES RES RES RES RES RES RES RES RES TXE TXE TXR RXE RTS MSG MSG NEW RXU TXP RXP DIR N1 N0 Q N EL VAL LST DAT PD ND ND w w w w w w w w w w w w w Field RESRXPND RESTXPND RESRXUPD Bits 0 1 2 Type Description w w w w w w w w w w w Reset Receive Pending This bit resets the RXPND Reset Transmit Pending This bit resets the TXPND Reset Receive Updating This bit resets the RXUPD Reset New Data This bit resets the NEWDAT Reset Message Lost This bit resets the MSGLST Reset Message Valid This bit resets the MSGVAL Reset Receive/Transmit Selected This bit resets the RTSEL Reset Receive Enable This bit resets the RXEN Reset Transmit Request This bit resets the TXRQ Reset Transmit Enable 0 This bit resets the TXEN0 Reset Transmit Enable 1 This bit resets the TXEN1 20-81 V1.0, 2007-06 RESNEWDAT 3 RESMSGLST 4 RESMSGVAL 5 RESRTSEL RESRXEN RESTXRQ RESTXEN0 RESTXEN1 6 7 8 9 10 User's Manual MultiCAN, V1.7d2 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field RESDIR 0 Bits 11 Controller Area Network (MultiCAN) Controller Type Description w Reset Message Direction This bit resets the DIR Reserved Should be written with 0. [15:12] w MOSTATnH (n = 0-127) Message Object n Status Register High (101EH+n*20H) Value:shiftl8(n+1)+(n-1)1) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Reset 0 PNEXT rh 1) PPREV rh Exceptions: Message Obj. 0 : Reset val. of PPREV = 0, Message Obj. 127 : Reset val. of PNEXT = 127 Field PNEXT Bits [15:8] Type Description rh Pointer to Previous Message Object PPREV holds the message object number of the previous message object in a message list structure. Pointer to Next Message Object PNEXT holds the message object number of the next message object in a message list structure. PPREV [7:0] rh MOSTATnL (n = 0-127) Message Object n Status Register Low(101CH+n*20H) 15 14 13 12 11 DIR rh 10 9 8 7 RX EN rh 6 5 4 Reset Value: 0000H 3 2 1 0 LIST rh TX TX TX EN1 EN0 RQ rh rh rh RT MSG MSG NEW RX TX RX SEL VAL LST DAT UPD PND PND rh rh rh rh rh rh rh User's Manual MultiCAN, V1.7d2 20-82 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller Field RXPND Bits 0 Type Description rh Receive Pending 0B No CAN message has been received. 1B A CAN message has been received by the message object n, either directly or via gateway copy action. RXPND is not reset by hardware but must be reset by software. Transmit Pending No CAN message has been transmitted. 0B 1B A CAN message from message object n has been transmitted successfully over the CAN bus. TXPND is reset by hardware but must be reset by software. Receive Updating 0B No receive update ongoing. 1B Message identifier, DLC, and data of the message object are currently updated. New Data 0B No update of the message object n since last flag reset. 1B Message object n has been updated. NEWDAT is set by hardware after a received CAN frame has been stored in message object n. NEWDAT is cleared by hardware when a CAN transmission of message object n has been started. NEWDAT should be set by software after the new transmit data has been stored in message object n to prevent the automatic reset of TXRQ at the end of an ongoing transmission. Message Lost No CAN message is lost. 0B 1B A CAN message is lost because NEWDAT has become set again when it has already been set. TXPND 1 rh RXUPD 2 rh NEWDAT 3 rh MSGLST 4 rh User's Manual MultiCAN, V1.7d2 20-83 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field MSGVAL Bits 5 Controller Area Network (MultiCAN) Controller Type Description rh Message Valid 0B Message object n is not valid. 1B Message object n is valid. Only a valid message object takes part in CAN transfers. Receive/Transmit Selected Message object n is not selected for receive or 0B transmit operation. 1B Message object n is selected for receive or transmit operation. Frame Reception: RTSEL is set by hardware when message object n has been identified for storage of a CAN frame that is currently received. Before a received frame becomes finally stored in message object n, a check is performed to determine if RTSEL is set. Thus the CPU can suppress a scheduled frame delivery to this message object n by clearing RTSEL by software. Frame Transmission: RTSEL is set by hardware when message object n has been identified to be transmitted next. A check is performed to determine if RTSEL is still set before message object n is actually set up for transmission and bit NEWDAT is cleared. It is also checked that RTSEL is still set before its message object n is verified due to the successful transmission of a frame. RTSEL needs to be checked only when the context of message object n changes, and a conflict with an ongoing frame transfer shall be avoided. In all other cases, RTSEL can be ignored. RTSEL has no impact on message acceptance filtering. RTSEL is not cleared by hardware. Receive Enable Message object n is not enabled for frame 0B reception. 1B Message object n is enabled for frame reception. RXEN is evaluated for receive acceptance filtering only. RTSEL 6 rh RXEN 7 rh User's Manual MultiCAN, V1.7d2 20-84 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field TXRQ Bits 8 Controller Area Network (MultiCAN) Controller Type Description rh Transmit Request 0B No transmission of message object n is requested. 1B Transmission of message object n on the CAN bus is requested. The transmit request becomes valid only if TXRQ, TXEN0, TXEN1 and MSGVAL are set. TXRQ is set by hardware if a matching Remote Frame has been received correctly. TXRQ is reset by hardware if message object n has been transmitted successfully and NEWDAT is not set again by software. Transmit Enable 0 0B Message object n is not enabled for frame transmission. 1B Message object n is enabled for frame transmission. Message object n can be transmitted only if both bits, TXEN0 and TXEN1, are set. The user may clear TXEN0 in order to inhibit the transmission of a message that is currently updated, or to disable automatic response of Remote Frames. Transmit Enable 1 0B Message object n is not enabled for frame transmission. 1B Message object n is enabled for frame transmission. Message object n can be transmitted only if both bits, TXEN0 and TXEN1, are set. TXEN1 is used by the MultiCAN module for selecting the active message object in the Transmit FIFOs. TXEN0 9 rh TXEN1 10 rh User's Manual MultiCAN, V1.7d2 20-85 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field DIR Bits 11 Controller Area Network (MultiCAN) Controller Type Description rh Message Direction 0B Receive Object selected: With TXRQ = 1, a Remote Frame with the identifier of message object n is scheduled for transmission. On reception of a Data Frame with matching identifier, the message is stored in message object n. 1B Transmit Object selected: If TXRQ = 1, message object n is scheduled for transmission of a Data Frame. On reception of a Remote Frame with matching identifier, bit TXRQ is set. List Allocation LIST indicates the number of the message list to which message object n is allocated. LIST is updated by hardware when the list allocation of the object is modified by a panel command. LIST [15:12] rh User's Manual MultiCAN, V1.7d2 20-86 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller The Message Object Interrupt Pointer Registers MOIPR H/L hold various pointers related to message interrupts as well as the frame counter value. MOIPRnH (n = 0-127) Message Object n Interrupt Pointer Register High (100AH+n*20H) 15 14 13 12 11 10 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 CFCVAL rwh Field CFCVAL Bits [15:0] Type Description rwh CAN Frame Counter Value When a message is stored in this message object or this message object has been successfully transmitted then the CAN frame counter value CFC of the CAN Node Frame Counter Register (NFCR) is copied to CFCVAL. MOIPRnL (n = 0-127) Message Object n Interrupt Pointer Register Low (1008H+n*20H) 15 14 13 12 11 10 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 MPN rw TXINP rw RXINP rw Field RXINP Bits [3:0] Type Description rw Receive Interrupt Node Pointer Select the interrupt output line INT_Om (m=0-15) for receive interrupts. Transmit Interrupt Node Pointer Select the interrupt output line INT_Om (m=0-15) for transmit interrupts. TXINP [7:4] rw User's Manual MultiCAN, V1.7d2 20-87 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field MPN Bits [15:8] Controller Area Network (MultiCAN) Controller Type Description rw Message Pending Number This field selects the bit position of the bit in the message pending register to be set upon a receive/transmit interrupt. User's Manual MultiCAN, V1.7d2 20-88 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller The Message Object Function Control Registers High / Low contain bits to select and to configure the function of the message object. It also holds the CAN data length code. MOFCRnH (n = 0-127) Message Object n Function Control Register High (1002H+n*20H) 15 14 13 12 11 10 DLC rwh 9 8 7 6 5 4 FRR EN rw Reset Value: 0000H 3 0 r 2 1 0 0MSC rwh STT SDT RMM rw rw rw OVIE TXIE RXIE rw rw rw Field RXIE Bits 0 Type Description rw Receive Interrupt Enable If RXIE is set then a message interrupt request is generated with the reception of a CAN message, no matter whether the CAN message is received directly or indirectly via a gateway action. The interrupt is requested on interrupt output line as defined by RXINP. Transmit Interrupt Enable If TXIE is set then a message interrupt request is generated when this message object successfully transmitted a message over the CAN bus. The interrupt is requested on interrupt output line as defined by TXINP. Overflow Interrupt Enable IF OVIE = 1 then a FIFO full interrupt is generated when the pointer to the current object CUR reaches the value of SEL in the FIFO/Gateway Pointer Register. If this object is a receive FIFO base object then the FIFO full interrupt is requested on interrupt ouput line as defined by TXINP. If this object is a transmit FIFO base object then the FIFO full interrupt is requested on interrupt output line as defined by RXINP. For all other message object modes OVIE has no effect. TXIE 1 rw OVIE 2 rw User's Manual MultiCAN, V1.7d2 20-89 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field FRREN Bits 4 Controller Area Network (MultiCAN) Controller Type Description rw Foreign Remote Request Enable Specifies if the TXRQ bit is set in this message object or in a foreign object referenced by the pointer CUR. 0 TXRQ of this message object is set upon the reception of a matching remote frame. 1TXRQ of the message object referenced by the pointer CUR is set upon the reception of a matching remote frame. Transmit Object Remote Monitoring 0 Remote monitoring disabled: The identifier, IDE bit and DLC of the message object remain unchanged upon the reception of a matching remote frame. 1 Remote monitoring enabled: The identifier, DLC and IDE bit of a matching remote frame are copied to this transmit object in order to monitor incoming remote frames. Bit RMM only applies to transmit objects and has no impact on receive objects. Single Data Transfer If SDT = 1 and this object is not a FIFO base object then MSGVAL is reset when this object has taken part in a successful data transfer (receive or transmit). If SDT = 1 and this object is a FIFO base object then MSGVAL is reset when the pointer to the current object CUR reaches the value of SEL in the FIFO/Gateway Pointer Register. With SDT = 0, bit MSGVAL is not affected. Single Transmit Trial If this bit is set then TXRQ is cleared upon transmission start of this message object. Thus no transmission retry is performed in case of transmission failure. Data Length Code Valid values for the data length are 0 to 8. DLC>8 leads to 8 data bytes, but the DLC code is not truncated upon reception or transmission of CAN frames. RMM 5 rw SDT 6 rw STT 7 rw DLC [11:8] rwh User's Manual MultiCAN, V1.7d2 20-90 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field 0 0 Bits Controller Area Network (MultiCAN) Controller Type Description Reserved; read as 0; should be written with 0. Reserved; read as 0; should be written with 0. [15:12] r 3 r MOFCRnL (n = 0-127) Message Object n Function Control Register Low (1000H+n*20H) 15 14 0 r 13 12 11 10 9 8 7 6 0 r 5 4 Reset Value: 0000H 3 2 1 0 DAT DLC GDF IDC C C S rw rw rw rw MMC rw Field MMC Bits [3:0] Type Description rw Message Mode Control Bit field MMC controls the functionality of the message object. 0000 Standard Message Object 0001 Receive FIFO Base Object 0010 Transmit FIFO Base Object 0011 Transmit FIFO Slave Object 0100 Gateway Source Object else Reserved Gateway Data Frame Send 1 TXRQ is set in the gateway destination object after the transfer of a data frame from the gateway source to the gateway destination. 0 TXRQ is not set in the destination object. Applicable only to Gateway Source Object. Identifier Copy IF IDC = 1 then the identifier of the gateway source object (after storing the received frame in the source) is copied to the gateway destination. Applicable only to Gateway Source Object. GDFS 8 rw IDC 9 rw User's Manual MultiCAN, V1.7d2 20-91 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field DLCC Bits 10 Controller Area Network (MultiCAN) Controller Type Description rw Data Length Code Copy If DLCC = 1 then the data length code of the gateway source object (after storing the received frame in the source) is copied to the gateway destination. Applicable only to Gateway Source Object. Data Copy If DATC = 1 then the data field (registers MODATA0 and MODATA4) of the gateway source object (after storing the received frame in the source) is copied to the gateway destination. Applicable only to Gateway Source Object. reserved; returns '0' if read; should be written with '0'; DATC 11 rw 0 [7:4], r [15:12] User's Manual MultiCAN, V1.7d2 20-92 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller The Message Object FIFO/Gateway Pointer Registers H/L contain a set of message object link pointer used for FIFO and gateway functionality MOFGPRnH (n = 0-127) Message Object n FIFO/Gateway Pointer Register High (1006H+n*20H) 15 14 13 12 11 10 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 SEL rw CUR rwh Field CUR Bits [7:0] Type Description rwh Current Object Pointer The Current Object Pointer links to the actual target object within a FIFO/Gateway structure. After a FIFO/gateway operation CUR is updated with the message number of the next message object in the list structure (given by PNEXT of the message control register) until it reaches the FIFO top element (given by TOP) when it is reset to the bottom element (given by BOT). Object Select Pointer The Object Select Pointer is the second (software) pointer to complement the hardware pointer CUR in the FIFO structure. SEL is used for monitoring purposes only. SEL [15:8] rw MOFGPRnL (n = 0-127) Message Object n FIFO/Gateway Pointer Register Low (1004H+n*20H) 15 14 13 12 11 10 9 8 7 6 5 4 Reset Value: 0000H 3 BOT rw 2 1 0 TOP rw User's Manual MultiCAN, V1.7d2 20-93 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller Field BOT Bits [7:0] Type Description rw Bottom Pointer The Bottom Pointer points to the first element in a FIFO structure. Top Pointer The TOP pointer points to the last element in a FIFO structure. TOP [15:8] rw Note: The pointers in this register must be set to objects assigned to the same CAN node. It is forbidden to refer to objects that are not in the linked list for the same CAN node. User's Manual MultiCAN, V1.7d2 20-94 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller Registers MOAMR H/L contain the mask bits for the acceptance filtering of the mesage object. MOAMRnH (n = 0-127) Message Object n Acceptance Mask Register High (100EH+n*20H) 15 0 r 14 13 MID E rw 12 11 10 9 8 7 6 AM[28:16] rw 5 4 Reset Value: 3FFFH 3 2 1 0 Field AM[28:16] MIDE Bits [12:0] 13 Type Description rw rw Acceptance Mask for Message Identifier High see description of MOAMRnL.AM[15:0] Acceptance Mask bit for Message IDE bit 0 This message objects accepts the reception of both standard and extended frames. 1 This message object only receives frames with matching IDE bit. Reserved; read as 0; should be written with 0. 0 [15:14] r MOAMRnL (n = 0-127) Message Object n Acceptance Mask Register Low (100CH+n*20H) 15 14 13 12 11 10 9 8 7 6 5 4 Reset Value: FFFFH 3 2 1 0 AM[15:0] rw User's Manual MultiCAN, V1.7d2 20-95 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller Field AM[15:0] Bits [15:0] Type Description rw Acceptance Mask for Message Identifier Mask to filter incoming messages with standard identifiers (AM[28:18]) or extended identifiers (AM[28:0]). For standard identifiers bits AM[17:0] are "don't care". User's Manual MultiCAN, V1.7d2 20-96 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller Registers MOAR H/L contain the CAN identifier of the message object. MOARnH (n = 0-127) Message Object n Arbitration Register High (101AH+n*20H) 15 14 13 IDE rwh 12 11 10 9 8 7 6 ID[28:16] rwh 5 4 Reset Value: 0000H 3 2 1 0 PRI rw Field ID[28:16] Bits [12:0] Type Description rwh CAN Identifier of Message Object Identifier of a standard message (ID[28:18]) or an extended message (ID[28:0]). For standard identifiers bits ID[17:0] are "don't care". CAN IDE bit of Message Object 0 Standard frame with 11-bit identifier 1Extended frame with 29-bit identifier IDE 13 rwh User's Manual MultiCAN, V1.7d2 20-97 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field PRI Bits Controller Area Network (MultiCAN) Controller Type Description Priority Class PRI assigns one of the four priority classes 0, 1, 2, 3 to the message object, with lower PRI number meaning higher priority. Message objects with lower PRI value always win acceptance filtering for frame reception and transmission over message objects with higher PRI value. Acceptance filtering based on identifier/mask and list position is only performed between message objects of the same priority class. PRI also defines the acceptance filtering method for transmission: 00 Reserved. Transmit objects with PRI = 00 are not taken into account for the transmit acceptance filtering. 01 Transmit acceptance filtering is based on the list order, i.e. this message object is considered for transmission only if there is no other message object with valid transmit request (MSGVAL & TXRQ & TXEN0 & TXEN1 = 1) somewhere before this object in the list. 10Transmit acceptance filtering is based on the CAN identifier, i.e. this message object is considered for transmission only if there is no other message object with higher priority identifier+IDE+DIR (with respect to CAN arbitration rules) somewhere in the list (see Table 20-13). 11Transmit acceptance filtering is based on the list order (like PRI = 01). [15:14] rw MOARnL (n = 0-127) Message Object n Arbitration Register Low (1018H+n*20H) 15 14 13 12 11 10 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 ID[15:0] rwh User's Manual MultiCAN, V1.7d2 20-98 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller Field ID[15:0] Bits [15:0] Type Description rwh CAN Identifier of Message Object Low Identifier of a standard message (ID[28:18]) or an extended message (ID[28:0]). For standard identifiers bits ID[17:0] are "don't care". Transmit Priority Table 20-13 Transmit Priority based on CAN Arbitration Rules Settings of arbitrarily chosen message Comment objects A and B, where A has higher transmit priority than B A.MOAR[28:18] < B.MOAR[28:18] Messages with lower standard identifier (11 bit standard identifier of A less than 11 have higher priority than messages with bit standard identifier of B) higher standard identifier. MOAR[28] is the most significant bit (MSB) of the standard identifier. MOAR[18] is the least significant bit of the standard identifier. A.MOAR[28:18] = B.MOAR[28:18] A.MOAR.IDE = 0 (send standard frame) B.MOAR.IDE = 1 (send extended frame) A.MOAR[28:18] = B.MOAR[28:18] A.MOAR.IDE = B.MOAR.IDE = 0 A.MOCTR.DIR = 1 (send data frame) B.MOCTR.DIR = 0 (send remote frame) A.MOAR[28:0] = B.MOAR[28:0] A.MOAR.IDE = B.MOAR.IDE = 1 A.MOCTR.DIR = 1 (send data frame) B.MOCTR.DIR = 0 (send remote frame) A.MOAR[28:0] < B.MOAR[28:0] A.MOAR.IDE = B.MOAR.IDE = 1 (29 bit identifier) Standard frames have higher transmit priority than extended frames with equal standard identifier. Standard data frames have higher transmit priority than standard remote frames with equal identifier. Extended data frames have higher transmit priority than extended remote frames with equal identifier. Extended frames with lower identifier have higher transmit priority than extended frames with higher identifier. MOAR[28] is the most significant bit (MSB) of the overall identifier (standard identifier MOAR[28:18] and identifier extension MOAR[17:0]). MOAR[0] is the least significant bit (LSB) of the overall identifier. User's Manual MultiCAN, V1.7d2 20-99 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller MODATAnLH (n = 0-127) Message Object n Data Register Low High (1012H+n*20H) 15 14 13 12 11 10 9 8 7 6 5 4 Reset Value: 0000H 3 DB2 rwh 2 1 0 DB3 rwh Field DB2 DB3 Bits [7:0] [15:8] Type Description rwh rwh CAN Data Byte 2 CAN Data Byte 3 MODATAnLL (n = 0-127) Message Object n Data Register Low Low (1010H+n*20H) 15 14 13 12 11 10 9 8 7 6 5 4 Reset Value: 0000H 3 DB0 rwh 2 1 0 DB1 rwh Field DB0 DB1 Bits [7:0] [15:8] Type Description rwh rwh CAN Data Byte 0 CAN Data Byte 1 User's Manual MultiCAN, V1.7d2 20-100 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller Registers MODATAH H/L contain the highest four CAN data bytes. Unused data bytes are padded zero upon reception and ignored for transmission . MODATAnHH (n = 0-127) Message Object n Data Register High High (1016H+n*20H) 15 14 13 12 11 10 9 8 7 6 5 4 DB6 rwh Reset Value: 0000H 3 2 1 0 DB7 rwh Field DB6 DB7 Bits [7:0] [15:8] Type Description rwh rwh CAN Data Byte 6 CAN Data Byte 7 MODATAnHL (n = 0-127) Message Object n Data Register High Low (1014H+n*20H) 15 14 13 12 11 10 9 8 7 6 5 4 Reset Value: 0000H 3 DB4 rwh 2 1 0 DB5 rwh Field DB4 DB5 Bits [7:0] [15:8] Type Description rwh rwh CAN Data Byte 4 CAN Data Byte 5 User's Manual MultiCAN, V1.7d2 20-101 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller 20.3 General Control and Status The following section describes the general clock, debug and interrupt topics. 20.3.1 Clock Control The CAN clock frequency fCAN of the functional blocks of the MultiCAN module is derived from the system clock fSYS (= clock on the system bus). The fractional divider FDIV in the module is used to generate the CAN clock frequency for the bit timing calculation. This frequency is identical for all CAN nodes. The scheduler itself is in the fSYS domain. The clock generation can be enabled/disabled by the fractional divider control bit field FDR.DM. fSYS FDIV fCAN baud rate prescalers register file MultiCAN_clocks-- Figure 20-17 MultiCAN Clock Generation The fractional divider FDIV output fCAN is based on the system clock fSYS, but only every n-th clock pulse is taken. The register file is in the system frequency domain. The suspend signal (coming as acknowledge from the module as answer to the OCDS suspend request) freezes or resets the fractional divider. Note: The receive input line contains a synchronization stage to ensure stable input data. Together with the internal CAN state machine, this leads to a minimum reaction time of at least 3 clock cycles of fSYS between CAN input and output. The switching delay of the input stages can be generally neglected, whereas the rise/fall times of the port output drivers (programmable values) should be taken into account, especially for higher baud rates. The table below indicates the minimum frequencies of fSYS in MHz for MultiCAN module operation (acceptance filtering, MO handling, etc.), that are required for a baud rate of 1 Mbit/s for the active CAN nodes (the highest CAN baud rate of the activated CAN nodes has to be taken into account). If less baud rate is desired, the values can be scaled linearly (e.g. for a maximum of 500 kbit/s, 50% of the indicated value are required). User's Manual MultiCAN, V1.7d2 20-102 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller The values imply that the CPU (or PEC) executes a maximum of accesses to the MultiCAN module. The values may contain rounding effects. Table 20-14 Minimum Operating Frequencies [MHz] Number of allocated message 1 CAN objects MO1) node active 16 MO 32 MO 64 MO 128 MO 1) 2 CAN nodes active 19 23 28 45 3 CAN nodes active 26 30 37 50 4 CAN nodes active 33 37 46 55 5 CAN nodes active 40 44 53 61 12 15 21 40 Only those message objects have to be taken into account that are allocated to a CAN node. The unallocated message objects have no influence on the minimum operating frequency. The baud rate generation of the MultiCAN being based on fSYS, this frequency has to be chosen carefully to allow correct CAN bit timing. The required value of fSYS is given by an integer multiple (n) of the CAN baud rate multiplied by the number of time quanta per CAN bit time. For example, to reach 1 Mbit/s with 20 tq per bit time, possible values of fSYS are given by formula [n x 20] MHz, with n being an integer value, starting at 1. In order to minimize jitter, it is not recommended to use the fractional divider mode for high baud rates. 20.3.2 Port Input Control There is the possibility to select the input lines for the RXDCANx inputs for the CAN nodes. The selected input is connected to the CAN node and is also available to wake up the system. User's Manual MultiCAN, V1.7d2 20-103 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller 20.3.3 Suspend Mode The suspend mode can be triggered by the OCDS in order to freeze the state of the module and to have access to the registers (at least for read actions). There are several aspects related to the suspend mode: * All actions are immediately stopped ("hard suspend"): The module clock is switched off as soon as the suspend line becomes active. This mode is supported by the fast switch off feature of the BPI. Write actions to the module are not supported and only combinatorial read actions deliver the desired data (the CAN RAM and the CAN registers can not be accessed). In this mode, all further module actions are disabled and there is a very high probability that the communication with other devices is made impossible and that the CAN bus is blocked by the device in hard suspend mode (e.g. if the suspended CAN just sends a dominant level). A normal continuation when the suspend mode is left is not always possible and reset must be activated. The current action is finished ("soft suspend"): The module functions are stopped (clock is still running!) automatically after internal actions have been finished, for example after a CAN frame has been sent out. Due to this behavior, the communication network is not blocked due to the suspend mode of one communication partner. Furthermore, all registers are accessible for read and write actions. As a result, the debugger can stop the module actions and modify registers. These modifications are taken into account after the suspend mode is left. This mode is designed to be able to modify registers or to read them by the OCDS while the rest of the systems is still running and not corrupted by the suspend mode. * In the MultiCAN module a suspend mechanism is implemented allowing the individual freeze of CAN nodes. The fast switch off feature (hard suspend) of the BPI must not be activated by the user in order to support the soft suspend mode. In order to allow the required flexibility for the system, each CAN node can be individually enabled for the soft suspend mode. The hard suspend feature can be enabled/disabled for the complete MultiCAN module, whereas the soft suspend feature can be enabled/disabled independently for each CAN node. The fractional divider disables the CAN clock only if all CAN nodes signal that they can be suspended. A CAN node that is not active can always be suspended. User's Manual MultiCAN, V1.7d2 20-104 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller 20.3.4 Interrupt Structure The general interrupt structure is shown in the figure below. The interrupt event can trigger the interrupt generation. The interrupt pulse is generated independently from the interrupt flag in the interrupt status register. The interrupt flag can be reset by SW by writing a 0 to it. If enabled by the related interrupt enable bit in the interrupt enable register, an interrupt pulse can be generated at one of the 16 interrupt output lines INT_Ox of the module. If more than one interrupt source is connected to the same interrupt node pointer (in the interrupt node pointer register), the requests are combined to one common line. int_reset_SW int_flag INP to INT_O0 O R to INT_O1 ... to INT_O15 int_event int_enable A N D other interrupt sources on the same INP MultiCAN_int_struct Figure 20-18 General Interrupt Structure User's Manual MultiCAN, V1.7d2 20-105 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller 20.4 MultiCAN Module Implementation This section describes CAN module interfaces with the clock control, port connections, interrupt control, and address decoding. 20.4.1 Interfaces of the CAN Module Figure 20-19 shows the XC2000 specific implementation details and interconnections of the CAN module. The I/O lines of the CAN module kernel (two I/O lines of each CAN node) are connected to the ports as described in Table 20-18. The CAN module is further supplied by clock control, interrupt control, and address decoding logic. MultiCAN Module Kernel Clock Control fC AN Message Object Buffer 128 Objects CAN Node 4 TX DC4 RX DC4 Address Decoder Linked List Control . . . CAN Node 1 CAN Node 0 . . . TX DC1 RX DC1 TX DC0 RX DC0 . . . Port Control Interrupt Control CAN Control mc_multican_block5.vsd Figure 20-19 CAN Module Implementation and Interconnections The MultiCAN interrupt control register x is connected to the CAN interrupt output line INT_Ox, with x = 15 - 0. Additionally, the signal INT_O15 can be used to start timers. User's Manual MultiCAN, V1.7d2 20-106 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller 20.4.2 Module Clock Generation As shown in Figure 20-20, the clock signals for the MultiCAN module are generated and controlled by a clock generation unit. This clock generation unit is responsible for the enable/disable control, the clock frequency adjustment, and the debug clock control. The frequency control of the module timer clock fCAN is performed via the CAN_FDR register. MultiCAN Clock Generation f SYS Fractional Divider Register CAN_FDR f CAN f SYS CANClockGen_P11 Figure 20-20 MultiCAN Module Clock Generation The module control clock fSYS is used inside the MultiCAN module kernel for control purposes such as e.g. for clocking of control logic and register operations. The frequency of fSYS is identical to the system clock frequency fSYS. The module timer clock fCAN is used inside the MultiCAN module kernels as input clock for all timing relevant operations. The frequency of fCAN is defined by: 1 n n fCAN = fSYS x or with n = 1024 - CAN_FDR.STEP with n = 0-1023 1024 Note: The upper formula applies to normal divider mode of the fractional divider (CAN_FDR.DM = 01B). The lower formula applies to fractional divider mode (CAN_FDR.DM = 10B). Note: Input signal ECEN of the MultiCAN fractional divider is wired to 0. fCAN = fSYS x 20.4.2.1 Fractional Divider Overview The fractional divider allows to generate output clocks from an input clock using a programmable divider. The fractional divider divides an input clock fIN either by the factor 1/n or by a fraction of n/1024 for any value of n from 0 to 1023 and outputs the clock User's Manual MultiCAN, V1.7d2 20-107 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller signals, fOUT. The clock generation can be enabled/disabled by the fractional divider register control bit field FDR.DM. STEP (10-bit) 1 Mux Adder Mux RESULT (10-bit) Control fOUT fIN Debug Suspend Request Debug Suspend Acknowledge External Clock Enable Module Disable Request SPND SPNDACK ECEN MODDISREQ KERNELDISREQ FDIVBlockDiag RST_EXT_DIV Figure 20-21 Fractional Divider Block Diagram The clock generation in the fractional divider is further controlled by four input signals. User's Manual MultiCAN, V1.7d2 20-108 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller Table 20-15 Fractional Divider I/O Lines Signal SPND I/O Input Description Suspend Request Input is controlled by the debug system suspend request signal. It becomes active when a general suspend request is issued from the debug system to the on-chip modules. Suspend Acknowledge Input is driven with the disable acknowledge signal from the module kernel. This signal is activated by the module kernel as a response to a suspend request that has been issued by the fractional divider via KERNELDISREQ = 0. Module Disable Request Input is connected to the disable request output from the CLC logic. An active signal at this input results in the activation of output signal KERNELDISREQ. External Clock Enable Signal ECEN can be used to synchronize the fractional divider clock generation to external events. Output Kernel Disable Request This output signal becomes active when either MODDISREQ is activated or when SPND becomes active. Reset External Divider This output signal allows to control (stop/reset) external divider stages for fOUT. Module Clock Enable Signal fOUT is the enable signal for the module clock. The module clock itself is built by and-ing the fOUT enable signal with fIN. Module clock frequency references mostly refer to the AND combination of fOUT with fIN. SPNDACK MODDISREQ ECEN KERNELDISREQ RST_EXT_DIV fOUT The fractional divider has two operating modes: * * Normal divider mode Fractional divider mode User's Manual MultiCAN, V1.7d2 20-109 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Normal Divider Mode In normal divider mode (FDR.DM = 01B) the fractional divider behaves like a reload counter (addition of +1) that generates an output clock pulse at fOUT on the transition from 3FFH to 000H. FDR.RESULT represents the counter value and FDR.STEP defines the reload value. The output frequencies in normal divider mode are defined according the following formulas: Controller Area Network (MultiCAN) Controller fOUT = fIN x 1 n with n = 1024 - STEP In order to get fOUT = fIN STEP must be programmed with 3FFH. Figure 20-22 shows the operation of the normal divider mode with a reload value of FDR.STEP = 3FDH. The clock frequency of fOUT is represented by and-ing the fOUT enable signal with fIN. STEP 3FD Reload 3FD Reload 3FE 3FF 3FD 3FE 3FF 3FD Reload 3FD 3FE RESULT 3FF 3FD fIN fOUT Enable FDIVNormalMode Figure 20-22 Normal Mode Timing User's Manual MultiCAN, V1.7d2 20-110 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Fractional Divider Mode When the fractional divider mode is selected (FDR.DM = 10B), the output clock fOUT is derived from the input clock fIN by division of a fraction of n/1024 for any value of n from 0 to 1023. In general, the fractional divider mode allows to program the average output clock frequency with a higher accuracy than in normal divider mode. In fractional divider mode an output clock pulse at fOUT is generated dependent on the result of the addition FDR.RESULT + FDR.STEP. If the addition leads to an overflow over 3FFH a pulse is generated at fOUT. Note that in fractional divider mode the clock fOUT can have a maximum period jitter of one fIN clock period. The output frequencies in fractional divider mode are defined according the following formulas: Controller Area Network (MultiCAN) Controller fOUT = fIN x n 1024 with n = 0-1023 Figure 20-23 shows the operation of the fractional divider mode with a reload value of FDR.STEP = 234H (= factor 564/1024 = 0.55). The clock frequency of fOUT is represented by and-ing the fOUT enable signal with fIN. STEP = 234H : fOUT = 0.55 x fIN fIN RESULT 150 384 1B8 3EC 220 054 288 0BC 2F0 124 358 18C 3C0 +234 +234 fOUT Enable +234 +234 +234 +234 +234 +234 +234 +234 +234 +234 +234 FDIVFraDivMode Figure 20-23 Fractional Divider Mode Timing Suspend Mode Control The fractional divider allows to control its operation according to the input Suspend Request (SPND). This input is activated in suspend mode by the on-chip debug control logic. In suspend mode, the module registers are accessible for read and write actions, but the other module internal functions are frozen. Suspend mode is requested by SPND = 1. Suspend mode is entered one fIN clock cycle after the suspend mode request has been acknowledged by setting SPNDACK to 0 (granted suspend mode) and User's Manual MultiCAN, V1.7d2 20-111 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller FDR.SC is not equal 00B (clock output signal disabled). Suspend mode is immediately entered when bit SM is set to 1 and FDR.SC is not equal 00B (immediate suspend mode The state of signals SPND and SPNDACK is latched in two status flags of register FDR, SUSREQ and SUSACK. SPND and (SPNDACK or bit SM) must remain set both to maintain the suspend mode. SPNDACK SPND Register FDR SUS SUS REQ ACK SC SM Fractional Divider >1 & SC not equal 00B switch fOUT off & >1 MODDISREQ KERNELDISREQ FDIVSuspend Figure 20-24 Suspend Mode Configuration The Kernel Disable Request signal KERNELDISREQ becomes always active when MODDISREQ is activated, independently of the suspend mode settings in the fractional divider logic. External Clock Enable When the module clock generation has been disabled by software (setting FDR.DISCLK = 1), the disable state can be left via input ECEN = 1 (hardware controlled). This feature is enabled when FDR.ENHW = 1. In the MultiCAN module, signal ECEN is tied to 0. Registers Overview Fractional Divider Registers The fractional divider contains two registers, FDRL (lower 16 bits) and FDRH (higher 16 bits). User's Manual MultiCAN, V1.7d2 20-112 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary FDRL Fractional Divider Register L 15 DM rw 14 13 SC rw 12 11 SM rw 10 0 r 9 Controller Area Network (MultiCAN) Controller (0CH) 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 STEP rw Field STEP Bits [9:0] Type Description rw Step Value In normal divider mode STEP contains the reload value for RESULT. In fractional divider mode this bit field defines the 10bit value that is added to the RESULT with each input clock cycle. Suspend Mode SM selects between granted or immediate suspend mode. 0 Granted suspend mode selected 1 Immediate suspend mode selected Suspend Control This bit field defines the behavior of the fractional divider in suspend mode (bit SUSREQ and SUSACK set). 00 Clock generation continues. 01 Clock generation is stopped and the clock output signals are not generated. RESULT is not changed except when writing bit field DM with 01B or 10B. 10 Clock generation is stopped and the clock output signals are not generated. RESULT is loaded with 3FFH. 11 Same as SC = 10B but RST_EXT_DIV is 1 (independently of bit field DM). SM 11 rw SC [13:12] rw User's Manual MultiCAN, V1.7d2 20-113 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field DM Bits [15:14] Controller Area Network (MultiCAN) Controller Type Description rw Divider Mode This bit fields defines the functionality of the fractional divider block. 00 Fractional divider is switched off; no output clock is generated. RST_EXT_DIV is 1. RESULT is not updated (default after reset). 01 Normal divider mode selected. 10 Fractional divider mode selected. 11 Fractional divider is switched off; no output clock is generated. RESULT is not updated. Reserved read as 0; should be written with 0. 0 others r FDRH Fractional Divider Register H 15 14 13 12 11 0 r 10 9 (0EH) 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 DIS EN SUS SUS CLK HW REQ ACK rwh rw rh rh RESULT rh Field RESULT Bits [9:0] Type Description rh Result Value In normal divider mode RESULT acts as reload counter (addition +1). In fractional divider mode this bit field contains the result of the addition RESULT+STEP. If DM is written with 01B or 10B, RESULT is loaded with 3FFH. Suspend Mode Acknowledge 0 Suspend mode is not acknowledged. 1 Suspend mode is acknowledged. Suspend mode is entered when SUSACK and SUSREQ are set. SUSACK 12 rh User's Manual MultiCAN, V1.7d2 20-114 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field SUSREQ Bits 13 Controller Area Network (MultiCAN) Controller Type Description rh Suspend Mode Request 0 Suspend mode is not requested. 1 Suspend mode is requested. Suspend mode is entered when SUSREQ and SUSACK are set. Enable Hardware Clock Control 0 Bit DISCLK cannot be reset by HW by a high level at input signal ECEN. 1 Bit DISCLK is reset by hardware while input signal ECEN is at high level. Disable Clock 0 Clock generation of fOUT is enabled according to the setting of bit field DM. 1 Fractional divider is stopped. The enable signal fOUT becomes inactive. No change except when writing bit field DM. Reserved read as 0; should be written with 0. ENHW 14 rw DISCLK 15 rwh 0 others r Fractional Divider Operation Modes Table 20-16 Fractional Divider Function Table Mode SC DM RES_EXT RESULT _DIV 1 0 unchanged fOUT Operation of Fractional Divider switched off normal divider mode fractional divider mode Normal Mode - 00 01 10 11 inactive continuously active updated1) unchanged inactive switched off User's Manual MultiCAN, V1.7d2 20-115 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller Table 20-16 Fractional Divider Function Table Mode SC DM RES_EXT RESULT _DIV 1 0 unchanged fOUT Operation of Fractional Divider switched off normal divider mode fractional divider mode Suspend Mode 00 00 01 10 11 inactive continuously active updated1) unchanged 1 0 unchanged unchanged1) unchanged 1 0 loaded with 3FFH inactive inactive switched off switched off halted switched off 01 00 01 10 11 10 00 01 10 11 inactive switched off halted switched off 11 1) - 1 loaded with 3FFH inactive switched off Each write operation to FDR with DM = 01B or 10B sets RESULT to 3FFH. 20.4.3 * Mode Control Behavior The MultiCAN module provides two mechanisms to stop participation in CAN traffic: Suspend Mode: The suspend mode request is issued by the OCDS block. The sensitivity of a CAN node to a suspend request can be individually enabled/disabled for each CAN node. In suspend mode, a CAN node correctly finishes a running CAN frame, but does not start a new one. Immediate Stop Mode: The immediate stop mode is entered when a stop mode is requested by the mode control of the device, configured by MCAN_KSCCFG. If an immediate stop is requested, the CAN module immediately stops all CAN activity (even within a running frame) and sets all transmit outputs to 1. In oder to allow CAN operation, bit field NOMCFG has to be set to a run mode. To support suspend mode (see description above), bit field SUMCFG has to be set to run mode to avoid immediate stop mode. * User's Manual MultiCAN, V1.7d2 20-116 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller 20.4.4 Mode Control The mode control concept for system control tasks, such as power saving, or suspend request for debugging, allows to program the module behavior under different device operating conditions. The behavior of the MultiCAN kernel can be programmed for each of the device operating modes, that are requested by the global state control part of the SCU. MultiCAN has an associated register CAN_KSCFG defining the behavior of the kernel of the module in the following device operating modes: * Normal operation: This operating mode is the default operating mode when neither a suspend request nor a clock-off request are pending. The module clock is not switched off and the MultiCAN registers can be read or written. The kernel behavior is defined by KSCFG.NOMCFG. Suspend mode: This operating mode is requested when a suspend request (issued by a debugger) is pending in the device. The module clock is not switched off and the MultiCAN registers can be read or written. The kernel behavior is defined by KSCFG.SUMCFG. Clock-off mode: This operating mode is requested for power saving purposes. The module clock is switched off automatically when all kernels of the MultiCAN module reached their specified state in a stop mode. In this case, MultiCAN registers can not be accessed. The kernel behavior is defined by KSCFG.COMCFG. * * For the MultiCAN module, the following internal actions can be influenced by mode control: * A current transmision of a CAN message: If there is a pending request, it can be started. This start has to be enabled by the mode control. If the current kernel mode allows the start (run modes 0 and 1), it will be executed. If the kernel mode does not allow a start (stop modes 0 and 1), the request is not started. The start request is not cancelled, but frozen. A "frozen" request is started as programmed if the kernel mode is changed to a run mode again. The behavior of the MultiCAN kernel can be programmed for each of the device operating modes (normal operation, suspend mode, clock-off mode). Therefore, the MultiCAN kernel supports four kernel modes, as shown in Table 20-17. User's Manual MultiCAN, V1.7d2 20-117 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller Table 20-17 MultiCAN Kernel Behavior Kernel Mode run mode 0 run mode 1 stop mode 0 Kernel Behavior kernel operation as specified, no impact on data transfer (same behavior for run mode 0 and run mode 1) A currently running transfer is completely finished and the result is treated. Pending requests are not taken into account (but not deleted). They restart after entering a run mode as programmed. The arbiter continues as programmed. Code 00B 01B 10B stop mode 1 Like stop mode 0, but the arbiter is stopped after it has finished 11B its arbitration round. Generally, bit field KSCFG.NOMCFG should be configured for run mode 0 as default setting for standard operation. If the MultiCAN kernel should not react to a suspend request (and to continue operation as in normal mode), bit field KSCFG.SUMCFG has to be configured with the same value as KSCFG.NOMCFG. If the MultiCAN kernel should show a different behavior and stop operation when a specific stop condition is reached, the code for stop mode 0 or stop mode 1 has to be written to KSCFG.SUMCFG. A similar mechanism applies for the clock-off mode with the possibility to program the desired behavior by bit field KSCFG.COMCFG. Note: The stop mode selection strongly depends on the application needs and it is very unlikely that different stop modes are required in parallel in the same application. As a result, only one stop mode type (either 0 or 1) should be used in the bit fields in register KSCFG. Do not mix stop mode 0 and stop mode 1 and avoid transitions from stop mode 0 to stop mode 1 (or vice versa) for the MultiCAN module. Please note that bit KSCFG.MODEN should only be set by SW while all configuration fields are configured for run mode 0. User's Manual MultiCAN, V1.7d2 20-118 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller 20.4.5 Mode Control Register Description 20.4.5.1 Kernel State Configuration Register The kernel state configuration register KSCFG allows the selection of the desired kernel modes for the different device operating modes. Bit fields KSCFG.NOMCFG and KSCFG.COMCFG are reset by a class 3 reset. Bit field KSCFG.SUMCFG is reset by a class 1 reset. Note: The coding of the bit fields NOMCFG, SUMCFG and COMCFG is described in Table 20-17. CAN_KSCFG Kernel State Configuration Register SFR(FE1EH) 15 BP COM w 14 13 12 11 10 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 0 BP COMCFG SUM rw w 0 BP SUMCFG NOM rw w 0 NOMCFG 0 BP MOD MOD EN EN w rw r r r rw r Field MODEN Bits 0 Type Description rw Module Enable This bit enables the module kernel clock and the module functionality. 0B The module is switched off immediately (without respecting a stop condition). It does not react on mode control actions and the module clock is switched off. The module does not react on read accesses and ignores write accesses (except to KSCFG). The module is switched on and can operate. 1B After writing 1 to MODEN, it is recommended to read register KSCFG to avoid pipeline effects in the control block before accessing other ADC registers. Note: This bit is reset by a class 3 reset. User's Manual MultiCAN, V1.7d2 20-119 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field BPMODEN Bits 1 Controller Area Network (MultiCAN) Controller Type Description w Bit Protection for MODEN This bit enables the write access to the bit MODEN. It always reads 0. 0B MODEN is not changed. 1B MODEN is updated with the written value. Note: This bit is reset by a class 3 reset. NOMCFG [5:4] rw Normal Operation Mode Configuration This bit field defines the kernel mode applied in normal operation mode. 0XB The module is switched on. 1XB The module is switched off. This field is taken into account for CR = 00 or 11. Note: This bit is reset by a class 3 reset. BPNOM 7 w Bit Protection for NOMCFG This bit enables the write access to the bit field NOMCFG. It always reads 0. 0B NOMCFG is not changed. 1B NOMCFG is updated with the written value. Note: This bit is reset by a class 3 reset. SUMCFG [9:8] rw Suspend Mode Configuration This bit field defines the kernel mode applied in suspend mode. 0XB The module is switched on. This is the recommended setting in order to have soft suspend behavior. 1XB The module is switched off. This field is taken into account for CR = 01. Note: This bit is reset by a class 1 reset. BPSUM 11 w Bit Protection for SUMCFG This bit enables the write access to the bit field SUMCFG. It always reads 0. 0B SUMCFG is not changed. 1B SUMCFG is updated with the written value. Note: This bit is reset by a class 1 reset. User's Manual MultiCAN, V1.7d2 20-120 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Field COMCFG Bits [13:12] Controller Area Network (MultiCAN) Controller Type Description rw Clock Off Mode Configuration This bit field defines the kernel mode applied in clock off mode. 0XB The module is switched on. 1XB The module is switched off. This field is taken into account for CR = 10. Note: This bit is reset by a class 3 reset. BPCOM 15 w Bit Protection for COMCFG This bit enables the write access to the bit field COMCFG. It always reads 0. 0B COMCFG is not changed. 1B COMCFG is updated with the written value. Note: This bit is reset by a class 3 reset. 0 [3:2], 6, 10, 14 r Reserved returns 0 if read; should be written with 0; Note: The bit protection bits BPxxx allow partly modification of the configuration bits with a single write operation (without the need of a read-modify-write mechanism handled by the CPU). User's Manual MultiCAN, V1.7d2 20-121 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller 20.4.6 Connection of External Signals The following table shows the digital connections of the MultiCAN signals with other modules or pins in the XC2000 device. The selected input signal (selected by bit field RXSEL) for each CAN node is made available by signal CANxINS (CAN node x input signal, with x = 4 - 0). These signals can be used in the SCU for wake-up purposes and to allow two CAN nodes receive the same signal (analysis and safety feature). Table 20-18 MultiCAN Connections in XC2000 Signal from/to Module P2.3 P0.3 P2.0 P2.6 ESR1 1 0 P0.1 P0.2 P2.1 P2.4 P2.5 MultiCAN Node 1 Signals RXDC1A RXDC1B RXDC1C RXDC1D RXDC1E RXDC1 [G:F] RXDC1H P2.4 P0.4 P2.7 CAN0INS ESR2 1 0 I receive input A (NPCR1.RXSEL = 000B) receive input B (NPCR1.RXSEL = 001B) receive input C (NPCR1.RXSEL = 010B) receive input D (NPCR1.RXSEL = 011B) receive input E (NPCR1.RXSEL = 100B) receive inputs [G:F] (NPCR1.RXSEL = 101B to 110B) receive input H (NPCR1.RXSEL = 111B) O I/O to CAN I Can be used to/as MultiCAN Node 0 Signals RXDC0A RXDC0B RXDC0C RXDC0D RXDC0E RXDC0 [G:F] RXDC0H TXDC0 receive input A (NPCR0.RXSEL = 000B) receive input B (NPCR0.RXSEL = 001B) receive input C (NPCR0.RXSEL = 010B) receive input D (NPCR0.RXSEL = 011B) receive input E (NPCR0.RXSEL = 100B) receive inputs [G:F] (NPCR0.RXSEL = 101B to 110B) receive input H (NPCR0.RXSEL = 111B) transmit output User's Manual MultiCAN, V1.7d2 20-122 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller Table 20-18 MultiCAN Connections in XC2000 (cont'd) Signal TXDC1 from/to Module P0.6 P2.2 P2.9 MultiCAN Node 2 Signals RXDC2A RXDC2B RXDC2C RXDC2D RXDC2 [G:E] RXDC2H TXDC2 P4.3 P10.11 CAN1INS ESR0 1 0 P4.1 P4.2 P10.12 MultiCAN Node 3 Signals RXDC3A RXDC3B RXDC3C RXDC3D RXDC3 [G:E] RXDC3H TXDC3 P3.3 P3.0 P10.14 CAN2INS 1 0 P3.1 P3.2 P10.13 MultiCAN Node 4 Signals O I receive input A (NPCR3.RXSEL = 000B) receive input B (NPCR3.RXSEL = 001B) receive input C (NPCR3.RXSEL = 010B) receive input D (NPCR3.RXSEL = 011B) receive inputs [G:E] (NPCR3.RXSEL = 100B to 110B) receive input H (NPCR3.RXSEL = 111B) transmit output O I receive input A (NPCR2.RXSEL = 000B) receive input B (NPCR2.RXSEL = 001B) receive input C (NPCR2.RXSEL = 010B) receive input D (NPCR2.RXSEL = 011B) receive inputs [G:E] (NPCR2.RXSEL = 100B to 110B) receive input H (NPCR2.RXSEL = 111B) transmit output I/O to CAN O Can be used to/as transmit output User's Manual MultiCAN, V1.7d2 20-123 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller Table 20-18 MultiCAN Connections in XC2000 (cont'd) Signal RXDC4A RXDC4B RXDC4C RXDC4D RXDC4 [G:E] RXDC4H TXDC4 from/to Module P3.4 P7.0 P10.7 CAN3INS 1 0 P3.6 P7.1 P7.2 P10.6 General MultiCAN Signals INT_O[15:0] interrupt controller INT_O15 to CCU62 and CCU63 O interrupt output lines (service requests) notification for timer start O I/O to CAN I Can be used to/as receive input A (NPCR4.RXSEL = 000B) receive input B (NPCR4.RXSEL = 001B) receive input C (NPCR4.RXSEL = 010B) receive input D (NPCR4.RXSEL = 011B) receive inputs [G:E] (NPCR4.RXSEL = 100B to 110B) receive input H (NPCR4.RXSEL = 111B) transmit output User's Manual MultiCAN, V1.7d2 20-124 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller 20.4.7 MultiCAN Module Register Address Map In the XC2000, the registers of the MultiCAN module are located in the following address range: Table 20-19 Registers Address Space Module CAN Base Address 20 0000H End Address 20 3FFFH Note Note: he complete and detailed address map of the MultiCAN modules is described in the chapter "Register Overview" of the XC2000 System Units User's Manual. In the MultiCAN module address range, the following register blocks are located at the offset start addresses, see Figure 20-25: - 0000H - 0100H - 0200H - 1000H - 3E00H General registers for clock control, fractional divider, ID Global Module Control registers CAN node 0 registers Message object memory (32 bytes for each object) Scheduler memory (128 * 4 bytes) The CAN RAM is automatically initialized after reset by the list controller in order to ensure correct list pointers in each message object. The end of this CAN RAM initialization is indicated by bit PANCTR.BUSY becoming inactive. Before the end of the initialization sequence, the CAN module must not be accessed with other instructions than polling for bit PANCTR.BUSY. The CAN RAM can be optionally enabled for parity detection. The feature is controlled in the SCU. User's Manual MultiCAN, V1.7d2 20-125 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Controller Area Network (MultiCAN) Controller MO = Message Object; n = 0-127 MOBASE = 1000H + n * 20 H MO n Control Register H/L MO n Arbitration Reg. H/L +3FFC H MOBASE + +1EH / 1C H + 1AH / 18 H + 16H / 14 H + 12H / 10 H + 0EH / 0C H + 0AH / 08 H + 06H / 04 H + 02H / 00 H +1FE0H Message Object 127 .Message Object 126. . . . . . . . . . . . . . . Message Object 1 Message Object 0 CAN Registers Node 4 MO n Data Register HH/HL MO n Data Register LH/LL MO n Accept. Mask Reg. H/L MO n Interrupt Ptr. Reg. H/L MO n FIFO/Gtw. Ptr. Reg. H/L MO n Function Control Reg. H/L +1040H +1020H +1000H +600H NO = Node; x = 0-4 NOBASE = 200H + x * 100 H NO BASE + + 1AH / 18 H + 16H / 14 H + 12H / 10 H + 0CH + 08H + 04H + 00H Node 0 Frame Counter Reg. H/L Node 0 Error Counter Reg. H/L +500H CAN Registers Node 3 Node 0 Bit Timing Reg. H/L Node 0 Port Control Reg. Node 0 Interrupt Ptr. Reg. +400H CAN Registers Node 2 Node 0 Status Registers Node 0 Control Reg. +300H CAN Registers Node 1 + CC H + C8H + C6H / C4 H + C2H / C0 H + 80H + 42H / 40H + 02H / 00 H +200H CAN Registers Node 0 Module Interrupt Trg. Reg Module Control Register Panel Control Register H/L Msg. Index Mask Reg. H/L Msg. Index Registers k Global Module Control +100H General Module Control 000H Msg. Pending Reg. k H/L List Registers l H/L Fractional Divider Register H/L Module Identification Register + 0EH / 0C H + 08H Mu ltiC AN _ P1 1 MR _ re g ma p --.vsd Figure 20-25 MultiCAN Module Register Map User's Manual MultiCAN, V1.7d2 20-126 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Keyword Index Keyword Index This section lists a number of keywords which refer to specific details of the XC2000 in terms of its architecture, its functional units or functions. This helps to quickly find the answer to specific questions about the XC2000. This User's Manual consists of two Volumes, "System Units" and "Peripheral Units". For your convenience this keyword index refers to both volumes, so you can immediately find the reference to the desired section in the corresponding document ([1] or [2]). Note: Registers are listed in a separate index: Register Index. A Acronyms 1-9 [1] Addressing Modes CoREG Addressing Mode 4-50 [1] DSP Addressing Modes 4-46 [1] Indirect Addressing Modes 4-44 [1] Long Addressing Modes 4-41 [1] Short Addressing Modes 4-39 [1] ALU 4-57 [1] B Baudrate Bootstrap Loader 10-9 [1] Bit Handling 4-60 [1] Manipulation Instructions 12-2 [1] protected 4-61 [1] reserved 2-17 [1] Block Diagram ITC / PEC 5-3 [1] Bootstrap Loader 10-4 [1] C CAN Block diagram 20-2 [2] Clock control 20-102 [2] Features 20-2 [2] Functional description 20-4 [2] Interrupt structure 20-105 [2] Module implementation 20-106 [2] MultiCAN Analysis mode 20-19 [2] User's Manual L-1 Bit timing 20-10 [2] Block diagram 20-7 [2] Error handling 20-12 [2] Gateway mode 20-42 [2] Interrupts 20-13 [2] Message acceptance filtering 20-22 [2] Message object FIFO 20-37 [2] Message object lists 20-14 [2] Node control 20-10 [2] Overview 20-4 [2] Registers LISTiH 20-58 [2] LISTiL 20-59 [2] MCR 20-56 [2] MITR 20-57 [2] MOAMRnH 20-95 [2] MOAMRnL 20-95 [2] MOARnH 20-97 [2] MOARnL 20-98 [2] MOCTRnH 20-80 [2], 20-82 [2] MOCTRnL 20-81 [2], 20-82 [2] MODATAnHH 20-101 [2] MODATAnHL 20-101 [2] MODATAnLH 20-100 [2] MODATAnLL 20-100 [2] MOFCRnH 20-89 [2] MOFCRnL 20-91 [2] MOFGPRnH 20-93 [2] MOFGPRnL 20-93 [2] MOIPRnH 20-87 [2] V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary MOIPRnL 20-87 [2] MSIDk 20-61 [2] MSIMASKH 20-62 [2] MSIMASKL 20-62 [2] MSPNDkH 20-60 [2] MSPNDkL 20-60 [2] NBTRxH 20-72 [2] NBTRxL 20-73 [2] NCRx 20-63 [2] NECNTxH 20-74 [2] NECNTxL 20-74 [2] NFCRxH 20-76 [2] NFCRxL 20-77 [2] NIPRx 20-70 [2] NPCRx 20-71 [2] NSRx 20-66 [2] PANCTRH 20-51 [2] PANCTRL 20-51 [2] CAPCOM12 Capture Mode 17-14 [2] Counter Mode 17-9 [2] CAPCOM2 2-17 [1] Capture Mode GPT1 14-26 [2] GPT2 (CAPREL) 14-48 [2] Capture/Compare Registers 17-11 [2] CCU6 2-19 [1] Clock generation 2-32 [1] Clock System 6-2 [1] Clock Control Unit 6-13 [1] Clock Generation Unit 6-2 [1] Clock Output 6-15 [1] Crystal oscillator 6-3 [1] Crystal Oscillator run detection 6-11 [1] Emergency Clock Operation 6-14 [1] PLL 6-5 [1] Switching parameters 6-12 [1] Concatenation of Timers 14-22 [2], 14-47 [2] Context Pointer Updating 4-34 [1] Switch 4-33 [1] User's Manual Keyword Index Switching 5-33 [1] Count direction 14-6 [2], 14-36 [2] Counter 14-20 [2], 14-45 [2] Counter Mode (GPT1) 14-10 [2], 14-40 [2] CPU 2-2 [1], 4-1 [1] D Data Management Unit (Introduction) 2-9 [1] Data Page 4-42 [1] Development Support 1-8 [1] Direction count 14-6 [2], 14-36 [2] Disable Interrupt 5-30 [1] Division 4-62 [1] Double-Register Compare 17-24 [2] DPP 4-42 [1] E EBC Bus Signals 9-3 [1] Memory Table 9-33 [1] Enable Interrupt 5-30 [1] End of PEC Interrupt Sub Node 5-29 [1] ESRx 5-1 [1] External Bus 2-14 [1] Interrupts 5-36 [1] External Request Unit (ERU) 6-64 [1] ERS 6-72 [1] ETL 6-74 [1] Internal Connections 6-76 [1] OGU 6-77 [1] Operation 6-64 [1] Pin Connetions 6-66 [1] External Service Request (ESR) 6-52 [1] ESR Pad Control 6-57 [1] ESR Reset 6-55 [1] ESR Trap 6-56 [1] ESR Wake-up 6-56 [1] Operation 6-52 [1] V1.0, 2007-06 L-2 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Keyword Index F Flags 4-56 [1]-4-59 [1] Fractional divider Block diagram 20-108 [2] Operating modes 20-110 [2] Suspend mode 20-111 [2] L Latency Interrupt, PEC 5-39 [1] LXBus 2-14 [1] M Memory 2-10 [1] Multiplication 4-62 [1] G Gated timer mode (GPT1) 14-9 [2] Gated timer mode (GPT2) 14-39 [2] Global State Controller (GSC) 6-156 [1] Commands 6-157 [1] Operation 6-156 [1] Priorities 6-156 [1] GPT 2-20 [1] GPT1 14-2 [2] GPT2 14-32 [2] O OCDS Requests 5-38 [1] P PEC 2-10 [1], 5-19 [1] Latency 5-39 [1] Transfer Count 5-20 [1] Peripheral Event Controller --> PEC 5-19 [1] Summary 2-15 [1] Pins 8-1 [1] Pipeline 4-11 [1] Port 2-30 [1] Ports Configuring a Pin 7-15 [1] I/O Description Entry 7-6 [1] Output register Pn_OUT 7-10 [1] Pad driver control 7-7 [1] Structure Analog 7-4 [1] Hardware Override 7-3 [1] Standard 7-2 [1] Power Control 6-90 [1] Changing Core Voltage 6-126 [1] Control of Core Voltage 6-115 [1] EVR 6-115 [1] Monitoring Core Voltage 6-97 [1] PSC 6-128 [1] PVC 6-97 [1] Supply Watchdog (SWD) 6-91 [1] Program Management Unit (Introduction) 2-9 [1] H Hardware Traps 5-41 [1] I Incremental Interface Mode (GPT1) 14-11 [2] Instruction 12-1 [1] Bit Manipulation 12-2 [1] Pipeline 4-11 [1] protected 12-6 [1] Interface External Bus 9-1 [1] Interrupt Arbitration 5-4 [1] Enable/Disable 5-30 [1] External 5-36 [1] Jump Table Cache 5-17 [1] Latency 5-39 [1] Node Sharing 5-35 [1] Priority 5-7 [1] Processing 5-1 [1] RTC 15-13 [2] System 2-8 [1], 5-2 [1] User's Manual L-3 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Protected Bits 4-61 [1] instruction 12-6 [1] Stack 4-52 [1] Keyword Index T Temperature Compensation Unit 6-165 [1] Timer 14-2 [2], 14-32 [2] Auxiliary Timer 14-15 [2], 14-41 [2] Concatenation 14-22 [2], 14-47 [2] Core Timer 14-4 [2], 14-34 [2] Counter Mode (GPT1) 14-10 [2], 14-40 [2] Gated Mode (GPT1) 14-9 [2] Gated Mode (GPT2) 14-39 [2] Incremental Interface Mode (GPT1) 14-11 [2] Mode (GPT1) 14-8 [2] Mode (GPT2) 14-38 [2] Tools 1-8 [1] Traps 5-41 [1] R Real Time Clock (->RTC) 2-22 [1], 15-1 [2] Reserved bits 2-17 [1] Reset 6-33 [1] Modules behavior 6-40 [1] Reset Operation 6-33 [1] Reset Types 6-33 [1] CPU Reset 6-38 [1] ESR Reset 6-37 [1] Memory Parity Reset 6-38 [1] OCDS Controlled Reset 6-38 [1] Power-on Reset 6-37 [1] Software Reset 6-38 [1] Supply Watchdog Reset 6-37 [1] Voltage Monitoring Reset 6-37 [1] Watchdog Timer Reset 6-38 [1] RTC 2-22 [1], 15-1 [2] Registers T14 15-8 [2] T14REL 15-8 [2] W Wake-up Timer 6-176 [1] Watchdog 2-29 [1] Watchdog Timer 6-168 [1] Operation 6-168 [1] Disable Mode 6-171 [1] Normal Mode 6-170 [1] Prewarning Mode 6-171 [1] Suspend Mode 6-172 [1] S SCU Identification 6-218 [1] Interrupt 6-186 [1] Buffering 6-210 [1] Operation 6-187 [1] Register Access 6-181 [1] Register Overview 6-220 [1] Trap 6-186 [1] Buffering 6-210 [1] Operation 6-200 [1] Segmentation 4-37 [1] Sharing Interrupt Nodes 5-35 [1] Software Traps 5-41 [1] SR0 5-46 [1] SR1 5-46 [1] User's Manual L-4 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary Register Index Register Index This section lists the registers of the XC2000. This helps to quickly find the reference to the description of the respective register. This User's Manual consists of two Volumes, "System Units" and "Peripheral Units". For your convenience this register index refers to both volumes, so you can immediately find the reference to the desired section in the corresponding document ([1] or [2]). Note: Keywords are listed in a separate index: Keyword Index. A ADC0_KSCFG 16-24 [2] ADCx_ALR0 16-77 [2] ADCx_ASENR 16-37 [2] ADCx_CHCTRx 16-68 [2] ADCx_CHINCR 16-73 [2] ADCx_CHINFR 16-72 [2] ADCx_CHINPRx 16-74 [2] ADCx_CRCRx 16-43 [2] ADCx_CRMRx 16-45 [2] ADCx_CRPRx 16-44 [2] ADCx_EMCTR 16-102 [2] ADCx_EMENR 16-103 [2] ADCx_EVINCR 16-93 [2] ADCx_EVINFR 16-92 [2] ADCx_EVINPRx 16-94 [2] ADCx_GLOBCTR 16-26 [2] ADCx_GLOBSTR 16-28 [2] ADCx_INPRx 16-70 [2] ADCx_LCBRx 16-71 [2] ADCx_PISEL 16-31 [2] ADCx_Q0Rx 16-57 [2] ADCx_QBURx 16-59 [2] ADCx_QINRx 16-61 [2] ADCx_QMRx 16-52 [2] ADCx_QSRx 16-55 [2] ADCx_RCRx 16-90 [2] ADCx_RESRAVx 16-87 [2] ADCx_RESRAx 16-87 [2] ADCx_RESRVx 16-86 [2] ADCx_RESRx 16-86 [2] ADCx_RSPRx 16-38 [2] User's Manual ADCx_RSSR 16-88 [2] ADCx_SYNCTR 16-104 [2] ADCx_VFR 16-89 [2] ADDRSELx 9-22 [1] B BANKSELx 5-34 [1] C CAN_LISTiH 20-58 [2] CAN_LISTiL 20-59 [2] CAN_MCR 20-56 [2] CAN_MITR 20-57 [2] CAN_MOAMRnH 20-95 [2] CAN_MOAMRnL 20-95 [2] CAN_MOARnH 20-97 [2] CAN_MOARnL 20-98 [2] CAN_MOCTRnH 20-80 [2] CAN_MOCTRnL 20-81 [2] CAN_MODATAnHH 20-101 [2] CAN_MODATAnHL 20-101 [2] CAN_MODATAnLH 20-100 [2] CAN_MODATAnLL 20-100 [2] CAN_MOFCRnH 20-89 [2] CAN_MOFCRnL 20-91 [2] CAN_MOFGPRnH 20-93 [2] CAN_MOFGPRnL 20-93 [2] CAN_MOIPRnH 20-87 [2] CAN_MOIPRnL 20-87 [2] CAN_MOSTATnH 20-82 [2] CAN_MOSTATnL 20-82 [2] CAN_MSIDk 20-61 [2] L-5 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary CAN_MSIMASKH 20-62 [2] CAN_MSIMASKL 20-62 [2] CAN_MSPNDkH 20-60 [2] CAN_MSPNDkL 20-60 [2] CAN_NBTRxH 20-72 [2] CAN_NBTRxL 20-73 [2] CAN_NCRx 20-63 [2] CAN_NECNTxH 20-74 [2] CAN_NECNTxL 20-74 [2] CAN_NFCRxH 20-76 [2] CAN_NFCRxL 20-77 [2] CAN_NIPRx 20-70 [2] CAN_NPCRx 20-71 [2] CAN_NSRx 20-66 [2] CAN_PANCTRH 20-51 [2] CAN_PANCTRL 20-51 [2] CAPREL 14-56 [2] CC2_CCyIC 17-36 [2] CC2_DRM 17-25 [2] CC2_IOC 17-31 [2] CC2_KSCCFG 17-39 [2] CC2_M4/5/6/7 17-11 [2] CC2_OUT 17-27 [2] CC2_SEE 17-29 [2] CC2_SEM 17-29 [2] CC2_T78CON 17-5 [2] CC2_T7IC 17-10 [2] CC2_T8IC 17-10 [2] CCU6x_CC63R 18-65 [2] CCU6x_CC63SR 18-65 [2] CCU6x_CC6xR 18-34 [2] CCU6x_CC6xSR 18-35 [2] CCU6x_CMPMODIF 18-40 [2] CCU6x_CMPSTAT 18-38 [2] CCU6x_IEN 18-98 [2] CCU6x_INP 18-101 [2] CCU6x_IS 18-91 [2] CCU6x_ISR 18-96 [2] CCU6x_ISS 18-94 [2] CCU6x_KSCFG 18-111 [2] CCU6x_KSCSR 18-113 [2] CCU6x_MCFG 18-114 [2] CCU6x_MCMCTR 18-84 [2] User's Manual Register Index CCU6x_MCMOUT 18-87 [2] CCU6x_MCMOUTS 18-86 [2] CCU6x_MODCTR 18-78 [2] CCU6x_PISELH 18-109 [2] CCU6x_PISELL 18-107 [2] CCU6x_PSLR 18-83 [2] CCU6x_T12 18-33 [2] CCU6x_T12DTC 18-36 [2] CCU6x_T12MSEL 18-41 [2] CCU6x_T12PR 18-33 [2] CCU6x_T13 18-63 [2] CCU6x_T13PR 18-64 [2] CCU6x_TCTR0 18-42 [2] CCU6x_TCTR2 18-45 [2] CCU6x_TCTR4 18-48 [2] CCU6x_TRPCTR 18-80 [2] CP 4-36 [1] CPUCON1 4-26 [1] CPUCON2 4-27 [1] CRIC 14-57 [2] CSP 4-38 [1] D DPP0/1/2/3 4-42 [1] DSTPx 5-24 [1] E EBCMOD0 9-13 [1] EBCMOD1 9-15 [1] EOPIC 5-28 [1] F FCONCS0 9-19 [1] FCONCS1/2/3/4/7 9-20 [1] FINT0/1ADDR 5-17 [1] FINT0/1CSP 5-17 [1] FL_KSCCFG 3-64 [1] FSR_BUSY 3-57 [1] FSR_OP 3-57 [1] FSR_PROT 3-59 [1] G GPT12E_CAPREL 14-56 [2] L-6 V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary GPT12E_CRIC 14-57 [2] GPT12E_KSCCFG 14-58 [2] GPT12E_T2,-T3,-T4 14-30 [2] GPT12E_T2/3/4IC 14-31 [2] GPT12E_T2CON 14-15 [2] GPT12E_T3CON 14-4 [2] GPT12E_T4CON 14-15 [2] GPT12E_T5,-T6 14-56 [2] GPT12E_T5/6IC 14-57 [2] GPT12E_T5CON 14-41 [2] GPT12E_T6CON 14-34 [2] Pn_IN 7-13 [1] Pn_IOCRx 7-14 [1] Pn_OMRH P10 7-11 [1] P2 7-11 [1] Pn_OMRL 7-11 [1] Pn_OUT 7-10 [1] Pn_POCON 7-8 [1] Ports Pn_IN 7-13 [1] Pn_IOCRx 7-14 [1] Pn_OMR 7-11 [1] PROCONx 3-62 [1] PSW 4-56 [1] Register Index I IDX0/1 4-46 [1] IMBCTRH 3-54 [1] IMBCTRL 3-52 [1] INTCTR 3-55 [1] IP 4-38 [1] Q QR0/1 4-45 [1] QX0/1 4-47 [1] M MAH 4-69 [1] MAL 4-68 [1] MAR 3-61 [1] MCW 4-65 [1] MDC 4-63 [1] MDH 4-62 [1] MDL 4-63 [1] MEM_KSCCFG 3-63 [1] MKMEM0/1 3-76 [1] MRW 4-72 [1] MSW 4-70 [1] R RELH/L 15-10 [2] RTC_CON 15-5 [2] RTC_IC 15-14 [2] RTC_ISNC 15-14 [2] RTC_KSCCFG 15-15 [2] RTC_RELH/L 15-10 [2] RTC_RTCH/L 15-9 [2] RTC_T14 15-8 [2] RTC_T14REL 15-8 [2] RTCH/L 15-9 [2] O ONES 4-74 [1] S SBRAM_DATA0 3-74 [1] SBRAM_DATA1 3-75 [1] SBRAM_RADD 3-72 [1] SBRAM_WADD 3-73 [1] SCU Registers DMPMIT 6-211 [1] DMPMITCLR 6-214 [1] ESRCFG0 6-61 [1] ESRCFG1 6-61 [1] ESRCFG2 6-61 [1] L-7 V1.0, 2007-06 P PECCx 5-20 [1] PECISNC 5-28 [1] PECON 3-78 [1] PECSEGx 5-24 [1] Pn_DIDIS P15 7-17 [1] P5 7-17 [1] User's Manual XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary ESRDAT 6-63 [1] ESREXCON1 6-58 [1] ESREXCON2 6-59 [1] EVR1CON0 6-118 [1] EVR1SET10V 6-123 [1] EVR1SET15VHP 6-125 [1] EVR1SET15VLP 6-124 [1] EVRMCON0 6-117 [1] EVRMCON1 6-119 [1] EVRMSET10V 6-120 [1] EVRMSET15VHP 6-122 [1] EVRMSET15VLP 6-121 [1] EXICON0 6-85 [1] EXICON1 6-85 [1] EXICON2 6-85 [1] EXICON3 6-85 [1] EXISEL 6-83 [1] EXOCON0 6-88 [1] EXOCON1 6-88 [1] EXOCON2 6-88 [1] EXOCON3 6-88 [1] EXTCON 6-31 [1] GSCEN 6-160 [1] GSCSTAT 6-163 [1] GSCSWREQ 6-160 [1] HPOSCCON 6-19 [1] IDCHIP 6-218 [1] IDMANUF 6-218 [1] IDMEM 6-219 [1] IDPROG 6-219 [1] INTCLR 6-192 [1] INTDIS 6-195 [1] INTNP0 6-196 [1] INTNP1 6-199 [1] INTSET 6-193 [1] INTSTAT 6-189 [1] ISSR 6-216 [1] PLLCON0 6-24 [1] PLLCON1 6-25 [1] PLLCON2 6-26 [1] PLLCON3 6-27 [1] PLLOSCCON 6-21 [1] PLLSTAT 6-22 [1] User's Manual L-8 Register Index PVC1CON0 6-100 [1] PVC1CONA1 6-106 [1] PVC1CONA2 6-106 [1] PVC1CONA3 6-106 [1] PVC1CONA4 6-106 [1] PVC1CONA5 6-106 [1] PVC1CONA6 6-106 [1] PVC1CONB1 6-112 [1] PVC1CONB3 6-112 [1] PVC1CONB4 6-112 [1] PVC1CONB5 6-112 [1] PVC1CONB6 6-112 [1] PVCMCON0 6-98 [1] PVCMCONA1 6-103 [1] PVCMCONA2 6-103 [1] PVCMCONA3 6-103 [1] PVCMCONA4 6-103 [1] PVCMCONA5 6-103 [1] PVCMCONA6 6-103 [1] PVCMCONB1 6-109 [1] PVCMCONB2 6-109 [1] PVCMCONB3 6-109 [1] PVCMCONB4 6-109 [1] PVCMCONB5 6-109 [1] PVCMCONB6 6-109 [1] RSTCNTCON 6-50 [1] RSTCON0 6-47 [1] RSTCON1 6-48 [1] RSTSTAT0 6-41 [1] RSTSTAT1 6-42 [1] RSTSTAT2 6-44 [1] RTCCLKCON 6-31 [1] SEQASTEP1 6-139 [1] SEQASTEP2 6-144 [1] SEQASTEP3 6-144 [1] SEQASTEP4 6-144 [1] SEQASTEP5 6-144 [1] SEQASTEP6 6-144 [1] SEQBSTEP1 6-147 [1] SEQBSTEP2 6-152 [1] SEQBSTEP3 6-152 [1] SEQBSTEP4 6-152 [1] SEQBSTEP5 6-152 [1] V1.0, 2007-06 XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary SEQBSTEP6 6-152 [1] SEQCON 6-134 [1] SLC 6-183 [1] SLS 6-184 [1] STATCLR0 6-29 [1] STATCLR1 6-30 [1] STEP0 6-136 [1] SWDCON0 6-94 [1] SWDCON1 6-95 [1] SWRSTCON 6-51 [1] SYSCON0 6-28 [1] SYSCON1 6-185 [1] TCCR 6-166 [1] TCLR 6-167 [1] TRAPCLR 6-204 [1], 6-205 [1] TRAPDIS 6-206 [1] TRAPNP 6-207 [1] TRAPSTAT 6-202 [1] WDTCS 6-173 [1] WDTREL 6-173 [1] WDTTIM 6-175 [1] WICR 6-178 [1] WUCR 6-178 [1] WUOSCCON 6-18 [1] SCU_STSTAT 6-46 [1] SP 4-53 [1] SPSEG 4-53 [1] SRCPx 5-24 [1] STKOV 4-55 [1] STKUN 4-55 [1] STSTAT 6-46 [1] T6CON 14-34 [2] T7IC 17-10 [2] T8IC 17-10 [2] TCONCS0 9-16 [1] TCONCS1/2/3/4 9-17 [1] TFR 5-43 [1] Register Index U USIC_BRGH 19-53 [2] USIC_BRGL 19-51 [2] USIC_BYP 19-91 [2] USIC_BYPCRH 19-93 [2] USIC_BYPCRL 19-91 [2] USIC_CCFG 19-31 [2] USIC_CCR 19-28 [2] USIC_DXxCR 19-42 [2] USIC_FDRH 19-50 [2] USIC_FDRL 19-49 [2] USIC_FMRH 19-71 [2] USIC_FMRL 19-70 [2] USIC_INPRH 19-36 [2] USIC_INPRL 19-35 [2] USIC_INx 19-107 [2] USIC_KSCFG 19-33 [2] USIC_OUTDRH 19-109 [2] USIC_OUTDRL 19-109 [2] USIC_OUTRH 19-108 [2] USIC_OUTRL 19-108 [2] USIC_PCRH 19-37 [2] USIC_PCRL 19-37 [2] USIC_PSCR 19-39 [2] USIC_PSR 19-38 [2] USIC_RBCTRH 19-103 [2] USIC_RBCTRL 19-103 [2] USIC_RBUF 19-79 [2] USIC_RBUF0 19-73 [2] USIC_RBUF01SRH 19-76 [2] USIC_RBUF01SRL 19-73 [2] USIC_RBUF1 19-76 [2] USIC_RBUFD 19-79 [2] USIC_RBUFSR 19-80 [2] USIC_SCTRH 19-62 [2] USIC_SCTRL 19-60 [2] L-9 V1.0, 2007-06 T T14 15-8 [2] T14REL 15-8 [2] T2, T3, T4 14-30 [2] T2/3/4IC 14-31 [2] T2CON 14-15 [2] T3CON 14-4 [2] T4CON 14-15 [2] T5, T6 14-56 [2] T5/6IC 14-57 [2] T5CON 14-41 [2] User's Manual XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Preliminary USIC_TBCTRH 19-100 [2] USIC_TBCTRL 19-100 [2] USIC_TBUFx 19-72 [2] USIC_TCSRH 19-68 [2] USIC_TCSRL 19-63 [2] USIC_TRBPTRH 19-110 [2] USIC_TRBPTRL 19-110 [2] USIC_TRBSCR 19-98 [2] USIC_TRBSRH 19-97 [2] USIC_TRBSRL 19-94 [2] Register Index V VECSEG 5-11 [1] X xxIC (gen.) 5-6 [1] Z ZEROS 4-74 [1] User's Manual L-10 V1.0, 2007-06 www.infineon.com Published by Infineon Technologies AG |
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